diff --git a/bin/run_embench.py b/bin/run_embench.py index 6523552922..8f92ff436c 100755 --- a/bin/run_embench.py +++ b/bin/run_embench.py @@ -190,6 +190,7 @@ def main(): f'--ldflags=-T{paths["bsp"]}/link.ld', f'--builddir={args.builddir}', f'--logdir={args.logdir}', + f'--timeout=15', '--clean'] logger.info(f"Calling build script: {' '.join(cmd)}") try: diff --git a/bin/run_many b/bin/run_many index 85d42c4b23..5b3f9e36ed 100755 --- a/bin/run_many +++ b/bin/run_many @@ -7,34 +7,48 @@ # Uses a different seed for each run. # Generates the same "make test" command generated by the "ci_check" script. # -# Usage: run_many [test-program] [simulator] [nruns] -# For example, "run_many hello-world vcs 2" will run the hello-world +# Usage: run_many [cfg] [test-program] [simulator] [nruns] [user_flags] +# For example, "run_many default hello-world vcs 2" will run the hello-world # test-program with VCS twice. # # TODO: command-line argument processing is primitive. if [ $# -gt 0 ] then - TESTPROGRAM=$1 + CFG=$1 else - TESTPROGRAM=hello-world + CFG=default fi if [ $# -gt 1 ] then - SIM=$2 + TESTPROGRAM=$2 else - SIM=vcs + TESTPROGRAM=hello-world fi if [ $# -gt 2 ] then - RUNS=$3 + SIM=$3 +else + SIM=vcs +fi + +if [ $# -gt 3 ] +then + RUNS=$4 else RUNS=2 fi let RUNSM1=$RUNS-1 +if [ $# -gt 4 ] +then + USER_FLAGS=$5 +else + USER_FLAGS= +fi + if [[ -z "${CV_CORE}" ]]; then echo CV_CORE not defined... cannot proceed. @@ -56,8 +70,8 @@ counter=0 until [ $counter -gt $RUNSM1 ] do THISSEED=`date +%N` - echo "make test SEED=$THISSEED TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO" - make test SEED=$THISSEED TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO + echo "make test CFG=$CFG TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO SEED=$THISSEED VSIM_USER_FLAGS=$USER_FLAGS" + make test CFG=$CFG TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO SEED=$THISSEED VSIM_USER_FLAGS=$USER_FLAGS ((counter++)) done diff --git a/bin/templates/regress_rmdb.j2 b/bin/templates/regress_rmdb.j2 index 4aba954d56..7fa6ce2c77 100644 --- a/bin/templates/regress_rmdb.j2 +++ b/bin/templates/regress_rmdb.j2 @@ -61,7 +61,10 @@ - proc getSeeds { num mode regr_name } { + proc getSeeds { num mode regr_name seed_value } { + if { $seed_value != "" } { + return $seed_value + } if {[string equal $mode "FIXED"]} { return [GetRandomValues $num] } @@ -141,6 +144,7 @@ + {% for build in r.get_builds() %} @@ -158,8 +162,8 @@ {% endfor %} - echo "BUILD RUNCMD: {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}}" - cd {{build.abs_dir}} && {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}} + echo "BUILD RUNCMD: {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} ENABLE_TRACE_LOG=NO USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}}" + cd {{build.abs_dir}} && {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} ENABLE_TRACE_LOG=NO USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}} {% endfor %} @@ -182,7 +186,7 @@ [getTestCfgName "(%t_test_cfg:%)"] [getParameterByPriorityYesOrNo "{{iss}}" "{{t.iss}}" "(%build_iss:%)"] [getParameterByPriorityYesOrNo "{{coverage}}" "{{t.cov}}" "(%build_cov:%)"] - [getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)"] + [getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)" "{{t.seed}}"] [file join "(%results_sim_path%)" "(%t_cfg%)" "{{t.testname}}" "(%t_test_cfg_name:%)" (%t_iteration%)] [getTestName "{{t.testname}}" "(%t_cfg%)" "(%t_test_cfg_name:%)" (%t_iteration%)] [getUCDBFilename "{{t.testname}}" "(%t_test_cfg_name:%)"] @@ -199,6 +203,7 @@ {% endfor %} + {% if lsf != None %} @@ -206,7 +211,7 @@ {% endif %} - echo " TEST RUNCMD: (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} COMP=0 CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%)" + echo " TEST RUNCMD: (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%)" echo " logfile: (%log_file%)" echo " RTL repo: CV_CORE_REPO : ${CV_CORE_REPO}" echo " CV_CORE_BRANCH: ${CV_CORE_BRANCH}" diff --git a/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40P_F-Zfinx-instructions.xlsx b/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40P_F-Zfinx-instructions.xlsx index b5cf28e4bf..dc6b1124d6 100644 Binary files a/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40P_F-Zfinx-instructions.xlsx and b/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40P_F-Zfinx-instructions.xlsx differ diff --git a/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_FPU_register_file.xlsx b/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_FPU_register_file.xlsx index a420314100..766c02b2e1 100644 Binary files a/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_FPU_register_file.xlsx and b/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_FPU_register_file.xlsx differ diff --git a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv index aa66013e7e..415b1cb1cb 100644 --- a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv +++ b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv @@ -230,7 +230,7 @@ class cv32e40p_instr extends riscv_instr; // special overrides for xcorev // for ALU, there exists variations for R and S types - if (category == ALU) begin + if (category inside {ALU,MAC}) begin if (instr_name inside {CV_CLIP, CV_CLIPU}) has_imm = 1'b1; if (format == S_FORMAT) has_rd = 1'b1; end @@ -698,7 +698,7 @@ class cv32e40p_instr extends riscv_instr; imm_str = $sformatf("%0d", $signed(imm[5:0])); end end else - super.update_imm_str(); + super.update_imm_str(); endfunction // `include "isa/riscv_instr_cov.svh" diff --git a/cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv b/cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv index 514c86a0fb..d62c51aa3b 100644 --- a/cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv +++ b/cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv @@ -415,6 +415,7 @@ class riscv_instr_gen_config extends uvm_object; if (fix_sp) { sp == SP; } + sp dist {SP := 15, [TP:T6] := 1}; // higher change assign to reg x2 sp != tp; !(sp inside {GP, RA, ZERO}); !(tp inside {GP, RA, ZERO}); diff --git a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv index 299874fbaa..f0283a00c0 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv @@ -33,14 +33,20 @@ // - gen_instr_fault_handler() // - gen_load_fault_handler() // - gen_store_fault_handler() +// - gen_init_section() //----------------------------------------------------------------------------------------- class cv32e40p_asm_program_gen extends corev_asm_program_gen; + cv32e40p_instr_gen_config corev_cfg; + `uvm_object_utils(cv32e40p_asm_program_gen) function new (string name = ""); super.new(name); + if(!uvm_config_db#(cv32e40p_instr_gen_config)::get(null,get_full_name(),"cv32e40p_instr_cfg", corev_cfg)) begin + `uvm_fatal(get_full_name(), "Cannot get cv32e40p_instr_gen_config") + end endfunction // Override the gen_trap_handler_section function from riscv_asm_program_gen.sv @@ -54,9 +60,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; bit is_interrupt = 'b1; string tvec_name; string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") if (cfg.mtvec_mode == VECTORED) begin gen_interrupt_vector_table(hart, mode, status, cause, ie, ip, scratch, instr); @@ -166,8 +169,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // software interrupts, are vectored to the same location as synchronous exceptions. This // ambiguity does not arise in practice, since user-mode software interrupts are either // disabled or delegated - cv32e40p_instr_gen_config corev_cfg; - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") instr = {instr, ".option norvc;", $sformatf("j %0s%0smode_exception_handler", hart_prefix(hart), mode)}; @@ -250,9 +251,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; privileged_reg_t status, ip, ie, scratch; string interrupt_handler_instr[$]; - cv32e40p_instr_gen_config corev_cfg; - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") - ls_unit = (XLEN == 32) ? "w" : "d"; if (mode < cfg.init_privileged_mode) return; if (mode == USER_MODE && !riscv_instr_pkg::support_umode_trap) return; @@ -406,14 +404,12 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; string str; string reg_name; bit [DATA_WIDTH-1:0] reg_val; - cv32e40p_instr_gen_config cfg_corev; bit [31:0] imm; - `DV_CHECK($cast(cfg_corev, cfg)) // Init general purpose registers with random values for(int i = 0; i < NUM_GPR; i++) begin if (i inside {cfg.sp, cfg.tp}) continue; - if (cfg.gen_debug_section && (i inside {cfg_corev.dp})) continue; + if (cfg.gen_debug_section && (i inside {corev_cfg.dp})) continue; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(reg_val, reg_val dist { @@ -429,23 +425,23 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; //after initializing all gprs, for zfinx extention tests again initialize //gprs for floating point instructions if(RV32ZFINX inside {supported_isa}) begin - foreach(cfg_corev.zfinx_reserved_gpr[i]) begin - if (cfg_corev.zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP}) continue; + foreach(corev_cfg.zfinx_reserved_gpr[i]) begin + if (corev_cfg.zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP}) continue; imm = get_rand_spf_value(); - reg_name = cfg_corev.zfinx_reserved_gpr[i].name(); + reg_name = corev_cfg.zfinx_reserved_gpr[i].name(); str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), imm); instr_stream.push_back(str); end end // Initialize reserved registers for store instr - if (!cfg_corev.no_load_store) begin - reg_name = cfg_corev.str_rs1.name(); + if (!corev_cfg.no_load_store) begin + reg_name = corev_cfg.str_rs1.name(); reg_val = 32'h80000000; // FIXME : Remove hardcoded value to allow configuration based on linker str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), reg_val); instr_stream.push_back(str); - reg_name = cfg_corev.str_rs3.name(); + reg_name = corev_cfg.str_rs3.name(); reg_val = $urandom_range(0,255); // FIXME : include negative also str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), reg_val); instr_stream.push_back(str); @@ -464,9 +460,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; string opts[$]; int dir_stream_id = 0; - cv32e40p_instr_gen_config corev_cfg; - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") - if(corev_cfg.insert_rand_directed_instr_stream) begin //test_rand_directed_instr_stream_num specify the total num of rand_* streams to select from dir_stream_id = $urandom_range(0,corev_cfg.test_rand_directed_instr_stream_num-1); @@ -527,17 +520,16 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack // With RV32X enabled, check for ecall instr on the last instr of hwloop // If true, then - // (a) Set MEPC to first instr of hwloop body - // (b) Add logic to decrement the LPCOUNT + // (a) Set MEPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment MEPC by 4 virtual function void gen_ecall_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin instr = {instr, - `COMMON_HWLOOP_EXC_HANDLING_CODE + `COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(cfg.gpr[0],cfg.gpr[1],MEPC) }; end else begin instr = {instr, @@ -555,19 +547,18 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack // With RV32X enabled, check for ebreak instr on the last instr of hwloop // If true, then - // (a) Set MEPC to first instr of hwloop body - // (b) Add logic to decrement the LPCOUNT + // (a) Set MEPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment MEPC by 4 virtual function void gen_ebreak_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, EBREAK_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin instr = {instr, - `COMMON_HWLOOP_EXC_HANDLING_CODE + `COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(cfg.gpr[0],cfg.gpr[1],MEPC) }; end else begin instr = {instr, @@ -586,19 +577,18 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack // With RV32X enabled, check for illegal instr on the last instr of hwloop // If true, then - // (a) Set MEPC to first instr of hwloop body - // (b) Add logic to decrement the LPCOUNT + // (a) Set MEPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment MEPC by 4 virtual function void gen_illegal_instr_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, ILLEGAL_INSTR_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin instr = {instr, - `COMMON_HWLOOP_EXC_HANDLING_CODE + `COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(cfg.gpr[0],cfg.gpr[1],MEPC) }; end else begin instr = {instr, @@ -617,9 +607,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack virtual function void gen_instr_fault_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, INSTR_FAULT_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); @@ -638,9 +625,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack virtual function void gen_load_fault_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, LOAD_FAULT_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); @@ -659,9 +643,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack virtual function void gen_store_fault_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, STORE_FAULT_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); @@ -676,4 +657,51 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; gen_section(get_label("store_fault_handler", hart), instr); endfunction + // Function to initialize GPR reserved for stores + virtual function void init_str_reserved_gpr(); + string str; + string reg_name; + bit [DATA_WIDTH-1:0] reg_val; + // Initialize reserved registers for store instr + if (!corev_cfg.no_load_store) begin + reg_name = corev_cfg.str_rs1.name(); + reg_val = 32'h80000000; // FIXME : Remove hardcoded value to allow configuration based on linker + str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), reg_val); + instr_stream.push_back(str); + + reg_name = corev_cfg.str_rs3.name(); + reg_val = $urandom_range(0,255); // FIXME : include negative also + str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), reg_val); + instr_stream.push_back(str); + end + endfunction + + // Override gen_init_section + // Add init_str_reserved_gpr() before other fpr/gpr initialization + virtual function void gen_init_section(int hart); + string str; + str = format_string(get_label("init:", hart), LABEL_STR_LEN); + instr_stream.push_back(str); + + // First initialize the store reserved register to minimize issues due to random stores + init_str_reserved_gpr(); + + if (cfg.enable_floating_point) begin + init_floating_point_gpr(); + end + init_gpr(); + // Init stack pointer to point to the end of the user stack + str = {indent, $sformatf("la x%0d, %0suser_stack_end", cfg.sp, hart_prefix(hart))}; + instr_stream.push_back(str); + if (cfg.enable_vector_extension) begin + randomize_vec_gpr_and_csr(); + end + core_is_initialized(); + gen_dummy_csr_write(); // TODO add a way to disable xStatus read + if (riscv_instr_pkg::support_pmp) begin + str = {indent, "j main"}; + instr_stream.push_back(str); + end + endfunction + endclass : cv32e40p_asm_program_gen diff --git a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv index c828b7395b..855202e7e1 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv @@ -107,6 +107,8 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; gen_single_step_logic(); end gen_dpc_update(); + init_dbg_rom_str_reserved_gpr(); + // write DCSR to the testbench for any analysis gen_signature_handshake(.instr(debug_main), .signature_type(WRITE_CSR), .csr(DCSR)); if (cfg.enable_ebreak_in_debug_rom || cfg.set_dcsr_ebreak) begin @@ -172,7 +174,26 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; // Insert section info so linker can place // debug exception code at the correct adress instr_stream.push_back(".section .debugger_exception, \"ax\""); - super.gen_debug_exception_handler(); + + // In CV32E40P there is no way to know the Instruction address + // that caused the debug exception entry. + // In these tests, this scenario is simply handled with assumptions: + // - The random illegal exception in debug program is generated + // as part of random instructions + // - And debug stack pointer is not used in any other random + // instruction in debug program + // With these 2 assumptions to ensure smooth continuity of rest of + // the test program, we simply jump to "debug_end" section to exit + // the debug rom properly. + + if (cfg.gen_debug_section) begin + str = {$sformatf("la x%0d, debug_end", cfg.scratch_reg), + $sformatf("jalr x0, x%0d, 0", cfg.scratch_reg), + "dret"}; + gen_section($sformatf("%0sdebug_exception", hart_prefix(hart)), str); + end else begin + super.gen_debug_exception_handler(); + end // Inser section info to place remaining code in the // original section @@ -342,5 +363,56 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; gen_signature_handshake(.instr(debug_main), .signature_type(WRITE_CSR), .csr(DSCRATCH0)); endfunction + // Override base class gen_dpc_update() + // Check dcsr.cause, for ebreak as debug entry cause. + // With RV32X enabled, check for ebreak instr on the last instr of hwloop + // If true, then + // (a) Set DPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment DPC by 4 + // as ebreak will set set dpc to its own address, which will cause an + // infinite loop. + virtual function void gen_dpc_update(); + str = {$sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DCSR), + $sformatf("slli x%0d, x%0d, 0x17", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("srli x%0d, x%0d, 0x1d", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("li x%0d, 0x1", cfg.gpr[0]), + $sformatf("bne x%0d, x%0d, 8f", cfg.scratch_reg, cfg.gpr[0])}; + debug_main = {debug_main, str}; + + if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin + str = { + `COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(cfg.gpr[0], cfg.scratch_reg, DPC) + }; + debug_main = {debug_main, str}; + str = {"8: nop"}; + debug_main = {debug_main, str}; + end else begin + increment_csr(DPC, 4, debug_main); + str = {"8: nop"}; + debug_main = {debug_main, str}; + end + endfunction + + // Function to initialize GPR reserved for stores + virtual function void init_dbg_rom_str_reserved_gpr(); + string reg_name; + bit [31:0] reg_val; + + // Initialize reserved registers for store instr + if (!cfg_corev.no_load_store) begin + reg_name = cfg_corev.str_rs1.name(); + reg_val = 32'h88000000; // FIXME : Remove hardcoded value to allow configuration based on linker + str = {$sformatf("li %0s, 0x%0x", reg_name.tolower(), reg_val)}; + debug_main = {debug_main, str}; + + reg_name = cfg_corev.str_rs3.name(); + reg_val = $urandom_range(0,255); // FIXME : include negative also + str = {$sformatf("li %0s, 0x%0x", reg_name.tolower(), reg_val)}; + debug_main = {debug_main, str}; + end + endfunction + endclass : cv32e40p_debug_rom_gen diff --git a/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv b/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv index dcad5642e1..5a09bb73c2 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv @@ -35,6 +35,14 @@ class cv32e40p_illegal_instr extends riscv_illegal_instr; instr_bin[31:20] != 'h7AA; // SCONTEXT } + constraint reserved_when_rv32FC_c { + if (riscv_instr_pkg::RV32FC inside {riscv_instr_pkg::supported_isa}) { + if (exception == kReservedCompressedInstr) { + reserved_c != kReservedLdsp; + } + } + } + `uvm_object_utils(cv32e40p_illegal_instr); function new(string name=""); diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv index a22508508b..3756295b06 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv @@ -175,12 +175,6 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence; instr_stream.instr_list[i].has_label = 1'b0; end end - // Remove all pulp store instructions inside debug_program - if(is_debug_program == 1) begin - if (instr_stream.instr_list[i].instr_name inside {CV_SB, CV_SH, CV_SW} ) begin - instr_stream.instr_list.delete(i); - end - end i++; end // while `uvm_info(get_full_name(), "Finished post-processing instructions", UVM_HIGH) diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv index eef1415f43..023ee982b0 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv @@ -28,68 +28,72 @@ package cv32e40p_instr_test_pkg; import corev_instr_test_pkg::*; - // MACRO for Common HWLOOP handling code for all the exception handlers + // MACRO for Common Exception Handling/Debug_Rom code for xEPC CSR management + // Including hwloop CSR management. (Used only with XPULP ISA support) + // // Common handler code to ensure all handlers use same code. // Description: // Check for expection (ecall/ebreak/illegal) on the last hwloop body instr // If true, then - // (a) Set MEPC to first instr of hwloop body - // (b) Add logic to decrement the LPCOUNT - `define COMMON_HWLOOP_EXC_HANDLING_CODE \ + // (a) Set xEPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment xEPC by 4 + `define COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(SCRATCH_REG0,SCRATCH_REG1,XEPC) \ /* Check LPCOUNT1 >= 1 */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT1), \ - $sformatf("li x%0d, 1", cfg.gpr[1]), \ - $sformatf("bge x%0d, x%0d, 1f", cfg.gpr[0], cfg.gpr[1]), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG0, LPCOUNT1), \ + $sformatf("li x%0d, 1", ``SCRATCH_REG1), \ + $sformatf("bge x%0d, x%0d, 1f", ``SCRATCH_REG0, ``SCRATCH_REG1), \ /* Check LPCOUNT0 >= 1 */ \ - $sformatf("2: csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT0), \ - $sformatf("li x%0d, 1", cfg.gpr[1]), \ - $sformatf("bge x%0d, x%0d, 3f", cfg.gpr[0], cfg.gpr[1]), \ + $sformatf("2: csrr x%0d, 0x%0x", ``SCRATCH_REG0, LPCOUNT0), \ + $sformatf("li x%0d, 1", ``SCRATCH_REG1), \ + $sformatf("bge x%0d, x%0d, 3f", ``SCRATCH_REG0, ``SCRATCH_REG1), \ /* Since both LPCOUNT0 & LPCOUNT1 equals 0 */ \ /* Nothing needs to be done for HWLOOPs and its CSRs */ \ $sformatf("beqz x0, 4f"), \ /* HWLOOP1 Handling */ \ /* Check for ILLEGAL being the LAST HWLOOP Body instr */ \ - $sformatf("1: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND1), \ - $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), \ - $sformatf("bne x%0d, x%0d, 2b", cfg.gpr[0], cfg.gpr[1]), \ + $sformatf("1: csrr x%0d, 0x%0x", ``SCRATCH_REG0, ``XEPC), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPEND1), \ + $sformatf("addi x%0d, x%0d, -4", ``SCRATCH_REG1, ``SCRATCH_REG1), \ + $sformatf("bne x%0d, x%0d, 2b", ``SCRATCH_REG0, ``SCRATCH_REG1), \ /* Else, If equal this means the illegal instr was the last */ \ /* hwloop body instr, thus we handle the HWLOOP manually here */ \ /* First decrement lpcount CSR manually as CSR not updated in HW */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT1), \ - $sformatf("addi x%0d, x%0d, -1", cfg.gpr[1], cfg.gpr[1]), \ - $sformatf("cv.count 1, x%0d", cfg.gpr[1]), \ - /* Check if the current LPCOUNT1 value == 0, if so, then MEPC=MEPC+4 */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT1), \ - $sformatf("beqz x%0d, 4f", cfg.gpr[1]), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPCOUNT1), \ + $sformatf("addi x%0d, x%0d, -1", ``SCRATCH_REG1, ``SCRATCH_REG1), \ + $sformatf("cv.count 1, x%0d", ``SCRATCH_REG1), \ + /* Check if the current LPCOUNT1 value == 0, if so, then xEPC=xEPC+4 */ \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPCOUNT1), \ + $sformatf("beqz x%0d, 4f", ``SCRATCH_REG1), \ /* Else LPCOUNT1 still >=1 and thus next, */ \ - /* Set the next MEPC to LPSTART1 for next HWLOOP iteration */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART1), \ + /* Set the next xEPC to LPSTART1 for next HWLOOP iteration */ \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG0, LPSTART1), \ $sformatf("beqz x0, 5f"), \ /* HWLOOP0 Handling */ \ /* Check for ILLEGAL being the LAST HWLOOP Body instr */ \ - $sformatf("3: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND0), \ - $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), \ - $sformatf("bne x%0d, x%0d, 4f", cfg.gpr[0], cfg.gpr[1]), \ + $sformatf("3: csrr x%0d, 0x%0x", ``SCRATCH_REG0, ``XEPC), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPEND0), \ + $sformatf("addi x%0d, x%0d, -4", ``SCRATCH_REG1, ``SCRATCH_REG1), \ + $sformatf("bne x%0d, x%0d, 4f", ``SCRATCH_REG0, ``SCRATCH_REG1), \ /* Else, If equal this means the illegal instr was the last */ \ /* hwloop body instr, thus we handle the HWLOOP manually here */ \ /* First decrement lpcount CSR manually as CSR not updated in HW */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT0), \ - $sformatf("addi x%0d, x%0d, -1", cfg.gpr[1], cfg.gpr[1]), \ - $sformatf("cv.count 0, x%0d", cfg.gpr[1]), \ - /* Check if the current LPCOUNT0 value == 0, if so, then MEPC=MEPC+4 */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT0), \ - $sformatf("beqz x%0d, 4f", cfg.gpr[1]), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPCOUNT0), \ + $sformatf("addi x%0d, x%0d, -1", ``SCRATCH_REG1, ``SCRATCH_REG1), \ + $sformatf("cv.count 0, x%0d", ``SCRATCH_REG1), \ + /* Check if the current LPCOUNT0 value == 0, if so, then xEPC=xEPC+4 */ \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPCOUNT0), \ + $sformatf("beqz x%0d, 4f", ``SCRATCH_REG1), \ /* Else LPCOUNT0 still >=1 and thus next, */ \ - /* Set the next MEPC to LPSTART0 for next HWLOOP iteration */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART0), \ + /* Set the next xEPC to LPSTART0 for next HWLOOP iteration */ \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG0, LPSTART0), \ $sformatf("beqz x0, 5f"), \ - /* Default increment for MEPC by 4 */ \ - $sformatf("4: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), \ - $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), \ - /* Write MEPC */ \ - $sformatf("5: csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]) + /* Default increment for xEPC by 4 */ \ + $sformatf("4: csrr x%0d, 0x%0x", ``SCRATCH_REG0, ``XEPC), \ + $sformatf("addi x%0d, x%0d, 4", ``SCRATCH_REG0, ``SCRATCH_REG0), \ + /* Write xEPC */ \ + $sformatf("5: csrw 0x%0x, x%0d", ``XEPC, ``SCRATCH_REG0) `include "cv32e40p_instr_gen_config.sv" diff --git a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv index 4d3b573608..a16141c3fa 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv @@ -27,6 +27,17 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; protected int idx_end[$]; protected int idx_min = 0; cv32e40p_instr_gen_config cv32e40p_cfg; + rand int unsigned default_avail_reg; + + constraint def_avail_reg_c { + if ((cfg.enable_fp_in_x_regs == 1) && (RV32ZFINX inside {riscv_instr_pkg::supported_isa})) { + default_avail_reg >= 8; + default_avail_reg <= (22 - cv32e40p_cfg.num_zfinx_reserved_reg); + } else { + default_avail_reg >= 8; + default_avail_reg <= 22; + } + } `uvm_object_utils(cv32e40p_rand_instr_stream) //`uvm_object_new @@ -155,12 +166,50 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; endfunction + // Override base class randomize_avail_regs function + // Add randomization for number of registers to be randomized + virtual function void randomize_avail_regs(); + std::randomize(default_avail_reg) with { if ((cfg.enable_fp_in_x_regs == 1) && (RV32ZFINX inside {riscv_instr_pkg::supported_isa})) { + default_avail_reg >= 8; + default_avail_reg <= (22 - cv32e40p_cfg.num_zfinx_reserved_reg); + } else { + default_avail_reg >= 8; + default_avail_reg <= 22; + } + }; + + avail_regs = new[default_avail_reg]; + if(avail_regs.size() > 0) begin + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(avail_regs, + unique{avail_regs}; + avail_regs[0] inside {[S0 : A5]}; + foreach(avail_regs[i]) { + !(avail_regs[i] inside {cfg.reserved_regs, reserved_rd}); + }, + "Cannot randomize avail_regs") + end + endfunction + + //Function: cv32e40p_rand_instr_stream::gen_instr() //override the parent class gen_instr() inside cv32e40p_rand_instr_stream virtual function void gen_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1, bit is_debug_program = 1'b0); setup_allowed_instr(no_branch, no_load_store); + // Need to randomize avail_regs[] to ensure the randomize_gpr() call + // actually randomize the registers for each instruction. + // And this also ensures the randomization is done separately for each + // program section. + // This also ensures reserved_regs get removed from gpr randomization + // for each instruction. + randomize_avail_regs(); + + `uvm_info("cv32e40p_rand_instr_stream", $sformatf("Randomized default_avail_reg = %d", default_avail_reg), UVM_DEBUG) + foreach(avail_regs[i]) begin + `uvm_info("cv32e40p_rand_instr_stream", $sformatf("Randomized avail_regs[%d] = %s", i, avail_regs[i]), UVM_DEBUG) + end + //Use this plusarg - include_xpulp_instr_in_debug_rom to include xpulp instr //In random debug_rom instructions. Added for v2 debug tests with xpulp. if (cv32e40p_cfg.xpulp_instr_in_debug_rom && is_debug_program && $test$plusargs("include_xpulp_instr_in_debug_rom")) begin @@ -170,6 +219,7 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; 1: randomize_debug_rom_instr(.instr(instr_list[i]), .is_in_debug(is_debug_program), .disable_dist()); 2: randomize_instr(instr_list[i], is_debug_program); endcase + store_instr_gpr_handling(instr_list[i]); end end else begin @@ -211,11 +261,20 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; exclude_instr = {exclude_instr, CV_BEQIMM, CV_BNEIMM, BEQ, BNE, BLT, BGE, BLTU, BGEU, C_BEQZ, C_BNEZ, JALR, JAL, C_JR, C_JALR, C_J, C_JAL}; end - exclude_instr = {exclude_instr, CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW, C_ADDI16SP, URET, SRET, MRET, DRET, ECALL}; + exclude_instr = {exclude_instr, CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW, C_ADDI16SP, C_SWSP, C_FSWSP, URET, SRET, MRET, DRET, ECALL}; instr = riscv_instr::get_rand_instr(.exclude_instr(exclude_instr)); instr.m_cfg = cfg; randomize_gpr(instr); endfunction + // Function to assign reserved reg for store instr from cfg to avoid random + // reg operands for stores which may result in corruption of instr memory + function void store_instr_gpr_handling(riscv_instr instr); + if (instr.instr_name inside {SB, SH, SW, C_SW, C_FSW, FSW, CV_SB, CV_SH, CV_SW}) begin + instr.rs1 = cv32e40p_cfg.str_rs1; + instr.rd = cv32e40p_cfg.str_rs3; + end + endfunction + endclass diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index 77a1dea937..7c608cdc0f 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -36,27 +36,28 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; `include "instr_lib/cv32e40p_float_instr_lib_defines.sv" // properties - start - string _header; - bit is_zfinx = riscv_instr_pkg::RV32ZFINX inside {riscv_instr_pkg::supported_isa}; - bit is_fp_instr, is_fpc_instr; - riscv_instr_name_t include_instr[]; - riscv_instr_name_t exclude_instr[]; - riscv_instr_category_t include_category[]; - riscv_instr_category_t exclude_category[]; - riscv_instr_group_t include_group[]; - riscv_instr_group_t exclude_group[]; - bit use_special_operand_patterns; // use special pattern opeands on directed instrs - bit use_fp_only_for_directed_instr; // use fp instr only as directed instrs in stream - bit use_no_repetitive_instr_per_stream; // directed instr is not allow to repeat in a stream - bit use_same_instr_per_stream; // same directed is use within a stream - bit use_prev_rd_on_next_operands; // previous instr rd is used for directed instr operands - bit use_diff_regs_for_operands = 0; // to control rand instr uses different registers for instr oeprands - bit more_weight_for_fdiv_fsqrt_gen; // more weight on generating fdiv and fsqrt directed_instr - bit init_gpr = (is_zfinx) ? 1 : 0; // initialize gpr registers in stream with rand value - bit init_fpr = (is_zfinx) ? 0 : 1; // initialize fpr registers in stream with rand value - bit en_clr_fflags_af_instr; // clear fflag to prevent residual fflags status of current f_instr - bit en_clr_fstate; // clean the fstate for current f_instr - bit include_load_store_base_sp; // include store instr that uses sp + string _header; + cv32e40p_instr_gen_config cfg_cv32e40p; + bit is_zfinx = riscv_instr_pkg::RV32ZFINX inside {riscv_instr_pkg::supported_isa}; + bit is_fp_instr, is_fpc_instr; + riscv_instr_name_t include_instr[]; + riscv_instr_name_t exclude_instr[]; + riscv_instr_category_t include_category[]; + riscv_instr_category_t exclude_category[]; + riscv_instr_group_t include_group[]; + riscv_instr_group_t exclude_group[]; + bit use_special_operand_patterns; // use special pattern opeands on directed instrs + bit use_fp_only_for_directed_instr; // use fp instr only as directed instrs in stream + bit use_no_repetitive_instr_per_stream; // directed instr is not allow to repeat in a stream + bit use_same_instr_per_stream; // same directed is use within a stream + bit use_prev_rd_on_next_operands; // previous instr rd is used for directed instr operands + bit use_diff_regs_for_operands = 0; // to control rand instr uses different registers for instr oeprands + bit more_weight_for_fdiv_fsqrt_gen; // more weight on generating fdiv and fsqrt directed_instr + bit init_gpr = (is_zfinx) ? 1 : 0; // initialize gpr registers in stream with rand value + bit init_fpr = (is_zfinx) ? 0 : 1; // initialize fpr registers in stream with rand value + bit en_clr_fflags_af_instr; // clear fflag to prevent residual fflags status of current f_instr + bit en_clr_fstate; // clean the fstate for current f_instr + bit include_load_store_base_sp; // include store instr that uses sp // for use_prev_rd_on_next_operands implementation usage - start riscv_reg_t prev_rd; @@ -116,7 +117,11 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; soft avail_gp_regs[i][0] inside {[S0:A5]}; // MUST: RV32C only uses 8 most common xregs soft avail_gp_regs[i][1] inside {SP}; // MUST: some random instr uses SP as rd foreach (avail_gp_regs[i][j]) { + if (cfg.gen_debug_section) { + !(avail_gp_regs[i][j] inside {cfg.reserved_regs, reserved_rd, gp_reg_scratch, gp_reg_sp, cfg_cv32e40p.dp}); + } else { !(avail_gp_regs[i][j] inside {cfg.reserved_regs, reserved_rd, gp_reg_scratch, gp_reg_sp}); + } } } } @@ -176,6 +181,11 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; en_clr_fflags_af_instr = 1; en_clr_fstate = 0; include_load_store_base_sp = $urandom_range(1); + if (cfg.gen_debug_section) begin + if (!$cast(cfg_cv32e40p, cfg)) begin + `uvm_fatal(_header, $sformatf("pre_randomize - cfg_cv32e40p casting failed")); + end + end endfunction: pre_randomize function void post_randomize(); @@ -347,6 +357,11 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; logic [31:0] i_imm; for (int i=1; i<32; i++) begin riscv_reg_t i_gpr = riscv_reg_t'(i); + if (cfg.gen_debug_section) begin + if (i == int'(cfg_cv32e40p.dp)) begin + continue; + end + end rand_fp_val(i_imm); `SET_GPR_VALUE(i_gpr,i_imm); end @@ -1084,6 +1099,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i use_fp_only_for_directed_instr = 1; en_clr_fflags_af_instr = 0; use_same_instr_per_stream = 1; + include_load_store_base_sp = 1; // store sp is randomly used here endfunction: pre_randomize virtual function void act_post_directed_instr( @@ -1172,7 +1188,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i FADD_S, FSUB_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end FMUL_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end FMIN_S, FMAX_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end - FDIV_S, FSQRT_S: begin mc_instr_latency = $urandom_range(1,12); end // table 12.1 + FDIV_S, FSQRT_S: begin mc_instr_latency = $urandom_range(1,19); end // table 12.1 FSGNJ_S,FSGNJN_S, FSGNJX_S: begin mc_instr_latency = 1 + fpu_others_lat; end // table 12.1 FCVT_W_S, FCVT_WU_S: begin mc_instr_latency = 1 + fpu_others_lat; end FEQ_S, FLT_S, FLE_S: begin mc_instr_latency = 1 + fpu_others_lat; end @@ -1201,7 +1217,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i while (!(loop_cnt == 100) && rand_mc_latency > 0) begin int p_rand_mc_latency = rand_mc_latency; - bit skip = 0; + bit skip = 0, is_csr = 0; unique case ($urandom_range(0,1)) 0: begin : INSERT_INTEGER_COMPUTATION_INSTR rand_instr = new riscv_instr::get_rand_instr( @@ -1215,10 +1231,29 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i .include_instr(`RV32M_MULH_INSTR_LIST), .include_group({RV32M}) ); - if ((rand_mc_latency - 5) < 0) - skip = 1; - else - rand_mc_latency = rand_mc_latency - 5; // determistic + if ((rand_mc_latency - 5) < 0) skip = 1; + else rand_mc_latency = rand_mc_latency - 5; // determistic + end + 2: begin : INSERT_CSR_ACCCESS // exclude this option because csr access get stalled after mult apu insn + bit is_4mc = $urandom_range(1); + logic [11:0] addr_csr = (is_4mc) ? 12'h305 : 12'h340; // mtvec(4) : mscratch(1) + is_csr = 1; + rand_instr = new riscv_instr::get_rand_instr( + .include_instr({CSRRW}) + ); + rand_instr.set_rand_mode(); + rand_instr.csr_c.constraint_mode(0); + `DV_CHECK_RANDOMIZE_WITH_FATAL(rand_instr, + if (has_rs1) { + rs1 == local::gp_reg_scratch; + } + if (has_rd) { + rd == ZERO; + } + csr == local::addr_csr; + ) + if ((rand_mc_latency - 1 - is_4mc*3) < 0) skip = 1; + else rand_mc_latency = rand_mc_latency - 1 - is_4mc*3; end endcase if (!skip) begin @@ -1240,7 +1275,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i if (instr_f.has_rs2) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_f.rs2}); end if (instr_f.has_rd) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_f.rd}); end end - randomize_gpr(rand_instr); + if (!is_csr) randomize_gpr(rand_instr); instr_list.push_back(rand_instr); instr_list[$].comment = {instr_list[$].comment, $sformatf(" [rand_fill_mc_latency_w_instrs - %0d cycles] ", p_rand_mc_latency)}; reserved_rd.delete(); @@ -1431,7 +1466,7 @@ class cv32e40p_fp_op_fwd_instr_stream extends cv32e40p_float_zfinx_base_instr_st riscv_fp_in_x_regs_instr instr_zfinx; riscv_floating_point_instr instr_f; bit has_rd, has_rs1, has_rs2, has_rs3; - int unsigned loop_cnt, loop_limit = 50; + int unsigned loop_cnt, loop_limit = 100; if (!(i % num_of_instr_per_block)) begin : RESET_PRIOR_START_OF_BLOCK i_instr_list.delete(); @@ -1519,6 +1554,7 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b load_store_opt_t load_store_option=NULL; bit use_load_store_w_sp_only; bit use_compress_load_store_only; + bit use_post_inc_load_store; int unsigned num_of_load_store_instr; bit post_fp_src_is_load_dest; int unsigned cnt, cnt_limit=100; @@ -1540,8 +1576,18 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b en_clr_fflags_af_instr = 0; include_load_store_base_sp = 0; // do not reserved SP reserved_rd = new[reserved_rd.size()+1] ({reserved_rd, ZERO}); + use_post_inc_load_store = $urandom_range(1); endfunction: pre_randomize + virtual function void rand_fp_val(output logic [31:0] val); + if (!use_post_inc_load_store) super.rand_fp_val(val); + else begin + void'(std::randomize(val) with { + val[31:23] == 0; val[22:18] != 0; val[17:13] == 0; val[12:8] == 0; val[7:0] == 0; + }); + end + endfunction : rand_fp_val + virtual function void update_current_instr_arg_list(int idx=0); endfunction: update_current_instr_arg_list @@ -1633,8 +1679,8 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b rand_avail_fp_regs[j] inside {[FS0:FA5]}; } }); - avail_gp_regs[i] = rand_avail_gp_regs; - avail_fp_regs[i] = rand_avail_fp_regs; + avail_gp_regs[i] = rand_avail_gp_regs; // override c_avail_gp_regs + avail_fp_regs[i] = rand_avail_fp_regs; // override c_avail_gp_regs end @@ -1682,11 +1728,20 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b else exclude_instr = new[8] ({C_LW, C_SW, C_FLW, C_FSW, C_LWSP, C_SWSP, C_FLWSP, C_FSWSP}); if (use_load_store_w_sp_only && !is_zfinx) include_instr = new[4] ({C_LWSP, C_SWSP, C_FLWSP, C_FSWSP}); else if (use_load_store_w_sp_only && is_zfinx) include_instr = new[2] ({C_LWSP, C_SWSP}); - unique case (load_store_option) - STORE_ONLY : include_category = new[2] ({STORE, POST_INC_STORE}); - LOAD_ONLY : include_category = new[2] ({LOAD, POST_INC_LOAD}); - LOAD_STORE : include_category = new[4] ({LOAD, POST_INC_LOAD, STORE, POST_INC_STORE}); - endcase + if (use_post_inc_load_store) begin : INCLUDE_CV_LOAD_STORE + unique case (load_store_option) + STORE_ONLY : include_category = new[2] ({STORE, POST_INC_STORE}); + LOAD_ONLY : include_category = new[2] ({LOAD, POST_INC_LOAD}); + LOAD_STORE : include_category = new[4] ({LOAD, POST_INC_LOAD, STORE, POST_INC_STORE}); + endcase + end + else begin : EXCLUDE_CV_LOAD_STORE + unique case (load_store_option) + STORE_ONLY : include_category = new[1] ({STORE}); + LOAD_ONLY : include_category = new[1] ({LOAD}); + LOAD_STORE : include_category = new[2] ({LOAD, STORE}); + endcase + end // note: include_category cannot mixed with inclue_group else it will have no effect (group override cat) // if (!is_zfinx) include_group = new[4] ({RV32I, RV32C, RV32F, RV32FC}); // else include_group = new[3] ({RV32I, RV32C, RV32ZFINX}); @@ -1849,19 +1904,22 @@ endclass: cv32e40p_fp_op_fwd_instr_w_loadstore_stream // - // extended class that clce through all the fp instructions that change - // fs state from Initial->Dirty and Clean->Dirty - // fixme: assess and consider the feedback in https://github.com/XavierAubert/core-v-verif/pull/70 + // extended class that cycle through all the fp instructions that change fs state from Initial->Dirty and Clean->Dirty + // note: + // 1) transistion only valid for F but not ZFINX extension (During ZFINX, FS always in OFF state) + // 2) this test is similar to custom fpu_mstatus_test but is generated by corev-dv and have certain constraint randomizations + // todo: assess and consider the feedback in https://github.com/XavierAubert/core-v-verif/pull/70 class cv32e40p_mstatus_fs_stream extends cv32e40p_float_zfinx_base_instr_stream; - localparam LOOP_CNT_LIMIT = 2; // init->dirty, clean->dirty + int unsigned loop_cnt_limit = (is_zfinx) ? 1 : 2; int unsigned loop_cnt = 0; + int unsigned total_instr = (is_zfinx) ? TOTAL_INSTR_ZFINX_TYPE : (TOTAL_INSTR_F_TYPE+TOTAL_INSTR_FC_TYPE); `uvm_object_utils(cv32e40p_mstatus_fs_stream) `uvm_object_new constraint ovr_c_others { - num_of_instr_per_stream == (TOTAL_INSTR_F_TYPE+TOTAL_INSTR_FC_TYPE) * LOOP_CNT_LIMIT; + num_of_instr_per_stream == total_instr * loop_cnt_limit; } function void pre_randomize(); @@ -1870,7 +1928,7 @@ class cv32e40p_mstatus_fs_stream extends cv32e40p_float_zfinx_base_instr_stream; use_no_repetitive_instr_per_stream = 1; include_load_store_base_sp = 1; clr_csr_option = 0; // uses CSRRW - en_clr_fstate = (!is_zfinx & en_clr_fflags_af_instr & !clr_csr_option); + en_clr_fstate = (en_clr_fflags_af_instr & !clr_csr_option); csr_mstatus_fs = 32'd1; // Initial endfunction: pre_randomize @@ -1881,21 +1939,19 @@ class cv32e40p_mstatus_fs_stream extends cv32e40p_float_zfinx_base_instr_stream; endfunction : initialize_regs virtual function void update_current_instr_arg_list(int idx=0); - include_group = new[2] ({RV32F, RV32FC}); + + if (!is_zfinx) include_group = new[2] ({RV32F, RV32FC}); + else include_group = new[2] ({RV32ZFINX, RV32FC}); + if (idx == 0) loop_cnt++; - else if (idx != 0 && idx%(TOTAL_INSTR_F_TYPE+TOTAL_INSTR_FC_TYPE) == 0) begin + else if (idx != 0 && idx%total_instr == 0) begin loop_cnt++; - assert (loop_cnt <= LOOP_CNT_LIMIT); + assert (loop_cnt <= loop_cnt_limit); exclude_instr.delete(); csr_mstatus_fs = 32'd2; // Clean + clr_csr_init_done = 0; // Update csrrw_val end - // fixme : refine after https://github.com/Imperas/private-dolphindesigns-riscv/issues/15 is resolved - case (idx) - 0: include_instr = new[1] ({FLW}); - 1: include_instr = new[1] ({C_FLW}); - 2: include_instr = new[1] ({C_FLWSP}); - default: include_instr.delete(); - endcase + endfunction: update_current_instr_arg_list virtual function void add_instr_prior_directed_instr(riscv_instr instr, int idx=0); diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index 96e253e7ad..91c7db6157 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -73,7 +73,6 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; localparam MAX_HWLOOP_INSTR_GEN = 4095; - rand riscv_reg_t hwloop_avail_regs[]; rand bit[1:0] num_loops_active; rand bit gen_nested_loop; //nested or not-nested hwloop @@ -155,14 +154,43 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; } constraint gen_hwloop_count_c { + solve num_loops_active before gen_nested_loop; + solve gen_nested_loop before hwloop_count, hwloop_counti; + + num_loops_active inside {1,2}; + + if (num_loops_active > 1) { + // num_loops_active == 2 + if (gen_nested_loop) { + // nested loop + foreach (hwloop_count[i]) { + hwloop_count[i] inside {[0:10]}; // max 100*2 + hwloop_counti[i] inside {[0:10]}; + } + } else { + // single loop + foreach (hwloop_count[i]) { + hwloop_count[i] inside {[0:50]}; // max 50*2 + hwloop_counti[i] inside {[0:50]}; + } + } + } else { + // num_loops_active == 1 + if (gen_nested_loop) { + // nested loop + foreach (hwloop_count[i]) { + hwloop_count[i] inside {[0:15]}; // max 225 + hwloop_counti[i] inside {[0:15]}; + } + } else { + // single loop + foreach (hwloop_count[i]) { + hwloop_count[i] inside {[51:100]}; // max 100 + hwloop_counti[i] inside {[51:100]}; + } + } + } // num_loops_active - num_loops_active inside {1,2,3}; - - foreach(hwloop_counti[i]) - hwloop_counti[i] inside {[0:64]}; - - foreach(hwloop_count[i]) - hwloop_count[i] inside {[0:64]}; } constraint num_hwloop_instr_c { @@ -277,6 +305,34 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; `uvm_fatal(this.get_type_name(), "cv32e40p_exclude_regs out of range") end + // Ensure the illegal inserted in the sequence function cv32e40p_insert_illegal_hint_instr() + // does not violate the hwloop end label offset limits with cv.setupi instr + // As a workaround here if illegal_instr_ratio is non-zero, + // The number of instructions in hwloop are reduced by 3(Change if + // needed), to allow illegal/hint instr insertion in the sequence. + // The coverage here is not critical as the max range with cv.setupi + // will be exercised in tests without illegals. + if (cfg.illegal_instr_ratio > 0) begin + if(gen_nested_loop) begin + if (use_setup_inst[1] && use_loop_setupi_inst[1] && (num_hwloop_instr[1] >= 28)) begin + num_hwloop_instr[1] = num_hwloop_instr[1] - 3; + if (num_hwloop_instr[0] >= 6) + num_hwloop_instr[0] = num_hwloop_instr[0] - 3; + else + num_hwloop_instr[0] = 3; + end else if (use_setup_inst[0] && use_loop_setupi_inst[0] && (num_hwloop_instr[0] >= 28)) begin + num_hwloop_instr[0] = num_hwloop_instr[0] - 3; + end + end else begin + if (use_setup_inst[1] && use_loop_setupi_inst[1] && (num_hwloop_instr[1] >= 28)) begin + num_hwloop_instr[1] = num_hwloop_instr[1] - 3; + end + if (use_setup_inst[0] && use_loop_setupi_inst[0] && (num_hwloop_instr[0] >= 28)) begin + num_hwloop_instr[0] = num_hwloop_instr[0] - 3; + end + end + end + gen_xpulp_hwloop_control_instr(); endfunction : post_randomize @@ -1050,9 +1106,10 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; endclass : cv32e40p_xpulp_hwloop_base_stream -//Class: cv32e40p_xpulp_short_hwloop_stream +//Class: cv32e40p_xpulp_short_hwloop_stream[_directed] //Running with <= 20 instructions in HWLOOP -//Increase Loop Count range to excersize upto 4095 (12-bit) uimmL value +//Increase Loop Count range to excersize upto 1024 +//Cover high Loop Count upto 4096 (12-bit) uimmL value [for _directed] class cv32e40p_xpulp_short_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stream; rand bit loop0_high_count; @@ -1083,39 +1140,26 @@ class cv32e40p_xpulp_short_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stre num_loops_active inside {1}; + // For rs1 32 bit count (long setup), not planned to exercise whole range in these streams + // due to long run times if(gen_nested_loop) { if(loop0_high_count) { - hwloop_counti[0] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; - - hwloop_count[0] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; - - hwloop_counti[1] inside {[0:5]}; - hwloop_count[1] inside {[0:5]}; + hwloop_counti[0] dist {[0:400] := 50, [401:1023] := 5}; + hwloop_count[0] dist {[0:400] := 50, [401:1023] := 5}; + hwloop_counti[1] inside {[0:3]}; + hwloop_count[1] inside {[0:3]}; } else { - hwloop_counti[0] inside {[0:5]}; - hwloop_count[0] inside {[0:5]}; - - hwloop_counti[1] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; - - hwloop_count[1] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; + hwloop_counti[0] inside {[0:3]}; + hwloop_count[0] inside {[0:3]}; + hwloop_counti[1] dist {[0:400] := 50, [401:1023] := 5}; + hwloop_count[1] dist {[0:400] := 50, [401:1023] := 5}; } - - } else { foreach(hwloop_counti[i]) - hwloop_counti[i] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; - - //For rs1 32 bit count, not planned to exercise whole range in these streams - //due to long run times + hwloop_counti[i] dist {[0:400] := 50, [401:1023] := 5}; foreach(hwloop_count[i]) - hwloop_count[i] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; + hwloop_count[i] dist {[0:400] := 50, [401:1023] := 5}; } } @@ -1205,13 +1249,70 @@ class cv32e40p_xpulp_short_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stre endfunction : post_randomize endclass : cv32e40p_xpulp_short_hwloop_stream +// directed test for higher count/counti +class cv32e40p_xpulp_short_hwloop_stream_directed extends cv32e40p_xpulp_short_hwloop_stream; + + `uvm_object_utils_begin(cv32e40p_xpulp_short_hwloop_stream_directed) + `uvm_field_int(num_loops_active, UVM_DEFAULT) + `uvm_field_int(gen_nested_loop, UVM_DEFAULT) + `uvm_field_sarray_int(use_setup_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_counti_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_starti_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_endi_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_setupi_inst, UVM_DEFAULT) + `uvm_field_sarray_int(hwloop_count, UVM_DEFAULT) + `uvm_field_sarray_int(hwloop_counti, UVM_DEFAULT) + `uvm_field_sarray_int(num_hwloop_instr, UVM_DEFAULT) + `uvm_field_sarray_int(num_hwloop_ctrl_instr, UVM_DEFAULT) + `uvm_field_sarray_int(num_fill_instr_loop_ctrl_to_loop_start, UVM_DEFAULT) + `uvm_field_int(num_fill_instr_in_loop1_till_loop0_setup, UVM_DEFAULT) + `uvm_field_int(setup_l0_before_l1_start, UVM_DEFAULT) + `uvm_field_sarray_int(num_instr_cv_start_to_loop_start_label, UVM_DEFAULT) + `uvm_field_int(loop0_high_count, UVM_DEFAULT) + `uvm_object_utils_end + + constraint gen_hwloop_count_c { + + solve gen_nested_loop, loop0_high_count before hwloop_count, hwloop_counti; + solve gen_nested_loop before loop0_high_count; + + num_loops_active inside {1}; + + // higher count/counti will be covered in directed test to improve simtime + // For rs1 32 bit count (long setup), not planned to exercise whole range in these streams + // due to long run times + if(gen_nested_loop) { + if(loop0_high_count) { + hwloop_counti[0] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_count[0] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_counti[1] inside {[1:2]}; + hwloop_count[1] inside {[1:2]}; + } else { + hwloop_counti[0] inside {[1:2]}; + hwloop_count[0] inside {[1:2]}; + hwloop_counti[1] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_count[1] dist {[1024:4094] := 50, 4095 := 5}; + } + } else { + foreach(hwloop_counti[i]) + hwloop_counti[i] dist {[1024:4094] := 50, 4095 := 5}; + foreach(hwloop_count[i]) + hwloop_count[i] dist {[1024:4094] := 50, 4095 := 5}; + } + } + + function new(string name = "cv32e40p_xpulp_short_hwloop_stream_directed"); + super.new(name); + endfunction : new + +endclass : cv32e40p_xpulp_short_hwloop_stream_directed //Class: cv32e40p_xpulp_long_hwloop_stream //Running with large instruction number in HWLOOP upto 4094 corresponding to 12-bit uimmL for end label. //Max num inside HWLOOP body can be 4094 only as End label is on instruction after last instr of HWLOOP. -//Reduce Loop Count range to upto 50. -class cv32e40p_xpulp_long_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stream; +//Reduce Loop Count range to upto 25. +class cv32e40p_xpulp_long_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stream; // fixme `uvm_object_utils_begin(cv32e40p_xpulp_long_hwloop_stream) `uvm_field_int(num_loops_active, UVM_DEFAULT) @@ -1232,12 +1333,21 @@ class cv32e40p_xpulp_long_hwloop_stream extends cv32e40p_xpulp_hwloop_base_strea `uvm_object_utils_end constraint gen_hwloop_count_c { + solve num_hwloop_instr before hwloop_count, hwloop_counti; num_loops_active inside {1}; - foreach(hwloop_counti[i]) - hwloop_counti[i] inside {[0:25]}; + foreach(hwloop_counti[i]) { + if (num_hwloop_instr[i] < 200) hwloop_counti[i] inside {[0:25]}; + if (num_hwloop_instr[i] >= 200 && num_hwloop_instr[i] < 1000) hwloop_counti[i] inside {[0:10]}; + if (num_hwloop_instr[i] >= 1000 && num_hwloop_instr[i] < 1500) hwloop_counti[i] inside {[0:3]}; + if (num_hwloop_instr[i] >= 1500 ) hwloop_counti[i] inside {[0:2]}; + } - foreach(hwloop_count[i]) - hwloop_count[i] inside {[0:25]}; + foreach(hwloop_count[i]) { + if (num_hwloop_instr[i] < 200) hwloop_count[i] inside {[0:25]}; + if (num_hwloop_instr[i] >= 200 && num_hwloop_instr[i] < 1000) hwloop_count[i] inside {[0:10]}; + if (num_hwloop_instr[i] >= 1000 && num_hwloop_instr[i] < 1500) hwloop_count[i] inside {[0:3]}; + if (num_hwloop_instr[i] >= 1500 ) hwloop_count[i] inside {[0:2]}; + } } diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_instr_lib.sv index d5672c9d3b..cf4531a8a4 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_instr_lib.sv @@ -223,6 +223,10 @@ class cv32e40p_xpulp_rand_stream extends cv32e40p_base_instr_stream; if(no_floating_point_instr) riscv_exclude_group = {riscv_exclude_group, RV32F, RV32ZFINX}; + if(cfg.sp != SP) begin // prevent corruption due to sw(sp) + riscv_exclude_instr = {riscv_exclude_instr, C_SWSP, C_FSWSP}; + end + `uvm_info("cv32e40p_xpulp_rand_stream", $sformatf("Total XPULP+RISCV instr gen in test %0d + %0d",num_of_xpulp_instr,num_of_riscv_instr),UVM_HIGH) @@ -285,6 +289,7 @@ class cv32e40p_xpulp_rand_stream extends cv32e40p_base_instr_stream; end endcase + instr_list[$].comment = {$sformatf(" Inserted %0s - idx[%0d]", get_name(), i)}; i++; diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv index 519f0f6a12..2068dadb06 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv @@ -29,10 +29,12 @@ class uvme_cv32e40p_cov_model_c extends uvm_component; uvme_cv32e40p_cfg_c cfg; uvme_cv32e40p_cntxt_c cntxt; - uvme_rv32isa_covg isa_covg; - uvme_interrupt_covg interrupt_covg; - uvme_debug_covg debug_covg; - uvme_rv32x_hwloop_covg rv32x_hwloop_covg; + uvme_rv32isa_covg isa_covg; + uvme_interrupt_covg interrupt_covg; + uvme_debug_covg debug_covg; + uvme_rv32x_hwloop_covg rv32x_hwloop_covg; + uvme_cv32e40p_fp_instr_covg cv32e40p_fp_instr_covg; + uvme_cv32e40p_zfinx_instr_covg cv32e40p_zfinx_instr_covg; `uvm_component_utils_begin(uvme_cv32e40p_cov_model_c) `uvm_field_object(cfg , UVM_DEFAULT) @@ -113,6 +115,16 @@ function void uvme_cv32e40p_cov_model_c::build_phase(uvm_phase phase); rv32x_hwloop_covg = uvme_rv32x_hwloop_covg::type_id::create("rv32x_hwloop_covg", this); + if( (cfg.rv32f_fcov_en == 1) && (cfg.zfinx_fcov_en == 0) ) begin + cv32e40p_fp_instr_covg = uvme_cv32e40p_fp_instr_covg::type_id::create("cv32e40p_fp_instr_covg", this); + uvm_config_db#(uvme_cv32e40p_cntxt_c)::set(this, "cv32e40p_fp_instr_covg", "cntxt", cntxt); + end else if ( (cfg.zfinx_fcov_en == 1) && (cfg.rv32f_fcov_en == 0) ) begin + cv32e40p_zfinx_instr_covg = uvme_cv32e40p_zfinx_instr_covg::type_id::create("cv32e40p_zfinx_instr_covg", this); + uvm_config_db#(uvme_cv32e40p_cntxt_c)::set(this, "cv32e40p_zfinx_instr_covg", "cntxt", cntxt); + end else if ( (cfg.rv32f_fcov_en == 1) && (cfg.zfinx_fcov_en == 1) ) begin + `uvm_fatal("FCOV", "Illegal Config with FCOV enable for both RV32F and RV32ZFINX") + end + endfunction : build_phase function void uvme_cv32e40p_cov_model_c::connect_phase(uvm_phase phase); diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv new file mode 100644 index 0000000000..05fb95ee2e --- /dev/null +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv @@ -0,0 +1,817 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright 2023 OpenHW Group +// Copyright 2023 Dolphin Design +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// +/////////////////////////////////////////////////////////////////////////////// + +class uvme_cv32e40p_fp_instr_covg extends uvm_component; + /* + * Class members + */ + uvme_cv32e40p_cfg_c cfg; + uvme_cv32e40p_cntxt_c cntxt; + + `uvm_component_utils_begin(uvme_cv32e40p_fp_instr_covg) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + extern function new(string name = "cv32e40p_fp_instr_covg", uvm_component parent = null); + extern function void build_phase(uvm_phase phase); + extern task run_phase(uvm_phase phase); + extern task sample_clk_i(); + + `define FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES \ + illegal_bins clk_2_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 0) ); \ + illegal_bins clk_3_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 1) ); \ + illegal_bins clk_4_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2, 3}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 2) ); + + `define FPU_ZERO_LATENCY_ILLEGAL_BUSY \ + illegal_bins apu_busy_curr_apu_op_not_div_sqrt = ( !binsof(cp_curr_fpu_apu_op_multicycle) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ + with ( ((cp_curr_fpu_apu_op_multicycle + 1) * (fpu_latency == 0)) != 0 ); + + `define IGNORE_BINS_NON_FD_F_INSTR \ + ignore_bins non_fd_f_inst = binsof(cp_curr_fpu_apu_op) intersect {`APU_INSTR_WITH_NO_FD}; + + `define IGNORE_BINS_ZERO_LAT_FPU_OP \ + ignore_bins zero_lat_inst = ( !binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ + with ( ((cp_curr_fpu_apu_op + 1) * (fpu_latency == 0)) != 0 ); + + `define IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU \ + ignore_bins in_contention_lsu_wr = ( binsof(cp_apu_contention) intersect {1} ) \ + with ( ((cp_curr_fpu_apu_op + 1) * (fpu_latency == 1)) != 0 ); + + `define IGNORE_BINS_NON_FS3_F_INSTR \ + ignore_bins non_fs3_f_inst = !binsof(cp_id_stage_f_inst) intersect {`RV32F_INSTR_WITH_NO_FS3}; + + `define IGNORE_BINS_NON_RD_F_INSTR \ + ignore_bins non_rd_f_inst = !binsof(cp_curr_fpu_apu_op) intersect {`APU_INSTR_WITH_NO_FD}; + + `define IGNORE_BINS_NON_RS_F_INSTR_IN_ID \ + ignore_bins non_rs_id_stage_f_inst = !binsof(cp_id_stage_f_inst) intersect {APU_OP_I2F, APU_OP_I2F_U}; + + `define IGNORE_BINS_NON_RS1_CV32E40P_INSTR \ + ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL}; + + `define IGNORE_BINS_NON_RS2_CV32E40P_INSTR \ + ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_INSTR_WITH_NO_RS2}; + + `define IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE \ + ignore_bins non_stalled_contention_wr_state = binsof(cp_contention_state) intersect {0,1}; + + `define IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION \ + ignore_bins non_fd_f_inst = binsof(cp_last_fpu_apu_op_at_contention) intersect {`APU_INSTR_WITH_NO_FD}; + + `define IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR \ + ignore_bins contention_at_lsu_wr = binsof(cp_apu_contention) intersect {1}; + + `define IGNORE_BINS_NON_RD_F_INSTR_AT_CONTENTION \ + ignore_bins non_rd_f_inst = !binsof(cp_last_fpu_apu_op_at_contention) intersect {`APU_INSTR_WITH_NO_FD}; + + `define IGNORE_BINS_NO_CONTENTION \ + ignore_bins no_contention = binsof(cp_apu_contention) intersect {1}; + + `define IGNORE_BINS_NO_CONTENTION_LSU \ + ignore_bins no_contention_lsu_wr = binsof(cp_apu_contention) intersect {0}; + + /* + * Covergroups + */ + + covergroup cg_f_multicycle(int fpu_latency); + `per_instance_fcov + option.at_least = 10; + + cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + `RV32F_INSTR_BINS + option.weight = 5; + } + + cp_id_stage_apu_op_ex_o : coverpoint `COVIF_CB.id_stage_apu_op_ex_o iff (`COVIF_CB.id_stage_apu_en_ex_o == 1) { + `FPU_OP_BINS + option.weight = 5; + } + + cp_f_multicycle_clk_window : coverpoint cntxt.cov_vif.if_clk_cycle_window iff ((`COVIF_CB.is_mulh_ex == 0) && + (`COVIF_CB.is_misaligned_data_req_ex == 0) && + (`COVIF_CB.is_post_inc_ld_st_inst_ex == 0) && + (`COVIF_CB.ex_apu_valid_memorised == 0)) { + bins clk1 = {1}; + bins clk2 = {2}; + bins clk3 = {3}; + bins clk4 = {4}; + bins clk5 = {5}; + bins clk6 = {6}; + bins clk7 = {7}; + bins clk8 = {8}; + bins clk9 = {9}; + bins clk10 = {10}; + bins clk11 = {11}; + bins clk12 = {12}; + bins clk13 = {13}; + bins clk14 = {14}; + bins clk15 = {15}; + bins clk16 = {16}; + bins clk17 = {17}; + bins clk18 = {18}; + bins clk19 = {19}; + ignore_bins ignore_idle = {0}; + illegal_bins clk_more_than_19 = {[20:31]}; + } + + cp_id_stage_inst_valid : coverpoint `COVIF_CB.id_stage_instr_valid_i { + bins id_stage_instr_valid = {1}; + option.weight = 1; + } + + cp_id_stage_apu_en_ex_o : coverpoint `COVIF_CB.id_stage_apu_en_ex_o { + bins id_stage_apu_en_ex_1 = {1}; + bins id_stage_apu_en_ex_0_to_1 = (0 => 1); + option.weight = 1; + } + + cp_apu_req_valid : coverpoint `COVIF_CB.apu_req { + bins apu_req_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_grant_valid : coverpoint `COVIF_CB.apu_gnt { + bins apu_gnt_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_busy : coverpoint `COVIF_CB.apu_busy { + bins apu_busy_high = {1'b1}; + option.weight = 1; + } + + cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { + `FPU_OP_BINS + option.weight = 5; + } + + cp_curr_fpu_apu_op_at_apu_req : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) ) + { + `FPU_OP_BINS + option.weight = 5; + } + + cp_curr_fpu_apu_op_multicycle : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff (`COVIF_CB.apu_busy == 1) + { + `FPU_OP_BINS + option.weight = 5; + } + + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall : coverpoint ((`COVIF_CB.is_mulh_ex == 0) && + (`COVIF_CB.is_misaligned_data_req_ex == 0) && + (`COVIF_CB.is_post_inc_ld_st_inst_ex == 0) && + (`COVIF_CB.ex_apu_valid_memorised == 0)) { + + bins no_alu_wr_stall = {1}; + option.weight = 1; + } + + // cross coverage for F-inst in ID-stage with preceeding F-multicycle instr + cr_f_inst_at_id_stage_inp_with_fpu_multicycle_req : cross cp_id_stage_f_inst, + cp_curr_fpu_apu_op_at_apu_req + {option.weight = 50;} + + // cross coverage for F-inst in ID-stage with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + cr_f_inst_at_id_stage_inp_while_fpu_busy : cross cp_id_stage_f_inst, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + // For FPU config with Latency=0 , apu_busy is expected to be set only for FDIV and FSQRT case + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at ID-stage input at various stages of APU latency + // clk-cycles of the ongoing/preceeding F-multicycle instr + cr_f_inst_at_id_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_f_inst, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + // cross coverage for F-inst at ID-stage output with preceeding F-multicycle instr + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + //cr_f_inst_at_id_stage_out_with_fpu_multicycle_req : cross cp_id_stage_apu_op_ex_o, + // cp_curr_fpu_apu_op_at_apu_req + //{option.weight = 50;} + + // cross coverage for F-inst at ID-stage output with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_while_fpu_busy : cross cp_id_stage_apu_op_ex_o, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at ID-stage output at various stages of APU latency + // clk-cycles of the ongoing/preceeding F-multicycle instr + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_apu_op_ex_o, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { + + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + endgroup : cg_f_multicycle + + + covergroup cg_f_inst_reg(int fpu_latency); + `per_instance_fcov + + cp_apu_req_valid : coverpoint `COVIF_CB.apu_req { + bins apu_req_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_grant_valid : coverpoint `COVIF_CB.apu_gnt { + bins apu_gnt_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_busy : coverpoint `COVIF_CB.apu_busy { + bins apu_busy_high = {1'b1}; + option.weight = 1; + } + + cp_apu_rvalid : coverpoint `COVIF_CB.apu_rvalid_i { + bins apu_rvalid = {1}; + option.weight = 1; + } + + cp_apu_contention : coverpoint `COVIF_CB.apu_perf_wb_o { + bins no_contention = {0}; + bins has_contention = {1}; + option.weight = 1; + } + + cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { + `FPU_OP_BINS + option.weight = 5; + } + + cp_last_fpu_apu_op_at_contention : coverpoint cntxt.cov_vif.o_last_fpu_apu_op_if { + bins curr_apu_op_fmadd = {APU_OP_FMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fnmsub = {APU_OP_FNMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fadd = {APU_OP_FADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmul = {APU_OP_FMUL} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fdiv = {APU_OP_FDIV} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsqrt = {APU_OP_FSQRT} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsgnj = {APU_OP_FSGNJ} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fminmax = {APU_OP_FMINMAX} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fcmp = {APU_OP_FCMP} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fclassify = {APU_OP_FCLASSIFY} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2f = {APU_OP_F2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2i = {APU_OP_F2I} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_i2f = {APU_OP_I2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmsub = {APU_OP_FMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fnmadd = {APU_OP_FNMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsub = {APU_OP_FSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsgnj_se = {APU_OP_FSGNJ_SE} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2i_u = {APU_OP_F2I_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_i2f_u = {APU_OP_I2F_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + option.weight = 5; + } + + // TODO: need to add another cover point for F-inst at ID-EX boundary ? + cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + `RV32F_INSTR_BINS + option.weight = 5; + } + + // TODO: to add rv32c coverage + cp_id_stage_non_rv32fc_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i[6:0] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + `CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC + option.weight = 5; + } + + cp_id_f_inst_fs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins fs1[] = {[0:31]}; + option.weight = 1; + } + + cp_id_f_inst_fs2 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[24:20] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins fs2[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_fd : coverpoint cntxt.cov_vif.curr_fpu_fd { + bins fd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_fd_for_0_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_fd + iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins fd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_fd_for_multicyc_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_fd + iff ( (`COVIF_CB.apu_busy == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins fd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_rd : coverpoint cntxt.cov_vif.curr_fpu_rd { + bins rd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_rd_for_0_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd + iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins rd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd + iff ( (`COVIF_CB.apu_busy == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins rd[] = {[0:31]}; + option.weight = 1; + } + + cp_apu_alu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_ex_regfile_wr_contention { + bins rd[] = {[0:31]} with ( ((item + 1) * (fpu_latency != 1)) != 0 ); + illegal_bins rd_addr_32_63 = {[32:63]} with ( ((item + 1) * (fpu_latency != 1)) != 0 ); + option.weight = 1; + } + + cp_lsu_apu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_wb_regfile_wr_contention { + bins rd[] = {[0:31]} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + illegal_bins rd_addr_32_63 = {[32:63]} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + option.weight = 1; + } + + cp_prev_rd_waddr_contention : coverpoint cntxt.cov_vif.prev_rd_waddr_contention { + bins rd[] = {[0:63]}; + option.weight = 1; + } + + cp_contention_state : coverpoint cntxt.cov_vif.contention_state { + bins no_contention = {0}; + bins contention_1st_cyc_done = {1}; + bins contention_2nd_cyc_done = {2}; + ignore_bins state3 = {3}; + option.weight = 1; + } + + cp_b2b_contention : coverpoint cntxt.cov_vif.b2b_contention { + bins b2b_contention_true = {1}; + option.weight = 5; + } + + cp_fd_fs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_fd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins fd_fs1_equal = {1}; + } + + cp_fd_fs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_fd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins fd_fs2_equal = {1}; + } + + cp_fd_fs3_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[31:27] == cntxt.cov_vif.curr_fpu_fd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins fd_fs3_equal = {1}; + } + + cp_rd_rs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins rd_rs1_equal = {1}; + } + + cp_rd_rs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins rd_rs1_equal = {1}; + } + + //********************************************************************************************************* + // Cross Cov description for reg-to-reg dependency cases in instr sequence with F-multicycle instr + //********************************************************************************************************* + // This Cross Coverage captures the cases where latest APU execution's RD addr is same as + // rs1/rs2/rs3 of the next instruction in pipeline. + // Design is expected to stall EX in such scenarios until the previous instruction retires. + // The test scenarios are captured for correct RTL behavior, expecting EX stall in such cases. + // And for any conflicting design behaviour with EX proceeding without stalls, tests rely on Ref model + // to flag the resulting errors. + + //********************************************************************************************************* + // CASES WITH/WITHOUT CONTENTION AT THE TIME OF APU RESULT WRITE TO REGFILE + // WHERE APU WRITE WILL WIN (APU LATENCY = 0,2,3,4) + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with fd to fs1 dependency + // case with APU latency > 0 + cr_fd_fs1_eq_nonzero_lat : cross cp_fd_fs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_NON_FD_F_INSTR + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + } + + // cross coverage for F-instr following F-instr with fd to fs2 dependency + // case with APU latency > 0 + cr_fd_fs2_eq_nonzero_lat : cross cp_fd_fs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_NON_FD_F_INSTR + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + } + + // cross coverage for F-instr following F-instr with fd to fs3 dependency + // case with APU latency > 0 + cr_fd_fs3_eq_nonzero_lat : cross cp_fd_fs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_NON_FD_F_INSTR + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_FS3_F_INSTR + } + + // cross coverage for F-instr following F-instr with rd to rs1 dependency + // case with APU latency > 0 + cr_rd_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS_F_INSTR_IN_ID + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency + // case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + } + + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency + // case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + } + + // cross coverage for contention case 2nd cycle with ALU regfile write + cr_waddr_rd_apu_alu_ex_contention : cross cp_apu_alu_contention_wr_rd, + cp_contention_state, + cp_apu_contention { + + bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention + with ( (cp_contention_state <= 3) & (fpu_latency != 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NO_CONTENTION + } + + + //********************************************************************************************************* + // CASES WITH/WITHOUT CONTENTION AT APU RESULT WRITE TO REGFILE. APU_LATENCY=0 PRIOIRTY APU WRITE WINS + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with fd to fs1 dependency - 0 Latency + cr_fd_fs1_eq_no_lat : cross cp_fd_fs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_fd_fs1_eq_no_lat with ( (cp_fd_fs1_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_FD_F_INSTR + } + + // cross coverage for F-instr following F-instr with fd to fs2 dependency - 0 Latency + cr_fd_fs2_eq_no_lat : cross cp_fd_fs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_fd_fs2_eq_no_lat with ( (cp_fd_fs2_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_FD_F_INSTR + } + + // cross coverage for F-instr following F-instr with fd to fs3 dependency - 0 Latency + cr_fd_fs3_eq_no_lat : cross cp_fd_fs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_fd_fs3_eq_no_lat with ( (cp_fd_fs3_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_FD_F_INSTR + `IGNORE_BINS_NON_FS3_F_INSTR + } + + // cross coverage for F-instr following F-instr with rd to rs1 dependency - 0 Latency + cr_rd_rs1_eq_no_lat : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs1_eq_no_lat with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS_F_INSTR_IN_ID + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency - 0 Latency + cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + } + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency - 0 Latency + cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat : cross cp_rd_rs2_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + } + + //********************************************************************************************************* + // CONTENTION DURING APU RESULT WRITE TO REGFILE WHERE APU RESULT WRITE STALLS. APU LATENCY = 1 + //********************************************************************************************************* + + // cp_apu_contention = 1 cases + // cp_contention_state = 1 indicates that there was contention in WB at LSU-APU regfile wr mux + + // cross coverage for F-instr following F-instr with fd to fs1 dependency + // case with APU latency = 1 and contention with LSU + cr_fd_fs1_eq_nonzero_lat_with_contention : cross cp_fd_fs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_fd_fs1_eq_nonzero_lat_with_contention + with ( (cp_fd_fs1_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with fd to fs2 dependency + // case with APU latency = 1 and contention with LSU + cr_fd_fs2_eq_nonzero_lat_with_contention : cross cp_fd_fs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_fd_fs2_eq_nonzero_lat_with_contention + with ( (cp_fd_fs2_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with fd to fs3 dependency + // case with APU latency = 1 and contention with LSU + cr_fd_fs3_eq_nonzero_lat_with_contention : cross cp_fd_fs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_fd_fs3_eq_nonzero_lat_with_contention + with ( (cp_fd_fs3_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_FS3_F_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with rd to rs1 dependency + // case with APU latency = 1 and contention with LSU + cr_rd_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs1_eq_nonzero_lat_with_contention + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + `IGNORE_BINS_NON_RD_F_INSTR_AT_CONTENTION + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency + // case with APU latency = 1 and contention with LSU + cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + `IGNORE_BINS_NON_RD_F_INSTR_AT_CONTENTION + } + + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency + // case with APU latency = 1 and contention with LSU + cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention : cross cp_rd_rs2_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + `IGNORE_BINS_NON_RD_F_INSTR_AT_CONTENTION + } + + // TODO: does it require checking rd to rs1/rs2 equal in this case? + // cross coverage for contention case 1st cycle with LSU regfile write win + cr_waddr_rd_lsu_apu_wb_contention : cross cp_apu_busy, + cp_apu_rvalid, + cp_lsu_apu_contention_wr_rd, + cp_apu_contention { + + bins main_cr_bin = cr_waddr_rd_lsu_apu_wb_contention + with ( (cp_apu_rvalid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NO_CONTENTION_LSU + } + + endgroup : cg_f_inst_reg + +endclass : uvme_cv32e40p_fp_instr_covg + +function uvme_cv32e40p_fp_instr_covg::new(string name = "cv32e40p_fp_instr_covg", uvm_component parent = null); + super.new(name, parent); + void'(uvm_config_db#(uvme_cv32e40p_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("cv32e40p_fp_instr_covg", "Configuration handle is null") + end + + cg_f_multicycle = new(.fpu_latency(cfg.fpu_latency)); + cg_f_inst_reg = new(.fpu_latency(cfg.fpu_latency)); + +endfunction : new + +function void uvme_cv32e40p_fp_instr_covg::build_phase(uvm_phase phase); + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cv32e40p_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("cv32e40p_fp_instr_covg", "No cntxt object passed to model"); + end +endfunction : build_phase + +task uvme_cv32e40p_fp_instr_covg::run_phase(uvm_phase phase); + super.run_phase(phase); + `uvm_info("cv32e40p_fp_instr_covg", "The RV32_F coverage model is running", UVM_LOW); + fork + sample_clk_i(); + join_none +endtask : run_phase + + +task uvme_cv32e40p_fp_instr_covg::sample_clk_i(); + while (1) begin + @(`COVIF_CB); + if ((`COVIF_CB.debug_req_i == 0) && (`COVIF_CB.debug_mode_q == 0) && + (`COVIF_CB.trigger_match_i == 0) && (cntxt.debug_cov_vif.mon_cb.dcsr_q[2] == 0)) begin // Only sample in M-mode without debug entry cases + cg_f_multicycle.sample(); + cg_f_inst_reg.sample(); + end + end +endtask : sample_clk_i diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv new file mode 100644 index 0000000000..4d2c43739e --- /dev/null +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv @@ -0,0 +1,762 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright 2023 OpenHW Group +// Copyright 2023 Dolphin Design +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// +/////////////////////////////////////////////////////////////////////////////// + +class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; + /* + * Class members + */ + uvme_cv32e40p_cfg_c cfg; + uvme_cv32e40p_cntxt_c cntxt; + + `uvm_component_utils_begin(uvme_cv32e40p_zfinx_instr_covg) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + extern function new(string name = "cv32e40p_zfinx_instr_covg", uvm_component parent = null); + extern function void build_phase(uvm_phase phase); + extern task run_phase(uvm_phase phase); + extern task sample_clk_i(); + + `define FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES \ + illegal_bins clk_2_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 0) ); \ + illegal_bins clk_3_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 1) ); \ + illegal_bins clk_4_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2, 3}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 2) ); + + `define FPU_ZERO_LATENCY_ILLEGAL_BUSY \ + illegal_bins apu_busy_curr_apu_op_not_div_sqrt = ( !binsof(cp_curr_fpu_apu_op_multicycle) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ + with ( ((cp_curr_fpu_apu_op_multicycle + 1) * (fpu_latency == 0)) != 0 ); + + `define IGNORE_BINS_ZERO_LAT_FPU_OP \ + ignore_bins zero_lat_inst = ( !binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ + with ( ((cp_curr_fpu_apu_op + 1) * (fpu_latency == 0)) != 0 ); + + `define IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU \ + ignore_bins in_contention_lsu_wr = ( binsof(cp_apu_contention) intersect {1} ) \ + with ( ((cp_curr_fpu_apu_op + 1) * (fpu_latency == 1)) != 0 ); + + `define IGNORE_BINS_NON_RS1_CV32E40P_INSTR \ + ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL}; + + `define IGNORE_BINS_NON_RS2_CV32E40P_INSTR \ + ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_INSTR_WITH_NO_RS2}; + + `define IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE \ + ignore_bins non_stalled_contention_wr_state = binsof(cp_contention_state) intersect {0,1}; + + `define IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR \ + ignore_bins contention_at_lsu_wr = binsof(cp_apu_contention) intersect {1}; + + `define IGNORE_BINS_NO_CONTENTION \ + ignore_bins no_contention = binsof(cp_apu_contention) intersect {1}; + + `define IGNORE_BINS_NON_RS3_ZFINX_INSTR \ + ignore_bins non_rs3_f_inst = !binsof(cp_id_stage_f_inst) intersect {`RV32F_INSTR_WITH_NO_FS3}; + + `define IGNORE_BINS_NO_CONTENTION_LSU \ + ignore_bins no_contention_lsu_wr = binsof(cp_apu_contention) intersect {0}; + + /* + * Covergroups + */ + + covergroup cg_f_multicycle(int fpu_latency); + `per_instance_fcov + option.at_least = 10; + + cp_if_stage_f_inst : coverpoint `COVIF_CB.if_stage_instr_rdata_i iff (`COVIF_CB.if_stage_instr_rvalid_i == 1) { + `ZFINX_INSTR_BINS + option.weight = 5; + } + + cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + `ZFINX_INSTR_BINS + option.weight = 5; + } + + cp_id_stage_apu_op_ex_o : coverpoint `COVIF_CB.id_stage_apu_op_ex_o iff (`COVIF_CB.id_stage_apu_en_ex_o == 1) { + `FPU_OP_BINS + option.weight = 5; + } + + cp_f_multicycle_clk_window : coverpoint cntxt.cov_vif.if_clk_cycle_window iff ((`COVIF_CB.is_mulh_ex == 0) && + (`COVIF_CB.is_misaligned_data_req_ex == 0) && + (`COVIF_CB.is_post_inc_ld_st_inst_ex == 0) && + (`COVIF_CB.ex_apu_valid_memorised == 0)) { + bins clk1 = {1}; + bins clk2 = {2}; + bins clk3 = {3}; + bins clk4 = {4}; + bins clk5 = {5}; + bins clk6 = {6}; + bins clk7 = {7}; + bins clk8 = {8}; + bins clk9 = {9}; + bins clk10 = {10}; + bins clk11 = {11}; + bins clk12 = {12}; + bins clk13 = {13}; + bins clk14 = {14}; + bins clk15 = {15}; + bins clk16 = {16}; + bins clk17 = {17}; + bins clk18 = {18}; + bins clk19 = {19}; + ignore_bins ignore_idle = {0}; + illegal_bins clk_more_than_19 = {[20:31]}; + } + + cp_id_stage_inst_valid : coverpoint `COVIF_CB.id_stage_instr_valid_i { + bins id_stage_instr_valid = {1}; + option.weight = 1; + } + + cp_if_stage_inst_valid : coverpoint `COVIF_CB.if_stage_instr_rvalid_i { + bins if_stage_instr_valid = {1}; + option.weight = 1; + } + + cp_id_stage_apu_en_ex_o : coverpoint `COVIF_CB.id_stage_apu_en_ex_o { + bins id_stage_apu_en_ex_1 = {1}; + bins id_stage_apu_en_ex_0_to_1 = (0 => 1); + option.weight = 1; + } + + cp_apu_req_valid : coverpoint `COVIF_CB.apu_req { + bins apu_req_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_grant_valid : coverpoint `COVIF_CB.apu_gnt { + bins apu_gnt_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_busy : coverpoint `COVIF_CB.apu_busy { + bins apu_busy_high = {1'b1}; + option.weight = 1; + } + + cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { + `FPU_OP_BINS + option.weight = 5; + } + + cp_curr_fpu_apu_op_at_apu_req : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) ) + { + `FPU_OP_BINS + option.weight = 5; + } + + cp_curr_fpu_apu_op_multicycle : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff (`COVIF_CB.apu_busy == 1) + { + `FPU_OP_BINS + option.weight = 5; + } + + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall : coverpoint ((cntxt.cov_vif.is_mulh_ex == 0) && + (cntxt.cov_vif.is_misaligned_data_req_ex == 0) && + (cntxt.cov_vif.is_post_inc_ld_st_inst_ex == 0) && + (cntxt.cov_vif.ex_apu_valid_memorised == 0)) { + + bins no_alu_wr_stall = {1}; + option.weight = 1; + } + + // cross coverage for F-inst in ID-stage with preceeding F-multicycle instr + cr_f_inst_at_id_stage_inp_with_fpu_multicycle_req : cross cp_id_stage_f_inst, + cp_curr_fpu_apu_op_at_apu_req + {option.weight = 50;} + + // cross coverage for F-inst in ID-stage with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + cr_f_inst_at_id_stage_inp_while_fpu_busy : cross cp_id_stage_f_inst, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + // For FPU config with Latency=0 , apu_busy is expected to be set only for FDIV and FSQRT case + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at ID-stage input at various stages of APU latency + // clk-cycles of the ongoing/preceeding F-multicycle instr + cr_f_inst_at_id_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_f_inst, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + // cross coverage for F-inst at ID-stage output with preceeding F-multicycle instr + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + //cr_f_inst_at_id_stage_out_with_fpu_multicycle_req : cross cp_id_stage_apu_op_ex_o, + // cp_curr_fpu_apu_op_at_apu_req + //{option.weight = 50;} + + // cross coverage for F-inst at ID-stage output with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_while_fpu_busy : cross cp_id_stage_apu_op_ex_o, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at ID-stage output at various stages of APU latency + // clk-cycles of the ongoing/preceeding F-multicycle instr + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_apu_op_ex_o, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { + + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + // cross coverage for F-inst at IF-stage with preceeding F-multicycle instr + cr_f_inst_at_if_stage_inp_with_fpu_multicycle_req : cross cp_if_stage_f_inst, + cp_curr_fpu_apu_op_at_apu_req + {option.weight = 50;} + + // cross coverage for F-inst at IF-stage with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + cr_f_inst_at_if_stage_inp_while_fpu_busy : cross cp_if_stage_f_inst, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at IF-stage output at various stages of + // APU latency clk-cycles of the ongoing/preceeding F-multicycle instr + cr_f_inst_at_if_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_if_stage_f_inst, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { + + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + endgroup : cg_f_multicycle + + + covergroup cg_zfinx_inst_reg(int fpu_latency); + `per_instance_fcov + + cp_apu_req_valid : coverpoint `COVIF_CB.apu_req { + bins apu_req_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_grant_valid : coverpoint `COVIF_CB.apu_gnt { + bins apu_gnt_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_busy : coverpoint `COVIF_CB.apu_busy { + bins apu_busy_high = {1'b1}; + option.weight = 1; + } + + cp_apu_rvalid : coverpoint `COVIF_CB.apu_rvalid_i { + bins apu_rvalid = {1}; + option.weight = 1; + } + + cp_apu_contention : coverpoint `COVIF_CB.apu_perf_wb_o { + bins no_contention = {0}; + bins has_contention = {1}; + option.weight = 1; + } + + cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { + `FPU_OP_BINS + option.weight = 5; + } + + cp_last_fpu_apu_op_at_contention : coverpoint cntxt.cov_vif.o_last_fpu_apu_op_if { + bins curr_apu_op_fmadd = {APU_OP_FMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fnmsub = {APU_OP_FNMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fadd = {APU_OP_FADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmul = {APU_OP_FMUL} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fdiv = {APU_OP_FDIV} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsqrt = {APU_OP_FSQRT} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsgnj = {APU_OP_FSGNJ} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fminmax = {APU_OP_FMINMAX} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fcmp = {APU_OP_FCMP} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fclassify = {APU_OP_FCLASSIFY} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2f = {APU_OP_F2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2i = {APU_OP_F2I} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_i2f = {APU_OP_I2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmsub = {APU_OP_FMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fnmadd = {APU_OP_FNMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsub = {APU_OP_FSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsgnj_se = {APU_OP_FSGNJ_SE} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2i_u = {APU_OP_F2I_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_i2f_u = {APU_OP_I2F_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + option.weight = 5; + } + + // TODO: need to add another cover point for F-inst at ID-EX boundary ? + cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + `ZFINX_INSTR_BINS + option.weight = 5; + } + + // TODO: to add rv32c coverage + cp_id_stage_non_rv32fc_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i[6:0] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + `CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC + option.weight = 5; + } + + cp_id_f_inst_fs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins fs1[] = {[0:31]}; + option.weight = 1; + } + + cp_id_f_inst_fs2 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[24:20] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins fs2[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_fd : coverpoint cntxt.cov_vif.curr_fpu_fd { + bins fd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_rd : coverpoint cntxt.cov_vif.curr_fpu_rd { + bins rd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_rd_for_0_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd + iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins rd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd + iff ( (`COVIF_CB.apu_busy == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins rd[] = {[0:31]}; + option.weight = 1; + } + + cp_apu_alu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_ex_regfile_wr_contention { + bins rd[] = {[0:31]} with ( (item < 32) & (fpu_latency != 1) ); + illegal_bins rd_addr_32_63 = {[32:63]}; + option.weight = 1; + } + + cp_lsu_apu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_wb_regfile_wr_contention { + bins rd[] = {[0:31]} with ( (item < 32) & (fpu_latency == 1) ); + illegal_bins rd_addr_32_63 = {[32:63]}; + option.weight = 1; + } + + cp_prev_rd_waddr_contention : coverpoint cntxt.cov_vif.prev_rd_waddr_contention { + bins rd[] = {[0:31]}; + illegal_bins rd_addr_32_63 = {[32:63]}; //for zfinx only 32 gprs available + option.weight = 1; + } + + cp_contention_state : coverpoint cntxt.cov_vif.contention_state { + bins no_contention = {0}; + bins contention_1st_cyc_done = {1}; + bins contention_2nd_cyc_done = {2}; + ignore_bins state3 = {3}; + option.weight = 1; + } + + cp_b2b_contention : coverpoint cntxt.cov_vif.b2b_contention { + bins b2b_contention_true = {1}; + option.weight = 5; + } + + cp_rd_rs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins rd_rs1_equal = {1}; + } + + cp_rd_rs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins rd_rs2_equal = {1}; + } + + cp_rd_rs3_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[31:27] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins rd_rs3_equal = {1}; + } + + cp_contention_rd_rd_eq : coverpoint (cntxt.cov_vif.curr_rd_at_ex_regfile_wr_contention == cntxt.cov_vif.prev_rd_waddr_contention) { + bins contention_rd_rd_equal = {1} with ( (item == 1) & (fpu_latency != 1) ); + } + + cp_contention_rd_rd_eq_fpu_lat_1 : coverpoint (cntxt.cov_vif.curr_fpu_rd == cntxt.cov_vif.prev_rd_waddr_contention) { + bins contention_rd_rd_equal = {1} with ( (item == 1) & (fpu_latency == 1) ); + } + + //********************************************************************************************************* + // Cross Cov description for reg-to-reg dependency cases in instr sequence with F-multicycle instr + //********************************************************************************************************* + + //********************************************************************************************************* + // CASES WITH/WITHOUT CONTENTION AT THE TIME OF APU RESULT WRITE TO REGFILE + // WHERE APU WRITE WILL WIN (APU LATENCY = 0,2,3,4) + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with rd to rs1 dependency + // case with APU latency > 0 + cr_rd_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + } + + // cross coverage for F-instr following F-instr with rd to rs2 dependency + // case with APU latency > 0 + cr_rd_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + } + + // cross coverage for F-instr following F-instr with rd to rs3 dependency + // case with APU latency > 0 + cr_rd_rs3_eq_nonzero_lat : cross cp_rd_rs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RS3_ZFINX_INSTR + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency + // case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + } + + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency + // case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + } + + // cross coverage for contention case 2nd cycle with ALU regfile write + cr_waddr_rd_apu_alu_ex_contention : cross cp_apu_alu_contention_wr_rd, + cp_contention_state, + cp_apu_contention { + + bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention + with ( (cp_contention_state <= 3) & (fpu_latency != 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NO_CONTENTION + } + + // cross coverage for RD-RD equal for both contention instructions + cr_contention_rd_rd_eq : cross cp_contention_rd_rd_eq, + cp_contention_state, + cp_apu_contention { + + bins main_cr_bin = cr_contention_rd_rd_eq + with ( (cp_contention_state <= 3) & (fpu_latency != 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NO_CONTENTION + } + + // cross coverage for RD-RD equal for both contention instructions for + // fpu_laterncy=1 + cr_contention_rd_rd_eq_fpu_lat_1 : cross cp_contention_rd_rd_eq_fpu_lat_1, + cp_contention_state, + cp_apu_contention { + + bins main_cr_bin = cr_contention_rd_rd_eq_fpu_lat_1 + with ( (cp_contention_state <= 3) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NO_CONTENTION + } + + //********************************************************************************************************* + // CASES WITH/WITHOUT CONTENTION AT APU RESULT WRITE TO REGFILE. APU_LATENCY=0 PRIOIRTY APU WRITE WINS + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with rd to rs1 dependency - 0 Latency + cr_rd_rs1_eq_no_lat : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs1_eq_no_lat with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 0) ); + } + + // cross coverage for F-instr following F-instr with rd to rs2 dependency - 0 Latency + cr_rd_rs2_eq_no_lat : cross cp_rd_rs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs2_eq_no_lat with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 0) ); + } + + // cross coverage for F-instr following F-instr with rd to rs3 dependency - 0 Latency + cr_rd_rs3_eq_no_lat : cross cp_rd_rs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs3_eq_no_lat with ( (cp_rd_rs3_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RS3_ZFINX_INSTR + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency - 0 Latency + cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + } + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency - 0 Latency + cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat : cross cp_rd_rs2_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + } + + //********************************************************************************************************* + // CONTENTION DURING APU RESULT WRITE TO REGFILE WHERE APU RESULT WRITE STALLS. APU LATENCY = 1 + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with rd to rs1 dependency + // case with APU latency = 1 and contention with LSU + cr_rd_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs1_eq_nonzero_lat_with_contention + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with rd to rs2 dependency + // case with APU latency = 1 and contention with LSU + cr_rd_rs2_eq_nonzero_lat_with_contention : cross cp_rd_rs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs2_eq_nonzero_lat_with_contention + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with rd to rs3 dependency + // case with APU latency = 1 and contention with LSU + cr_rd_rs3_eq_nonzero_lat_with_contention : cross cp_rd_rs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs3_eq_nonzero_lat_with_contention + with ( (cp_rd_rs3_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency + // case with APU latency = 1 and contention with LSU + cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency + // case with APU latency = 1 and contention with LSU + cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention : cross cp_rd_rs2_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // TODO: does it require checking rd to rs1/rs2 equal in this case? + // cross coverage for contention case 1st cycle with LSU regfile write win + cr_waddr_rd_lsu_apu_wb_contention : cross cp_apu_busy, + cp_apu_rvalid, + cp_lsu_apu_contention_wr_rd, + cp_apu_contention { + + bins main_cr_bin = cr_waddr_rd_lsu_apu_wb_contention + with ( (cp_apu_rvalid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NO_CONTENTION_LSU + } + endgroup : cg_zfinx_inst_reg + +endclass : uvme_cv32e40p_zfinx_instr_covg + +function uvme_cv32e40p_zfinx_instr_covg::new(string name = "cv32e40p_zfinx_instr_covg", uvm_component parent = null); + super.new(name, parent); + void'(uvm_config_db#(uvme_cv32e40p_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("cv32e40p_zfinx_instr_covg", "Configuration handle is null") + end + + cg_f_multicycle = new(.fpu_latency(cfg.fpu_latency)); + cg_zfinx_inst_reg = new(.fpu_latency(cfg.fpu_latency)); + +endfunction : new + +function void uvme_cv32e40p_zfinx_instr_covg::build_phase(uvm_phase phase); + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cv32e40p_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("cv32e40p_zfinx_instr_covg", "No cntxt object passed to model"); + end +endfunction : build_phase + +task uvme_cv32e40p_zfinx_instr_covg::run_phase(uvm_phase phase); + super.run_phase(phase); + `uvm_info("cv32e40p_zfinx_instr_covg", "The RV32ZFINX coverage model is running", UVM_LOW); + fork + sample_clk_i(); + join_none +endtask : run_phase + +task uvme_cv32e40p_zfinx_instr_covg::sample_clk_i(); + while (1) begin + @(`COVIF_CB); + cg_f_multicycle.sample(); + cg_zfinx_inst_reg.sample(); + end +endtask : sample_clk_i diff --git a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv index a1701d3822..74750003a2 100644 --- a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv @@ -426,451 +426,176 @@ class uvme_debug_covg extends uvm_component; dbg_req_vs_step : cross dbg_req, step; endgroup - covergroup cg_debug_with_f_inst; + covergroup cg_debug_with_rv32f_inst; `per_instance_fcov - dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { + + cp_dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins dbg_req_active = {1'b1}; bins dbg_req_0_to_1 = (0 => 1); } - step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins debug_step_mode_set = {1'b1}; + + cp_step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { + bins dbg_step_mode_set = {1'b1}; + bins dbg_step_mode_not_set = {1'b0}; } - ebreak: coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { + + cp_ebreak: coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { bins ebreak_ex = {1}; } - cebreak : coverpoint cntxt.debug_cov_vif.mon_cb.is_cebreak { + + cp_cebreak : coverpoint cntxt.debug_cov_vif.mon_cb.is_cebreak { bins cebreak_ex= {1'b1}; } - ebreakm_set: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[15] { + + cp_ebreakm_set: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[15] { bins ebreakm_is_set = {1}; } - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins in_debug_mode = {1}; + + cp_trigger_match : coverpoint cntxt.debug_cov_vif.mon_cb.trigger_match_i { + bins not_match = {0}; + bins match = {1}; } - irq : coverpoint |cntxt.debug_cov_vif.mon_cb.irq_i { - bins irq_trans_0_to_1 = (1'b0 => 1'b1); + + cp_trigger_en : coverpoint cntxt.debug_cov_vif.mon_cb.tdata1[2] { + bins trig_en = {1}; } - ill : coverpoint cntxt.debug_cov_vif.mon_cb.illegal_insn_i { + + cp_dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { + bins in_debug_mode = {1}; + } + + cp_irq : coverpoint (cntxt.debug_cov_vif.mon_cb.irq_i & cntxt.debug_cov_vif.mon_cb.mie_q) { + wildcard bins irq_31_trans_0_to_1 = ( {1'b0,31'b?} => {1'b1,31'b?} ); + wildcard bins irq_30_trans_0_to_1 = ( {1'b0,1'b0,30'b?} => {1'b0,1'b1,30'b?} ); + wildcard bins irq_29_trans_0_to_1 = ( {2'b0,1'b0,29'b?} => {2'b0,1'b1,29'b?} ); + wildcard bins irq_28_trans_0_to_1 = ( {3'b0,1'b0,28'b?} => {3'b0,1'b1,28'b?} ); + wildcard bins irq_27_trans_0_to_1 = ( {4'b0,1'b0,27'b?} => {4'b0,1'b1,27'b?} ); + wildcard bins irq_26_trans_0_to_1 = ( {5'b0,1'b0,26'b?} => {5'b0,1'b1,26'b?} ); + wildcard bins irq_25_trans_0_to_1 = ( {6'b0,1'b0,25'b?} => {6'b0,1'b1,25'b?} ); + wildcard bins irq_24_trans_0_to_1 = ( {7'b0,1'b0,24'b?} => {7'b0,1'b1,24'b?} ); + wildcard bins irq_23_trans_0_to_1 = ( {8'b0,1'b0,23'b?} => {8'b0,1'b1,23'b?} ); + wildcard bins irq_22_trans_0_to_1 = ( {9'b0,1'b0,22'b?} => {9'b0,1'b1,22'b?} ); + wildcard bins irq_21_trans_0_to_1 = ( {10'b0,1'b0,21'b?} => {10'b0,1'b1,21'b?} ); + wildcard bins irq_20_trans_0_to_1 = ( {11'b0,1'b0,20'b?} => {11'b0,1'b1,20'b?} ); + wildcard bins irq_19_trans_0_to_1 = ( {12'b0,1'b0,19'b?} => {12'b0,1'b1,19'b?} ); + wildcard bins irq_18_trans_0_to_1 = ( {13'b0,1'b0,18'b?} => {13'b0,1'b1,18'b?} ); + wildcard bins irq_17_trans_0_to_1 = ( {14'b0,1'b0,17'b?} => {14'b0,1'b1,17'b?} ); + wildcard bins irq_16_trans_0_to_1 = ( {15'b0,1'b0,16'b?} => {15'b0,1'b1,16'b?} ); + wildcard bins irq_11_trans_0_to_1 = ( {20'b0,1'b0,11'b?} => {20'b0,1'b1,11'b?} ); + wildcard bins irq_3_trans_0_to_1 = ( {24'b0,1'b0,3'b?,1'b0,3'b?} => {24'b0,1'b?,3'b?,1'b1,3'b?} ); + wildcard bins irq_7_trans_0_to_1 = ( {24'b0,1'b0,3'b?,1'b0,3'b?} => {24'b0,1'b1,3'b?,1'b0,3'b?} ); + } + + cp_ill : coverpoint cntxt.debug_cov_vif.mon_cb.illegal_insn_i { bins ill_inst_hit = {1}; } - f_inst : coverpoint cntxt.debug_cov_vif.mon_cb.rvfi_insn { - wildcard bins fadd = {cv32e40p_tracer_pkg::INSTR_FADD}; - wildcard bins fsub = {cv32e40p_tracer_pkg::INSTR_FSUB}; - wildcard bins fmul = {cv32e40p_tracer_pkg::INSTR_FMUL}; - wildcard bins fdiv = {cv32e40p_tracer_pkg::INSTR_FDIV}; - wildcard bins fsqrt = {cv32e40p_tracer_pkg::INSTR_FSQRT}; - wildcard bins fsgnjs = {cv32e40p_tracer_pkg::INSTR_FSGNJS}; - wildcard bins fsgnjns = {cv32e40p_tracer_pkg::INSTR_FSGNJNS}; - wildcard bins fsgnjxs = {cv32e40p_tracer_pkg::INSTR_FSGNJXS}; - wildcard bins fmin = {cv32e40p_tracer_pkg::INSTR_FMIN}; - wildcard bins fmax = {cv32e40p_tracer_pkg::INSTR_FMAX}; - wildcard bins fcvtws = {cv32e40p_tracer_pkg::INSTR_FCVTWS}; - wildcard bins fcvtwus = {cv32e40p_tracer_pkg::INSTR_FCVTWUS}; - wildcard bins fmvxs = {cv32e40p_tracer_pkg::INSTR_FMVXS}; - wildcard bins feqs = {cv32e40p_tracer_pkg::INSTR_FEQS}; - wildcard bins flts = {cv32e40p_tracer_pkg::INSTR_FLTS}; - wildcard bins fles = {cv32e40p_tracer_pkg::INSTR_FLES}; - wildcard bins fclass = {cv32e40p_tracer_pkg::INSTR_FCLASS}; - wildcard bins fcvtsw = {cv32e40p_tracer_pkg::INSTR_FCVTSW}; - wildcard bins fcvtswu = {cv32e40p_tracer_pkg::INSTR_FCVTSWU}; - wildcard bins fmvsw = {cv32e40p_tracer_pkg::INSTR_FMVSX}; - wildcard bins fmadd = {cv32e40p_tracer_pkg::INSTR_FMADD}; - wildcard bins fmsub = {cv32e40p_tracer_pkg::INSTR_FMSUB}; - wildcard bins fnmsub = {cv32e40p_tracer_pkg::INSTR_FNMSUB}; - wildcard bins fnmadd = {cv32e40p_tracer_pkg::INSTR_FNMADD}; - } - - rvfi_valid : coverpoint cntxt.debug_cov_vif.mon_cb.rvfi_valid { - bins rvfi_valid = {1}; - } - - apu_req_valid : coverpoint cntxt.debug_cov_vif.mon_cb.apu_req { + cp_rv32f_inst : coverpoint cntxt.debug_cov_vif.mon_cb.id_stage_instr_rdata_i iff (cntxt.debug_cov_vif.mon_cb.id_stage_instr_valid_i == 1) { + `RV32F_INSTR_BINS + } + + cp_apu_req_valid : coverpoint cntxt.debug_cov_vif.mon_cb.apu_req { bins apu_req_valid = {1'b1}; } - apu_grant_valid : coverpoint cntxt.debug_cov_vif.mon_cb.apu_gnt { + cp_apu_grant_valid : coverpoint cntxt.debug_cov_vif.mon_cb.apu_gnt { bins apu_gnt_valid[] = {1'b1}; } - apu_busy : coverpoint cntxt.debug_cov_vif.mon_cb.apu_busy { + cp_apu_busy : coverpoint cntxt.debug_cov_vif.mon_cb.apu_busy { bins apu_busy[] = {1'b0, 1'b1}; bins apu_busy_0_to_1 = (0 => 1); bins apu_busy_1_to_0 = (1 => 0); } - dbg_x_finst : cross dbg_req, f_inst; + // cross rv32f instr execution at debug req only - no trigger + cr_dbg_x_rv32f : cross cp_dbg_req, cp_rv32f_inst, cp_trigger_match { + ignore_bins no_trigger_match = binsof(cp_trigger_match) intersect {1}; + } - step_x_finst : cross step, f_inst; + // cross debug single stepping for each rv32f instr - no trigger + cr_step_x_rv32f : cross cp_step, cp_rv32f_inst, cp_trigger_match { + ignore_bins single_step_disable = binsof(cp_step) intersect {0}; + ignore_bins no_trigger_match = binsof(cp_trigger_match) intersect {1}; + } + + // cross debug entry with trigger addr match at rv32f inst + cr_trigger_with_rv32f : cross cp_trigger_match, cp_trigger_en, cp_rv32f_inst; + + cr_rv32f_in_dbg_mode : cross cp_dm, cp_rv32f_inst; - f_inst_in_dbg_mode : cross dm, f_inst; + // debug mode entry with debug_halt_req during multi cycle fp inst + cr_dbg_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req; + cr_dbg_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req; - //debug mode entry with debug_halt_req during multi cycle fp inst - dbg_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, dbg_req; - dbg_while_multi_cyc_f_B : cross apu_busy, dbg_req; + // debug_halt_req with irq during multi cycle fp inst + cr_dbg_irq_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_irq; + cr_dbg_irq_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req, cp_irq; - //debug_halt_req with irq during multi cycle fp inst - dbg_irq_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, dbg_req, irq; - dbg_irq_while_multi_cyc_f_B : cross apu_busy, dbg_req, irq; + // debug_halt_req with illegal instr during multi cycle fp inst + cr_dbg_ill_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_ill; + cr_dbg_ill_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req, cp_ill; - //debug_halt_req with illegal instr during multi cycle fp inst - dbg_ill_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, dbg_req, ill; - dbg_ill_while_multi_cyc_f_B : cross apu_busy, dbg_req, ill; + // debug mode entry with ebreak during multi cycle fp inst + cr_ebreak_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_ebreak, cp_ebreakm_set; + cr_ebreak_while_multi_cyc_f_B : cross cp_apu_busy, cp_ebreak, cp_ebreakm_set; - //debug mode entry with ebreak during multi cycle fp inst - ebreak_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, ebreak, ebreakm_set; - ebreak_while_multi_cyc_f_B : cross apu_busy, ebreak, ebreakm_set; + // debug mode entry with cebreak during multi cycle fp inst + cr_cebreak_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_cebreak, cp_ebreakm_set; + cr_cebreak_while_multi_cyc_f_B : cross cp_apu_busy, cp_cebreak, cp_ebreakm_set; - //debug mode entry with cebreak during multi cycle fp inst - cebreak_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, cebreak, ebreakm_set; - cebreak_while_multi_cyc_f_B : cross apu_busy, cebreak, ebreakm_set; + // debug mode entry with trigger during multi cycle fp inst + cr_dbg_trig_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_trigger_match, cp_trigger_en; + cr_dbg_trig_while_multi_cyc_f_B : cross cp_apu_busy, cp_trigger_match, cp_trigger_en; endgroup covergroup cg_debug_with_xpulp_inst; `per_instance_fcov - dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { + + cp_dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins dbg_req_active = {1'b1}; bins dbg_req_0_to_1 = (0 => 1); } - step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins debug_step_mode_set = {1'b1}; + + cp_step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { + bins dbg_step_mode_set = {1'b1}; + bins dbg_step_mode_not_set = {1'b0}; } - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { + + cp_trigger_match : coverpoint cntxt.debug_cov_vif.mon_cb.trigger_match_i { + bins not_match = {0}; + bins match = {1}; + } + + cp_trigger_en : coverpoint cntxt.debug_cov_vif.mon_cb.tdata1[2] { + bins trig_en = {1}; + } + + cp_dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins in_debug_mode = {1}; } - xpulp_instruction : coverpoint cntxt.debug_cov_vif.mon_cb.rvfi_insn { - wildcard bins cv_lb_pi_ri = {INSTR_CV_LB_PI_RI}; - wildcard bins cv_lh_pi_ri = {INSTR_CV_LH_PI_RI}; - wildcard bins cv_lw_pi_ri = {INSTR_CV_LW_PI_RI}; - wildcard bins cv_elw_pi_ri = {INSTR_CV_ELW_PI_RI}; - wildcard bins cv_lbu_pi_ri = {INSTR_CV_LBU_PI_RI}; - wildcard bins cv_lhu_pi_ri = {INSTR_CV_LHU_PI_RI}; - wildcard bins cv_beqimm = {INSTR_CV_BEQIMM}; - wildcard bins cv_bneimm = {INSTR_CV_BNEIMM}; - wildcard bins cv_lb_pi_rr = {INSTR_CV_LB_PI_RR}; - wildcard bins cv_lh_pi_rr = {INSTR_CV_LH_PI_RR}; - wildcard bins cv_lw_pi_rr = {INSTR_CV_LW_PI_RR}; - wildcard bins cv_lbu_pi_rr = {INSTR_CV_LBU_PI_RR}; - wildcard bins cv_lhu_pi_rr = {INSTR_CV_LHU_PI_RR}; - wildcard bins cv_lb_rr = {INSTR_CV_LB_RR}; - wildcard bins cv_lh_rr = {INSTR_CV_LH_RR}; - wildcard bins cv_lw_rr = {INSTR_CV_LW_RR}; - wildcard bins cv_lbu_rr = {INSTR_CV_LBU_RR}; - wildcard bins cv_lhu_rr = {INSTR_CV_LHU_RR}; - wildcard bins cv_sb_pi_ri = {INSTR_CV_SB_PI_RI}; - wildcard bins cv_sh_pi_ri = {INSTR_CV_SH_PI_RI}; - wildcard bins cv_sw_pi_ri = {INSTR_CV_SW_PI_RI}; - wildcard bins cv_sb_pi_rr = {INSTR_CV_SB_PI_RR}; - wildcard bins cv_sh_pi_rr = {INSTR_CV_SH_PI_RR}; - wildcard bins cv_sw_pi_rr = {INSTR_CV_SW_PI_RR}; - wildcard bins cv_sb_rr = {INSTR_CV_SB_RR}; - wildcard bins cv_sh_rr = {INSTR_CV_SH_RR}; - wildcard bins cv_sw_rr = {INSTR_CV_SW_RR}; - wildcard bins cv_starti = {INSTR_CV_STARTI}; - wildcard bins cv_start = {INSTR_CV_START}; - wildcard bins cv_endi = {INSTR_CV_ENDI}; - wildcard bins cv_end = {INSTR_CV_END}; - wildcard bins cv_counti = {INSTR_CV_COUNTI}; - wildcard bins cv_count = {INSTR_CV_COUNT}; - wildcard bins cv_setupi = {INSTR_CV_SETUPI}; - wildcard bins cv_setup = {INSTR_CV_SETUP}; - wildcard bins cv_extractr = {INSTR_CV_EXTRACTR}; - wildcard bins cv_extractur = {INSTR_CV_EXTRACTUR}; - wildcard bins cv_insertr = {INSTR_CV_INSERTR}; - wildcard bins cv_bclrr = {INSTR_CV_BCLRR}; - wildcard bins cv_bsetr = {INSTR_CV_BSETR}; - wildcard bins cv_ror = {INSTR_CV_ROR}; - wildcard bins cv_ff1 = {INSTR_CV_FF1}; - wildcard bins cv_fl1 = {INSTR_CV_FL1}; - wildcard bins cv_clb = {INSTR_CV_CLB}; - wildcard bins cv_cnt = {INSTR_CV_CNT}; - wildcard bins cv_abs = {INSTR_CV_ABS}; - wildcard bins cv_slet = {INSTR_CV_SLET}; - wildcard bins cv_sletu = {INSTR_CV_SLETU}; - wildcard bins cv_min = {INSTR_CV_MIN}; - wildcard bins cv_minu = {INSTR_CV_MINU}; - wildcard bins cv_max = {INSTR_CV_MAX}; - wildcard bins cv_maxu = {INSTR_CV_MAXU}; - wildcard bins cv_exths = {INSTR_CV_EXTHS}; - wildcard bins cv_exthz = {INSTR_CV_EXTHZ}; - wildcard bins cv_extbs = {INSTR_CV_EXTBS}; - wildcard bins cv_extbz = {INSTR_CV_EXTBZ}; - wildcard bins cv_clip = {INSTR_CV_CLIP}; - wildcard bins cv_clipu = {INSTR_CV_CLIPU}; - wildcard bins cv_clipr = {INSTR_CV_CLIPR}; - wildcard bins cv_clipur = {INSTR_CV_CLIPUR}; - wildcard bins cv_addnr = {INSTR_CV_ADDNR}; - wildcard bins cv_addunr = {INSTR_CV_ADDUNR}; - wildcard bins cv_addrnr = {INSTR_CV_ADDRNR}; - wildcard bins cv_addurnr = {INSTR_CV_ADDURNR}; - wildcard bins cv_subnr = {INSTR_CV_SUBNR}; - wildcard bins cv_subunr = {INSTR_CV_SUBUNR}; - wildcard bins cv_subrnr = {INSTR_CV_SUBRNR}; - wildcard bins cv_suburnr = {INSTR_CV_SUBURNR}; - wildcard bins cv_mac = {INSTR_CV_MAC}; - wildcard bins cv_msu = {INSTR_CV_MSU}; - wildcard bins cv_extract = {INSTR_CV_EXTRACT}; - wildcard bins cv_extractu = {INSTR_CV_EXTRACTU}; - wildcard bins cv_insert = {INSTR_CV_INSERT}; - wildcard bins cv_bclr = {INSTR_CV_BCLR}; - wildcard bins cv_bset = {INSTR_CV_BSET}; - wildcard bins cv_bitrev = {INSTR_CV_BITREV}; - wildcard bins cv_addn = {INSTR_CV_ADDN}; - wildcard bins cv_addun = {INSTR_CV_ADDUN}; - wildcard bins cv_addrn = {INSTR_CV_ADDRN}; - wildcard bins cv_addurn = {INSTR_CV_ADDURN}; - wildcard bins cv_subn = {INSTR_CV_SUBN}; - wildcard bins cv_subun = {INSTR_CV_SUBUN}; - wildcard bins cv_subrn = {INSTR_CV_SUBRN}; - wildcard bins cv_suburn = {INSTR_CV_SUBURN}; - wildcard bins cv_mulsn = {INSTR_CV_MULSN}; - wildcard bins cv_mulhhsn = {INSTR_CV_MULHHSN}; - wildcard bins cv_mulsrn = {INSTR_CV_MULSRN}; - wildcard bins cv_mulhhsrn = {INSTR_CV_MULHHSRN}; - wildcard bins cv_mulun = {INSTR_CV_MULUN}; - wildcard bins cv_mulhhun = {INSTR_CV_MULHHUN}; - wildcard bins cv_mulurn = {INSTR_CV_MULURN}; - wildcard bins cv_mulhhurn = {INSTR_CV_MULHHURN}; - wildcard bins cv_macsn = {INSTR_CV_MACSN}; - wildcard bins cv_machhsn = {INSTR_CV_MACHHSN}; - wildcard bins cv_macsrn = {INSTR_CV_MACSRN}; - wildcard bins cv_machhsrn = {INSTR_CV_MACHHSRN}; - wildcard bins cv_macun = {INSTR_CV_MACUN}; - wildcard bins cv_machhun = {INSTR_CV_MACHHUN}; - wildcard bins cv_macurn = {INSTR_CV_MACURN}; - wildcard bins cv_machhurn = {INSTR_CV_MACHHURN}; - wildcard bins cv_add_h = {INSTR_CV_ADD_H}; - wildcard bins cv_add_sc_h = {INSTR_CV_ADD_SC_H}; - wildcard bins cv_add_sci_h = {INSTR_CV_ADD_SCI_H}; - wildcard bins cv_add_b = {INSTR_CV_ADD_B}; - wildcard bins cv_add_sc_b = {INSTR_CV_ADD_SC_B}; - wildcard bins cv_add_sci_b = {INSTR_CV_ADD_SCI_B}; - wildcard bins cv_sub_h = {INSTR_CV_SUB_H}; - wildcard bins cv_sub_sc_h = {INSTR_CV_SUB_SC_H}; - wildcard bins cv_sub_sci_h = {INSTR_CV_SUB_SCI_H}; - wildcard bins cv_sub_b = {INSTR_CV_SUB_B}; - wildcard bins cv_sub_sc_b = {INSTR_CV_SUB_SC_B}; - wildcard bins cv_sub_sci_b = {INSTR_CV_SUB_SCI_B}; - wildcard bins cv_avg_h = {INSTR_CV_AVG_H}; - wildcard bins cv_avg_sc_h = {INSTR_CV_AVG_SC_H}; - wildcard bins cv_avg_sci_h = {INSTR_CV_AVG_SCI_H}; - wildcard bins cv_avg_b = {INSTR_CV_AVG_B}; - wildcard bins cv_avg_sc_b = {INSTR_CV_AVG_SC_B}; - wildcard bins cv_avg_sci_b = {INSTR_CV_AVG_SCI_B}; - wildcard bins cv_avgu_h = {INSTR_CV_AVGU_H}; - wildcard bins cv_avgu_sc_h = {INSTR_CV_AVGU_SC_H}; - wildcard bins cv_avgu_sci_h = {INSTR_CV_AVGU_SCI_H}; - wildcard bins cv_avgu_b = {INSTR_CV_AVGU_B}; - wildcard bins cv_avgu_sc_b = {INSTR_CV_AVGU_SC_B}; - wildcard bins cv_avgu_sci_b = {INSTR_CV_AVGU_SCI_B}; - wildcard bins cv_min_h = {INSTR_CV_MIN_H}; - wildcard bins cv_min_sc_h = {INSTR_CV_MIN_SC_H}; - wildcard bins cv_min_sci_h = {INSTR_CV_MIN_SCI_H}; - wildcard bins cv_min_b = {INSTR_CV_MIN_B}; - wildcard bins cv_min_sc_b = {INSTR_CV_MIN_SC_B}; - wildcard bins cv_min_sci_b = {INSTR_CV_MIN_SCI_B}; - wildcard bins cv_minu_h = {INSTR_CV_MINU_H}; - wildcard bins cv_minu_sc_h = {INSTR_CV_MINU_SC_H}; - wildcard bins cv_minu_sci_h = {INSTR_CV_MINU_SCI_H}; - wildcard bins cv_minu_b = {INSTR_CV_MINU_B}; - wildcard bins cv_minu_sc_b = {INSTR_CV_MINU_SC_B}; - wildcard bins cv_minu_sci_b = {INSTR_CV_MINU_SCI_B}; - wildcard bins cv_max_h = {INSTR_CV_MAX_H}; - wildcard bins cv_max_sc_h = {INSTR_CV_MAX_SC_H}; - wildcard bins cv_max_sci_h = {INSTR_CV_MAX_SCI_H}; - wildcard bins cv_max_b = {INSTR_CV_MAX_B}; - wildcard bins cv_max_sc_b = {INSTR_CV_MAX_SC_B}; - wildcard bins cv_max_sci_b = {INSTR_CV_MAX_SCI_B}; - wildcard bins cv_maxu_h = {INSTR_CV_MAXU_H}; - wildcard bins cv_maxu_sc_h = {INSTR_CV_MAXU_SC_H}; - wildcard bins cv_maxu_sci_h = {INSTR_CV_MAXU_SCI_H}; - wildcard bins cv_maxu_b = {INSTR_CV_MAXU_B}; - wildcard bins cv_maxu_sc_b = {INSTR_CV_MAXU_SC_B}; - wildcard bins cv_maxu_sci_b = {INSTR_CV_MAXU_SCI_B}; - wildcard bins cv_srl_h = {INSTR_CV_SRL_H}; - wildcard bins cv_srl_sc_h = {INSTR_CV_SRL_SC_H}; - wildcard bins cv_srl_sci_h = {INSTR_CV_SRL_SCI_H}; - wildcard bins cv_srl_b = {INSTR_CV_SRL_B}; - wildcard bins cv_srl_sc_b = {INSTR_CV_SRL_SC_B}; - wildcard bins cv_srl_sci_b = {INSTR_CV_SRL_SCI_B}; - wildcard bins cv_sra_h = {INSTR_CV_SRA_H}; - wildcard bins cv_sra_sc_h = {INSTR_CV_SRA_SC_H}; - wildcard bins cv_sra_sci_h = {INSTR_CV_SRA_SCI_H}; - wildcard bins cv_sra_b = {INSTR_CV_SRA_B}; - wildcard bins cv_sra_sc_b = {INSTR_CV_SRA_SC_B}; - wildcard bins cv_sra_sci_b = {INSTR_CV_SRA_SCI_B}; - wildcard bins cv_sll_h = {INSTR_CV_SLL_H}; - wildcard bins cv_sll_sc_h = {INSTR_CV_SLL_SC_H}; - wildcard bins cv_sll_sci_h = {INSTR_CV_SLL_SCI_H}; - wildcard bins cv_sll_b = {INSTR_CV_SLL_B}; - wildcard bins cv_sll_sc_b = {INSTR_CV_SLL_SC_B}; - wildcard bins cv_sll_sci_b = {INSTR_CV_SLL_SCI_B}; - wildcard bins cv_or_h = {INSTR_CV_OR_H}; - wildcard bins cv_or_sc_h = {INSTR_CV_OR_SC_H}; - wildcard bins cv_or_sci_h = {INSTR_CV_OR_SCI_H}; - wildcard bins cv_or_b = {INSTR_CV_OR_B}; - wildcard bins cv_or_sc_b = {INSTR_CV_OR_SC_B}; - wildcard bins cv_or_sci_b = {INSTR_CV_OR_SCI_B}; - wildcard bins cv_xor_h = {INSTR_CV_XOR_H}; - wildcard bins cv_xor_sc_h = {INSTR_CV_XOR_SC_H}; - wildcard bins cv_xor_sci_h = {INSTR_CV_XOR_SCI_H}; - wildcard bins cv_xor_b = {INSTR_CV_XOR_B}; - wildcard bins cv_xor_sc_b = {INSTR_CV_XOR_SC_B}; - wildcard bins cv_xor_sci_b = {INSTR_CV_XOR_SCI_B}; - wildcard bins cv_and_h = {INSTR_CV_AND_H}; - wildcard bins cv_and_sc_h = {INSTR_CV_AND_SC_H}; - wildcard bins cv_and_sci_h = {INSTR_CV_AND_SCI_H}; - wildcard bins cv_and_b = {INSTR_CV_AND_B}; - wildcard bins cv_and_sc_b = {INSTR_CV_AND_SC_B}; - wildcard bins cv_and_sci_b = {INSTR_CV_AND_SCI_B}; - wildcard bins cv_abs_h = {INSTR_CV_ABS_H}; - wildcard bins cv_abs_b = {INSTR_CV_ABS_B}; - wildcard bins cv_dotup_h = {INSTR_CV_DOTUP_H}; - wildcard bins cv_dotup_sc_h = {INSTR_CV_DOTUP_SC_H}; - wildcard bins cv_dotup_sci_h = {INSTR_CV_DOTUP_SCI_H}; - wildcard bins cv_dotup_b = {INSTR_CV_DOTUP_B}; - wildcard bins cv_dotup_sc_b = {INSTR_CV_DOTUP_SC_B}; - wildcard bins cv_dotup_sci_b = {INSTR_CV_DOTUP_SCI_B}; - wildcard bins cv_dotusp_h = {INSTR_CV_DOTUSP_H}; - wildcard bins cv_dotusp_sc_h = {INSTR_CV_DOTUSP_SC_H}; - wildcard bins cv_dotusp_sci_h = {INSTR_CV_DOTUSP_SCI_H}; - wildcard bins cv_dotusp_b = {INSTR_CV_DOTUSP_B}; - wildcard bins cv_dotusp_sc_b = {INSTR_CV_DOTUSP_SC_B}; - wildcard bins cv_dotusp_sci_b = {INSTR_CV_DOTUSP_SCI_B}; - wildcard bins cv_dotsp_h = {INSTR_CV_DOTSP_H}; - wildcard bins cv_dotsp_sc_h = {INSTR_CV_DOTSP_SC_H}; - wildcard bins cv_dotsp_sci_h = {INSTR_CV_DOTSP_SCI_H}; - wildcard bins cv_dotsp_b = {INSTR_CV_DOTSP_B}; - wildcard bins cv_dotsp_sc_b = {INSTR_CV_DOTSP_SC_B}; - wildcard bins cv_dotsp_sci_b = {INSTR_CV_DOTSP_SCI_B}; - wildcard bins cv_sdotup_h = {INSTR_CV_SDOTUP_H}; - wildcard bins cv_sdotup_sc_h = {INSTR_CV_SDOTUP_SC_H}; - wildcard bins cv_sdotup_sci_h = {INSTR_CV_SDOTUP_SCI_H}; - wildcard bins cv_sdotup_b = {INSTR_CV_SDOTUP_B}; - wildcard bins cv_sdotup_sc_b = {INSTR_CV_SDOTUP_SC_B}; - wildcard bins cv_sdotup_sci_b = {INSTR_CV_SDOTUP_SCI_B}; - wildcard bins cv_sdotusp_h = {INSTR_CV_SDOTUSP_H}; - wildcard bins cv_sdotusp_sc_h = {INSTR_CV_SDOTUSP_SC_H}; - wildcard bins cv_sdotusp_sci_h = {INSTR_CV_SDOTUSP_SCI_H}; - wildcard bins cv_sdotusp_b = {INSTR_CV_SDOTUSP_B}; - wildcard bins cv_sdotusp_sc_b = {INSTR_CV_SDOTUSP_SC_B}; - wildcard bins cv_sdotusp_sci_b = {INSTR_CV_SDOTUSP_SCI_B}; - wildcard bins cv_sdotsp_h = {INSTR_CV_SDOTSP_H}; - wildcard bins cv_sdotsp_sc_h = {INSTR_CV_SDOTSP_SC_H}; - wildcard bins cv_sdotsp_sci_h = {INSTR_CV_SDOTSP_SCI_H}; - wildcard bins cv_sdotsp_b = {INSTR_CV_SDOTSP_B}; - wildcard bins cv_sdotsp_sc_b = {INSTR_CV_SDOTSP_SC_B}; - wildcard bins cv_sdotsp_sci_b = {INSTR_CV_SDOTSP_SCI_B}; - wildcard bins cv_extract_h = {INSTR_CV_EXTRACT_H}; - wildcard bins cv_extract_b = {INSTR_CV_EXTRACT_B}; - wildcard bins cv_extractu_h = {INSTR_CV_EXTRACTU_H}; - wildcard bins cv_extractu_b = {INSTR_CV_EXTRACTU_B}; - wildcard bins cv_insert_h = {INSTR_CV_INSERT_H}; - wildcard bins cv_insert_b = {INSTR_CV_INSERT_B}; - wildcard bins cv_shuffle_h = {INSTR_CV_SHUFFLE_H}; - wildcard bins cv_shuffle_sci_h = {INSTR_CV_SHUFFLE_SCI_H}; - wildcard bins cv_shuffle_b = {INSTR_CV_SHUFFLE_B}; - wildcard bins cv_shufflei0_sci_b = {INSTR_CV_SHUFFLEI0_SCI_B}; - wildcard bins cv_shufflei1_sci_b = {INSTR_CV_SHUFFLEI1_SCI_B}; - wildcard bins cv_shufflei2_sci_b = {INSTR_CV_SHUFFLEI2_SCI_B}; - wildcard bins cv_shufflei3_sci_b = {INSTR_CV_SHUFFLEI3_SCI_B}; - wildcard bins cv_shuffle2_h = {INSTR_CV_SHUFFLE2_H}; - wildcard bins cv_shuffle2_b = {INSTR_CV_SHUFFLE2_B}; - wildcard bins cv_pack = {INSTR_CV_PACK}; - wildcard bins cv_pack_h = {INSTR_CV_PACK_H}; - wildcard bins cv_packhi_b = {INSTR_CV_PACKHI_B}; - wildcard bins cv_packlo_b = {INSTR_CV_PACKLO_B}; - wildcard bins cv_cmpeq_h = {INSTR_CV_CMPEQ_H}; - wildcard bins cv_cmpeq_sc_h = {INSTR_CV_CMPEQ_SC_H}; - wildcard bins cv_cmpeq_sci_h = {INSTR_CV_CMPEQ_SCI_H}; - wildcard bins cv_cmpeq_b = {INSTR_CV_CMPEQ_B}; - wildcard bins cv_cmpeq_sc_b = {INSTR_CV_CMPEQ_SC_B}; - wildcard bins cv_cmpeq_sci_b = {INSTR_CV_CMPEQ_SCI_B}; - wildcard bins cv_cmpne_h = {INSTR_CV_CMPNE_H}; - wildcard bins cv_cmpne_sc_h = {INSTR_CV_CMPNE_SC_H}; - wildcard bins cv_cmpne_sci_h = {INSTR_CV_CMPNE_SCI_H}; - wildcard bins cv_cmpne_b = {INSTR_CV_CMPNE_B}; - wildcard bins cv_cmpne_sc_b = {INSTR_CV_CMPNE_SC_B}; - wildcard bins cv_cmpne_sci_b = {INSTR_CV_CMPNE_SCI_B}; - wildcard bins cv_cmpgt_h = {INSTR_CV_CMPGT_H}; - wildcard bins cv_cmpgt_sc_h = {INSTR_CV_CMPGT_SC_H}; - wildcard bins cv_cmpgt_sci_h = {INSTR_CV_CMPGT_SCI_H}; - wildcard bins cv_cmpgt_b = {INSTR_CV_CMPGT_B}; - wildcard bins cv_cmpgt_sc_b = {INSTR_CV_CMPGT_SC_B}; - wildcard bins cv_cmpgt_sci_b = {INSTR_CV_CMPGT_SCI_B}; - wildcard bins cv_cmpge_h = {INSTR_CV_CMPGE_H}; - wildcard bins cv_cmpge_sc_h = {INSTR_CV_CMPGE_SC_H}; - wildcard bins cv_cmpge_sci_h = {INSTR_CV_CMPGE_SCI_H}; - wildcard bins cv_cmpge_b = {INSTR_CV_CMPGE_B}; - wildcard bins cv_cmpge_sc_b = {INSTR_CV_CMPGE_SC_B}; - wildcard bins cv_cmpge_sci_b = {INSTR_CV_CMPGE_SCI_B}; - wildcard bins cv_cmplt_h = {INSTR_CV_CMPLT_H}; - wildcard bins cv_cmplt_sc_h = {INSTR_CV_CMPLT_SC_H}; - wildcard bins cv_cmplt_sci_h = {INSTR_CV_CMPLT_SCI_H}; - wildcard bins cv_cmplt_b = {INSTR_CV_CMPLT_B}; - wildcard bins cv_cmplt_sc_b = {INSTR_CV_CMPLT_SC_B}; - wildcard bins cv_cmplt_sci_b = {INSTR_CV_CMPLT_SCI_B}; - wildcard bins cv_cmple_h = {INSTR_CV_CMPLE_H}; - wildcard bins cv_cmple_sc_h = {INSTR_CV_CMPLE_SC_H}; - wildcard bins cv_cmple_sci_h = {INSTR_CV_CMPLE_SCI_H}; - wildcard bins cv_cmple_b = {INSTR_CV_CMPLE_B}; - wildcard bins cv_cmple_sc_b = {INSTR_CV_CMPLE_SC_B}; - wildcard bins cv_cmple_sci_b = {INSTR_CV_CMPLE_SCI_B}; - wildcard bins cv_cmpgtu_h = {INSTR_CV_CMPGTU_H}; - wildcard bins cv_cmpgtu_sc_h = {INSTR_CV_CMPGTU_SC_H}; - wildcard bins cv_cmpgtu_sci_h = {INSTR_CV_CMPGTU_SCI_H}; - wildcard bins cv_cmpgtu_b = {INSTR_CV_CMPGTU_B}; - wildcard bins cv_cmpgtu_sc_b = {INSTR_CV_CMPGTU_SC_B}; - wildcard bins cv_cmpgtu_sci_b = {INSTR_CV_CMPGTU_SCI_B}; - wildcard bins cv_cmpgeu_h = {INSTR_CV_CMPGEU_H}; - wildcard bins cv_cmpgeu_sc_h = {INSTR_CV_CMPGEU_SC_H}; - wildcard bins cv_cmpgeu_sci_h = {INSTR_CV_CMPGEU_SCI_H}; - wildcard bins cv_cmpgeu_b = {INSTR_CV_CMPGEU_B}; - wildcard bins cv_cmpgeu_sc_b = {INSTR_CV_CMPGEU_SC_B}; - wildcard bins cv_cmpgeu_sci_b = {INSTR_CV_CMPGEU_SCI_B}; - wildcard bins cv_cmpltu_h = {INSTR_CV_CMPLTU_H}; - wildcard bins cv_cmpltu_sc_h = {INSTR_CV_CMPLTU_SC_H}; - wildcard bins cv_cmpltu_sci_h = {INSTR_CV_CMPLTU_SCI_H}; - wildcard bins cv_cmpltu_b = {INSTR_CV_CMPLTU_B}; - wildcard bins cv_cmpltu_sc_b = {INSTR_CV_CMPLTU_SC_B}; - wildcard bins cv_cmpltu_sci_b = {INSTR_CV_CMPLTU_SCI_B}; - wildcard bins cv_cmpleu_h = {INSTR_CV_CMPLEU_H}; - wildcard bins cv_cmpleu_sc_h = {INSTR_CV_CMPLEU_SC_H}; - wildcard bins cv_cmpleu_sci_h = {INSTR_CV_CMPLEU_SCI_H}; - wildcard bins cv_cmpleu_b = {INSTR_CV_CMPLEU_B}; - wildcard bins cv_cmpleu_sc_b = {INSTR_CV_CMPLEU_SC_B}; - wildcard bins cv_cmpleu_sci_b = {INSTR_CV_CMPLEU_SCI_B}; - wildcard bins cv_cplxmul_r = {INSTR_CV_CPLXMUL_R}; - wildcard bins cv_cplxmul_r_div2 = {INSTR_CV_CPLXMUL_R_DIV2}; - wildcard bins cv_cplxmul_r_div4 = {INSTR_CV_CPLXMUL_R_DIV4}; - wildcard bins cv_cplxmul_r_div8 = {INSTR_CV_CPLXMUL_R_DIV8}; - wildcard bins cv_cplxmul_i = {INSTR_CV_CPLXMUL_I}; - wildcard bins cv_cplxmul_i_div2 = {INSTR_CV_CPLXMUL_I_DIV2}; - wildcard bins cv_cplxmul_i_div4 = {INSTR_CV_CPLXMUL_I_DIV4}; - wildcard bins cv_cplxmul_i_div8 = {INSTR_CV_CPLXMUL_I_DIV8}; - wildcard bins cv_cplxconj = {INSTR_CV_CPLXCONJ}; - wildcard bins cv_subrotmj = {INSTR_CV_SUBROTMJ}; - wildcard bins cv_subrotmj_div2 = {INSTR_CV_SUBROTMJ_DIV2}; - wildcard bins cv_subrotmj_div4 = {INSTR_CV_SUBROTMJ_DIV4}; - wildcard bins cv_subrotmj_div8 = {INSTR_CV_SUBROTMJ_DIV8}; - wildcard bins cv_add_div2 = {INSTR_CV_ADD_DIV2}; - wildcard bins cv_add_div4 = {INSTR_CV_ADD_DIV4}; - wildcard bins cv_add_div8 = {INSTR_CV_ADD_DIV8}; - wildcard bins cv_sub_div2 = {INSTR_CV_SUB_DIV2}; - wildcard bins cv_sub_div4 = {INSTR_CV_SUB_DIV4}; - wildcard bins cv_sub_div8 = {INSTR_CV_SUB_DIV8}; - } - - //cross xpulp instr while in debug mode - xpulp_instructions_in_dbg_mode : cross dm, xpulp_instruction; - - //cross xpulp instr excution at debug req - dbg_req_at_xpulp_instr : cross dbg_req, xpulp_instruction; - - //cross debug single stepping for each xpulp instr - dbg_single_step_xpulp_instr : cross step, xpulp_instruction; + cp_xpulp_instr : coverpoint cntxt.debug_cov_vif.mon_cb.id_stage_instr_rdata_i iff (cntxt.debug_cov_vif.mon_cb.id_stage_instr_valid_i == 1) { + `RV32X_PULP_INSTR_BINS + } + + // cross xpulp instr while in debug mode + cr_xpulp_instructions_in_dbg_mode : cross cp_dm, cp_xpulp_instr; + + // cross xpulp instr execution at debug req only - no trigger + cr_dbg_req_at_xpulp_instr : cross cp_dbg_req, cp_xpulp_instr, cp_trigger_match { + ignore_bins no_trigger_match = binsof(cp_trigger_match) intersect {1}; + } + + // cross debug single stepping for each xpulp instr - no trigger + cr_dbg_single_step_xpulp_instr : cross cp_step, cp_xpulp_instr, cp_trigger_match { + ignore_bins single_step_disable = binsof(cp_step) intersect {0}; + ignore_bins no_trigger_match = binsof(cp_trigger_match) intersect {1}; + } + + // cross debug entry with trigger addr match at xpulp inst + cr_trigger_with_xpulp_instr : cross cp_trigger_match, cp_trigger_en, cp_xpulp_instr; endgroup @@ -901,7 +626,7 @@ function uvme_debug_covg::new(string name = "debug_covg", uvm_component parent = cg_debug_at_reset = new(); cg_fence_in_debug = new(); cg_debug_causes = new(); - cg_debug_with_f_inst = new(); + cg_debug_with_rv32f_inst = new(); cg_debug_with_xpulp_inst = new(); endfunction : new @@ -958,7 +683,7 @@ task uvme_debug_covg::sample_clk_i(); cg_debug_at_reset.sample(); cg_fence_in_debug.sample(); cg_debug_causes.sample(); - cg_debug_with_f_inst.sample(); + cg_debug_with_rv32f_inst.sample(); cg_debug_with_xpulp_inst.sample(); end endtask : sample_clk_i diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index c9844c1132..7e1360e621 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -23,6 +23,7 @@ // 2) It uses uvmt_cv32e40p_rvvi_if // 3) Has covergroup for hwloops csr setup registers // 4) Has covergroup for hwloops features and events within hwloops such as exception, irq and debug entry (debug covers haltreq, trigger, ebreakm, step) +// 5) Improvement[Optional]: hwloop_stat_sub for handle (irq/debug) implementation `ifndef UVME_RV32X_HWLOOP_COVG `define UVME_RV32X_HWLOOP_COVG @@ -37,12 +38,19 @@ class uvme_rv32x_hwloop_covg # ( localparam CSR_LPSTART0_ADDR = 32'hCC0; localparam CSR_LPEND0_ADDR = 32'hCC1; localparam CSR_LPCOUNT0_ADDR = 32'hCC2; - localparam INSN_CEBREAK = 32'h00009002; // compress ebreak + localparam INSTR_CBREAK = 32'h9002; localparam INSN_ILLEGAL = 32'hFFFFFFFF; // user-defined for any illegal insn that leads to illegal exception localparam INSN_EBREAKM = 32'hFFFFFFFE; // user-defined - typedef enum bit [1:0] {NULL_TYPE=0, SINGLE, NESTED} hwloop_type_t; - typedef enum bit [1:0] {NULL_SETUP=0, SHORT, LONG} hwloop_setup_t; + typedef enum bit [1:0] {NULL_TYPE=0, SINGLE, NESTED} hwloop_type_t; + typedef enum bit [1:0] {NULL_SETUP=0, SHORT, LONG} hwloop_setup_t; + typedef enum int {EXCP_EBREAK=0, EXCP_ECALL, EXCP_ILLEGAL, + IS_IRQ, DBG_HALTREQ, DBG_EBREAKM, DBG_TRIG, + DBG_STEP, MC_INSN, TOTAL_EVENT=9} hwloop_evt_t; + typedef enum int {LOC_LPSTART=0, LOC_LPSTART_P4, + LOC_LPEND, LOC_LPEND_M4, + LOC_OTHERS, TOTAL_LOC=5} hwloop_evt_loc_t; + typedef struct { bit [31:0] lp_start [HWLOOP_NB]; bit [31:0] lp_end [HWLOOP_NB]; @@ -52,37 +60,66 @@ class uvme_rv32x_hwloop_covg # ( bit lp_count_wb [HWLOOP_NB]; } s_csr_hwloop; typedef struct { - hwloop_type_t hwloop_type; - hwloop_setup_t hwloop_setup [HWLOOP_NB]; - s_csr_hwloop hwloop_csr; - bit sample_hwloop_csr_done [HWLOOP_NB]; - bit execute_instr_in_hwloop [HWLOOP_NB]; - int track_lp_count [HWLOOP_NB]; + hwloop_type_t hwloop_type; + hwloop_setup_t hwloop_setup [HWLOOP_NB]; + s_csr_hwloop hwloop_csr; + bit sample_hwloop_csr_done [HWLOOP_NB]; + bit execute_instr_in_hwloop [HWLOOP_NB]; + int track_lp_cnt [HWLOOP_NB]; + int unsigned dbg_haltreq_cnt [HWLOOP_NB]; + int unsigned dbg_ebreakm_cnt [HWLOOP_NB]; + int unsigned dbg_trigger_cnt [HWLOOP_NB]; + int unsigned dbg_step_cnt [HWLOOP_NB]; + int unsigned excp_ebreak_cnt [HWLOOP_NB]; + int unsigned excp_ecall_cnt [HWLOOP_NB]; + int unsigned excp_illegal_cnt [HWLOOP_NB]; } s_hwloop_stat; + typedef struct { + bit en_cov_irq ; + bit en_cov_dbg_haltreq ; + bit en_cov_dbg_ebreakm ; + bit en_cov_dbg_trigger ; + bit en_cov_dbg_step_cnt ; + bit en_cov_dbg_step_cnt_loc ; + bit en_cov_excp_ebreak ; + bit en_cov_excp_ecall ; + bit en_cov_excp_illegal ; + bit en_cov_mc_insn ; + bit en_cov_insn ; + bit en_cov_event_loc ; + } s_hwloop_cov; // PROPERTIES - START - local s_csr_hwloop csr_hwloop_init = '{default:0}; - local s_hwloop_stat hwloop_stat_init = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; `define DEF_LOCAL_VARS(TYPE) \ - local s_csr_hwloop csr_hwloop_``TYPE = '{default:0}; \ - local s_hwloop_stat hwloop_stat_``TYPE = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; \ - local bit [(ILEN-1):0] insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ - local bit [31:0] irq_vect_``TYPE [HWLOOP_NB][$]; \ - local bit debug_req_``TYPE [HWLOOP_NB] = '{default:0}; \ - local bit dbg_trigger_``TYPE [HWLOOP_NB] = '{default:0}; \ - local int unsigned dbg_step_cnt_``TYPE [HWLOOP_NB] = '{default:0}; \ - local bit done_insn_list_capture_``TYPE [HWLOOP_NB] = '{default:0}; + local s_csr_hwloop csr_hwloop_``TYPE = '{default:0}; \ + local s_hwloop_stat hwloop_stat_``TYPE = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; \ + local logic [31:0] prev_pc_rdata_``TYPE = '{default:0}; \ + local hwloop_evt_loc_t hwloop_evt_loc_``TYPE [HWLOOP_NB][hwloop_evt_t][$]; \ + local bit [(ILEN-1):0] insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ + local bit [(ILEN-1):0] mc_insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ + local bit [31:0] irq_vect_``TYPE [HWLOOP_NB][$]; \ + local bit lpend_has_pending_irq_``TYPE [HWLOOP_NB] = '{default:0}; \ + local bit done_insn_list_capture_``TYPE [HWLOOP_NB] = '{default:0}; \ + local bit done_insn_list_capture_d1_``TYPE [HWLOOP_NB] = '{default:0}; \ + local s_hwloop_cov hwloop_cov_``TYPE [HWLOOP_NB] = '{default:0}; `DEF_LOCAL_VARS(main) `DEF_LOCAL_VARS(sub) + `DEF_LOCAL_VARS(init) - virtual uvmt_cv32e40p_rvvi_if #( .XLEN(XLEN), .ILEN(ILEN)) cv32e40p_rvvi_vif; - string _header = "XPULPV2_HWLOOP_COV"; - bit en_cvg_sampling = 1; - bit in_nested_loop0 = 0; - bit is_ebreak = 0, is_ebreakm, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0; - bit enter_hwloop_sub = 0; + virtual uvmt_cv32e40p_rvvi_if #( .XLEN(XLEN), .ILEN(ILEN)) cv32e40p_rvvi_vif; + string _header = "XPULPV2_HWLOOP_COV"; + bit en_cvg_sampling = 1; + bit in_nested_loop0 = 0, in_nested_loop0_d1 = 0; + bit is_ebreak = 0, is_ebreakm = 0, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0, is_mc_insn = 0; + bit is_trap = 0; // trap any period that is redundant due to handling entry which causes data flush + bit has_pending_trap_due2_dbg = 0; // trap pending due to debug mode entry + bit enter_hwloop_sub = 0; + int enter_hwloop_sub_cnt = 0; + bit pending_irq = 0; + logic [31:0] prev_irq_onehot_priority = 0, prev_irq_onehot_priority_always = 0; + bit prev_irq_onehot_priority_is_0 = 0; dcsr_cause_t dcsr_cause; exception_code_t exception_code; @@ -112,10 +149,10 @@ class uvme_rv32x_hwloop_covg # ( } \ cp_lpcount_``LOOP_IDX : coverpoint (csr_hwloop.lp_count[``LOOP_IDX``]) iff (csr_hwloop.lp_start_wb[``LOOP_IDX``] && csr_hwloop.lp_end_wb[``LOOP_IDX``] && csr_hwloop.lp_count_wb[``LOOP_IDX``]) { \ // bins lpcount_zero = {32'h0}; // valid CSR writes to sample should be when lpcount{0/1}.value != 0 \ - bins lpcount_range_low_1 = {[32'h0000_00FF : 32'h0000_0001]}; // 1 <= x <255 \ - bins lpcount_range_low_2 = {[32'h0000_1FFF : 32'h0000_0100]}; // 256 <= x < 4K \ - // bins lpcount_range_middle = {[32'h00FF_FFFF : 32'h0000_1000]}; // 4K <= x < 16M \ - // bins lpcount_range_high = {[32'hFFFF_FFFF : 32'h0100_0000]}; // 16M <= x < 4G \ + bins lpcount_range_low_1 = {[32'h0000_0190 : 32'h0000_0001]}; // count 0-400 \ + bins lpcount_range_low_2 = {[32'h0000_03FF : 32'h0000_0191]}; // count 401-1023 \ + bins lpcount_range_low_3 = {[32'h0000_0FFE : 32'h0000_0400]}; // count 1024-4094 \ + bins lpcount_range_low_4 = {32'h0000_0FFF}; // 4095 \ // higher counts are not covered now to reduced simtime (amend if needed) \ } \ ccp_lpstart_0_lpend_lpcount_``LOOP_IDX : cross cp_lpstart_``LOOP_IDX``, cp_lpend_``LOOP_IDX``, cp_lpcount_``LOOP_IDX`` { \ @@ -137,7 +174,7 @@ class uvme_rv32x_hwloop_covg # ( `define CG_FEATURES_OF_HWLOOP(LOOP_IDX) cg_features_of_hwloop_``LOOP_IDX`` `define DEF_CG_FEATURES_OF_HWLOOP(LOOP_IDX) covergroup cg_features_of_hwloop_``LOOP_IDX with function \ - sample(s_hwloop_stat hwloop_stat, bit [31:0] insn, bit [31:0] irq, bit dbg_haltreq, bit dbg_trigger, int unsigned dbg_step_cnt); \ + sample(int lp_idx, s_hwloop_stat hwloop_stat, s_hwloop_cov hwloop_cov, bit [31:0] insn=32'b0, bit [31:0] irq=32'b0, hwloop_evt_loc_t evt_loc=TOTAL_LOC); \ option.per_instance = 1; \ `ifdef MODEL_TECH \ option.get_inst_coverage = 1; \ @@ -153,7 +190,7 @@ class uvme_rv32x_hwloop_covg # ( bins long_hwloop_setup = {LONG}; \ illegal_bins invalid = default; \ } \ - cp_hwloop_irq : coverpoint (irq) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + cp_hwloop_irq : coverpoint (irq) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_irq) { \ // priority order (high->low) : irq[31]...irq[16], irq[11], irq[3], irq[7] \ bins vec_irq_1hot_priority[] = {32'h0000_0008, \ 32'h0000_0080, \ @@ -163,461 +200,94 @@ class uvme_rv32x_hwloop_covg # ( 32'h0100_0000, 32'h0200_0000, 32'h0400_0000, 32'h0800_0000, \ 32'h1000_0000, 32'h2000_0000, 32'h4000_0000, 32'h8000_0000}; \ } \ - cp_hwloop_dbg_haltreq : coverpoint (dbg_haltreq) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ - bins dbg_haltreq = {1}; \ + cp_hwloop_dbg_haltreq : coverpoint (hwloop_stat.dbg_haltreq_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_haltreq) { \ + bins dbg_haltreq = {[1:$]}; \ + } \ + cp_hwloop_dbg_ebreakm : coverpoint (hwloop_stat.dbg_ebreakm_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_ebreakm) { \ + bins dbg_ebreakm = {[1:$]}; \ + } \ + cp_hwloop_dbg_trigger : coverpoint (hwloop_stat.dbg_trigger_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_trigger) { \ + bins dbg_trigger = {[1:$]}; \ + } \ + cp_hwloop_dbg_step_cnt : coverpoint (hwloop_stat.dbg_step_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_step_cnt) { \ + bins dbg_step_range_1 = {[1:4]}; \ + bins dbg_step_range_2 = {[5:20]}; \ + bins dbg_step_range_3 = {[20:50]}; \ + bins dbg_step_range_4 = {[51:$]}; \ + } \ + cp_hwloop_dbg_step_cnt_loc : coverpoint (hwloop_stat.dbg_step_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_step_cnt_loc) { \ + bins dbg_step_cnt_loc = {[1:$]}; \ + } \ + cp_hwloop_excp_ebreak : coverpoint (hwloop_stat.excp_ebreak_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_excp_ebreak) { \ + bins excp_ebreak = {[1:$]}; \ + } \ + cp_hwloop_excp_ecall : coverpoint (hwloop_stat.excp_ecall_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_excp_ecall) { \ + bins excp_ecall = {[1:$]}; \ } \ - cp_hwloop_dbg_trigger : coverpoint (dbg_trigger) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ - bins dbg_trigger = {1}; \ + cp_hwloop_excp_illegal : coverpoint (hwloop_stat.excp_illegal_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_excp_illegal) { \ + bins excp_illegal = {[1:$]}; \ } \ - cp_hwloop_dbg_step_cnt : coverpoint (dbg_step_cnt) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ - bins dbg_step_range_1 = {[1:4]}; \ - bins dbg_step_range_2 = {[5:20]}; \ - bins dbg_step_range_3 = {[20:50]}; \ - bins dbg_step_range_4 = {[51:$]}; \ + cp_hwloop_mc_insn : coverpoint (insn) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_mc_insn) { \ + // RV32F \ + `RV32F_INSTR_BINS \ + // RV32M \ + wildcard bins div = {TB_INSTR_DIV}; \ + wildcard bins divu = {TB_INSTR_DIVU}; \ + wildcard bins rem = {TB_INSTR_REM}; \ + wildcard bins remu = {TB_INSTR_REMU}; \ + wildcard bins pmuh = {TB_INSTR_PMUH}; \ + wildcard bins pmulhsu = {TB_INSTR_PMULHSU}; \ + wildcard bins pmulhu = {TB_INSTR_PMULHU}; \ + } \ + cp_hwloop_loc : coverpoint (evt_loc) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_event_loc) { \ + bins loc_lpstart = {LOC_LPSTART}; \ + bins loc_lpstart_plus4 = {LOC_LPSTART_P4}; \ + bins loc_lpend = {LOC_LPEND}; \ + bins loc_lpend_minus4 = {LOC_LPEND_M4}; \ + bins loc_others = {LOC_OTHERS}; \ } \ // note: hwloop setup custom instructions are not allow in hwloop_0 (manual exclusion needed) \ - cp_insn_list_in_hwloop : coverpoint (insn) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ - wildcard bins instr_lui = {INSTR_LUI}; \ - wildcard bins instr_auipc = {INSTR_AUIPC}; \ + cp_insn_list_in_hwloop : coverpoint (insn) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_insn) { \ + wildcard bins lui = {TB_INSTR_LUI}; \ + wildcard bins auipc = {TB_INSTR_AUIPC}; \ // OPIMM \ - wildcard bins instr_addi = {INSTR_ADDI}; \ - wildcard bins instr_slti = {INSTR_SLTI}; \ - wildcard bins instr_sltiu = {INSTR_SLTIU}; \ - wildcard bins instr_xori = {INSTR_XORI}; \ - wildcard bins instr_ori = {INSTR_ORI}; \ - wildcard bins instr_andi = {INSTR_ANDI}; \ - wildcard bins instr_slli = {INSTR_SLLI}; \ - wildcard bins instr_srli = {INSTR_SRLI}; \ - wildcard bins instr_srai = {INSTR_SRAI}; \ + `OPIMM_INSTR_BINS \ // OP \ - wildcard bins instr_add = {INSTR_ADD}; \ - wildcard bins instr_sub = {INSTR_SUB}; \ - wildcard bins instr_sll = {INSTR_SLL}; \ - wildcard bins instr_slt = {INSTR_SLT}; \ - wildcard bins instr_sltu = {INSTR_SLTU}; \ - wildcard bins instr_xor = {INSTR_XOR}; \ - wildcard bins instr_srl = {INSTR_SRL}; \ - wildcard bins instr_sra = {INSTR_SRA}; \ - wildcard bins instr_or = {INSTR_OR}; \ - wildcard bins instr_and = {INSTR_AND}; \ - wildcard bins instr_pavg = {INSTR_PAVG}; \ - wildcard bins instr_pavgu = {INSTR_PAVGU}; \ + `OP_INSTR_BINS \ // SYSTEM \ - wildcard bins instr_csrrw = {INSTR_CSRRW}; \ - wildcard bins instr_csrrs = {INSTR_CSRRS}; \ - wildcard bins instr_csrrc = {INSTR_CSRRC}; \ - wildcard bins instr_csrrwi = {INSTR_CSRRWI}; \ - wildcard bins instr_csrrsi = {INSTR_CSRRSI}; \ - wildcard bins instr_csrrci = {INSTR_CSRRCI}; \ - wildcard bins instr_ecall = {INSTR_ECALL}; \ - wildcard bins instr_ebreak = {INSTR_EBREAK}; \ + wildcard bins csrrw = {TB_INSTR_CSRRW}; \ + wildcard bins csrrs = {TB_INSTR_CSRRS}; \ + wildcard bins csrrc = {TB_INSTR_CSRRC}; \ + wildcard bins csrrwi = {TB_INSTR_CSRRWI}; \ + wildcard bins csrrsi = {TB_INSTR_CSRRSI}; \ + wildcard bins csrrci = {TB_INSTR_CSRRCI}; \ + wildcard bins ecall = {TB_INSTR_ECALL}; \ + wildcard bins ebreak = {TB_INSTR_EBREAK}; \ // RV32M \ - wildcard bins instr_div = {INSTR_DIV}; \ - wildcard bins instr_divu = {INSTR_DIVU}; \ - wildcard bins instr_rem = {INSTR_REM}; \ - wildcard bins instr_remu = {INSTR_REMU}; \ - wildcard bins instr_pmul = {INSTR_PMUL}; \ - wildcard bins instr_pmuh = {INSTR_PMUH}; \ - wildcard bins instr_pmulhsu = {INSTR_PMULHSU}; \ - wildcard bins instr_pmulhu = {INSTR_PMULHU}; \ + `RV32M_INSTR_BINS \ // RV32F \ - wildcard bins instr_fmadd = {INSTR_FMADD}; \ - wildcard bins instr_fmsub = {INSTR_FMSUB}; \ - wildcard bins instr_fnmsub = {INSTR_FNMSUB}; \ - wildcard bins instr_fnmadd = {INSTR_FNMADD}; \ - wildcard bins instr_fadd = {INSTR_FADD}; \ - wildcard bins instr_fsub = {INSTR_FSUB}; \ - wildcard bins instr_fmul = {INSTR_FMUL}; \ - wildcard bins instr_fdiv = {INSTR_FDIV}; \ - wildcard bins instr_fsqrt = {INSTR_FSQRT}; \ - wildcard bins instr_fsgnjs = {INSTR_FSGNJS}; \ - wildcard bins instr_fsgnjns = {INSTR_FSGNJNS}; \ - wildcard bins instr_fsgnjxs = {INSTR_FSGNJXS}; \ - wildcard bins instr_fmin = {INSTR_FMIN}; \ - wildcard bins instr_fmax = {INSTR_FMAX}; \ - wildcard bins instr_fcvtws = {INSTR_FCVTWS}; \ - wildcard bins instr_fcvtwus = {INSTR_FCVTWUS}; \ - wildcard bins instr_fmvxs = {INSTR_FMVXS}; \ - wildcard bins instr_feqs = {INSTR_FEQS}; \ - wildcard bins instr_flts = {INSTR_FLTS}; \ - wildcard bins instr_fles = {INSTR_FLES}; \ - wildcard bins instr_fclass = {INSTR_FCLASS}; \ - wildcard bins instr_fcvtsw = {INSTR_FCVTSW}; \ - wildcard bins instr_fcvtswu = {INSTR_FCVTSWU}; \ - wildcard bins instr_fmvsx = {INSTR_FMVSX}; \ + `RV32F_INSTR_BINS \ // LOAD STORE \ - wildcard bins instr_lb = {INSTR_LB}; \ - wildcard bins instr_lh = {INSTR_LH}; \ - wildcard bins instr_lw = {INSTR_LW}; \ - wildcard bins instr_lbu = {INSTR_LBU}; \ - wildcard bins instr_lhu = {INSTR_LHU}; \ - wildcard bins instr_sb = {INSTR_SB}; \ - wildcard bins instr_sh = {INSTR_SH}; \ - wildcard bins instr_sw = {INSTR_SW}; \ - // CUSTOM_0 \ - // Post-Increment Register-Immediate Load \ - wildcard bins instr_cvlbi = {INSTR_CVLBI}; \ - wildcard bins instr_cvlbui = {INSTR_CVLBUI}; \ - wildcard bins instr_cvlhi = {INSTR_CVLHI}; \ - wildcard bins instr_cvlhui = {INSTR_CVLHUI}; \ - wildcard bins instr_cvlwi = {INSTR_CVLWI}; \ - // Event Load \ - wildcard bins instr_cvelw = {INSTR_CVELW}; \ - // CUSTOM_1 \ - // Post-Increment Register-Register Load \ - wildcard bins instr_cvlbr = {INSTR_CVLBR}; \ - wildcard bins instr_cvlbur = {INSTR_CVLBUR}; \ - wildcard bins instr_cvlhr = {INSTR_CVLHR}; \ - wildcard bins instr_cvlhur = {INSTR_CVLHUR}; \ - wildcard bins instr_cvlwr = {INSTR_CVLWR}; \ - // Register-Register Load \ - wildcard bins instr_cvlbrr = {INSTR_CVLBRR}; \ - wildcard bins instr_cvlburr = {INSTR_CVLBURR}; \ - wildcard bins instr_cvlhrr = {INSTR_CVLHRR}; \ - wildcard bins instr_cvlhurr = {INSTR_CVLHURR}; \ - wildcard bins instr_cvlwrr = {INSTR_CVLWRR}; \ - // Post-Increment Register-Immediate Store \ - wildcard bins instr_cvsbi = {INSTR_CVSBI}; \ - wildcard bins instr_cvshi = {INSTR_CVSHI}; \ - wildcard bins instr_cvswi = {INSTR_CVSWI}; \ - // Post-Increment Register-Register Store operations encoding \ - wildcard bins instr_cvsbr = {INSTR_CVSBR}; \ - wildcard bins instr_cvshr = {INSTR_CVSHR}; \ - wildcard bins instr_cvswr = {INSTR_CVSWR}; \ - // Register-Register Store operations \ - wildcard bins instr_cvsbrr = {INSTR_CVSBRR}; \ - wildcard bins instr_cvshrr = {INSTR_CVSHRR}; \ - wildcard bins instr_cvswrr = {INSTR_CVSWRR}; \ - // Hardware Loops \ - wildcard bins instr_cvstarti0 = {INSTR_CVSTARTI0}; \ - wildcard bins instr_cvstart0 = {INSTR_CVSTART0}; \ - wildcard bins instr_cvsendi0 = {INSTR_CVSENDI0}; \ - wildcard bins instr_cvend0 = {INSTR_CVEND0}; \ - wildcard bins instr_cvcounti0 = {INSTR_CVCOUNTI0}; \ - wildcard bins instr_cvcount0 = {INSTR_CVCOUNT0}; \ - wildcard bins instr_cvsetupi0 = {INSTR_CVSETUPI0}; \ - wildcard bins instr_cvsetup0 = {INSTR_CVSETUP0}; \ - wildcard bins instr_cvstarti1 = {INSTR_CVSTARTI1}; \ - wildcard bins instr_cvstart1 = {INSTR_CVSTART1}; \ - wildcard bins instr_cvsendi1 = {INSTR_CVSENDI1}; \ - wildcard bins instr_cvend1 = {INSTR_CVEND1}; \ - wildcard bins instr_cvcounti1 = {INSTR_CVCOUNTI1}; \ - wildcard bins instr_cvcount1 = {INSTR_CVCOUNT1}; \ - wildcard bins instr_cvsetupi1 = {INSTR_CVSETUPI1}; \ - wildcard bins instr_cvsetup1 = {INSTR_CVSETUP1}; \ - wildcard bins instr_ff1 = {INSTR_FF1}; \ - wildcard bins instr_fl1 = {INSTR_FL1}; \ - wildcard bins instr_clb = {INSTR_CLB}; \ - wildcard bins instr_cnt = {INSTR_CNT}; \ - wildcard bins instr_exths = {INSTR_EXTHS}; \ - wildcard bins instr_exthz = {INSTR_EXTHZ}; \ - wildcard bins instr_extbs = {INSTR_EXTBS}; \ - wildcard bins instr_extbz = {INSTR_EXTBZ}; \ - wildcard bins instr_paddnr = {INSTR_PADDNR}; \ - wildcard bins instr_paddunr = {INSTR_PADDUNR}; \ - wildcard bins instr_paddrnr = {INSTR_PADDRNR}; \ - wildcard bins instr_paddurnr = {INSTR_PADDURNR}; \ - wildcard bins instr_psubnr = {INSTR_PSUBNR}; \ - wildcard bins instr_psubunr = {INSTR_PSUBUNR}; \ - wildcard bins instr_psubrnr = {INSTR_PSUBRNR}; \ - wildcard bins instr_psuburnr = {INSTR_PSUBURNR}; \ - wildcard bins instr_pabs = {INSTR_PABS}; \ - wildcard bins instr_pclip = {INSTR_PCLIP}; \ - wildcard bins instr_pclipu = {INSTR_PCLIPU}; \ - wildcard bins instr_pclipr = {INSTR_PCLIPR}; \ - wildcard bins instr_pclipur = {INSTR_PCLIPUR}; \ - wildcard bins instr_pslet = {INSTR_PSLET}; \ - wildcard bins instr_psletu = {INSTR_PSLETU}; \ - wildcard bins instr_pmin = {INSTR_PMIN}; \ - wildcard bins instr_pminu = {INSTR_PMINU}; \ - wildcard bins instr_pmax = {INSTR_PMAX}; \ - wildcard bins instr_pmaxu = {INSTR_PMAXU}; \ - wildcard bins instr_ror = {INSTR_ROR}; \ - wildcard bins instr_pbextr = {INSTR_PBEXTR}; \ - wildcard bins instr_pbextur = {INSTR_PBEXTUR}; \ - wildcard bins instr_pbinsr = {INSTR_PBINSR}; \ - wildcard bins instr_pbclrr = {INSTR_PBCLRR}; \ - wildcard bins instr_pbsetr = {INSTR_PBSETR}; \ - wildcard bins instr_pmac = {INSTR_PMAC}; \ - wildcard bins instr_pmsu = {INSTR_PMSU}; \ - // CUSTOM_2 \ - wildcard bins instr_pbext = {INSTR_PBEXT}; \ - wildcard bins instr_pbextu = {INSTR_PBEXTU}; \ - wildcard bins instr_pbins = {INSTR_PBINS}; \ - wildcard bins instr_pbclr = {INSTR_PBCLR}; \ - wildcard bins instr_pbset = {INSTR_PBSET}; \ - wildcard bins instr_pbrev = {INSTR_PBREV}; \ - wildcard bins instr_paddn = {INSTR_PADDN}; \ - wildcard bins instr_paddun = {INSTR_PADDUN}; \ - wildcard bins instr_paddrn = {INSTR_PADDRN}; \ - wildcard bins instr_paddurn = {INSTR_PADDURN}; \ - wildcard bins instr_psubn = {INSTR_PSUBN}; \ - wildcard bins instr_psubun = {INSTR_PSUBUN}; \ - wildcard bins instr_psubrn = {INSTR_PSUBRN}; \ - wildcard bins instr_psuburn = {INSTR_PSUBURN}; \ - wildcard bins instr_pmulsn = {INSTR_PMULSN}; \ - wildcard bins instr_pmulhhsn = {INSTR_PMULHHSN}; \ - wildcard bins instr_pmulsrn = {INSTR_PMULSRN}; \ - wildcard bins instr_pmulhhsrn = {INSTR_PMULHHSRN}; \ - wildcard bins instr_pmulun = {INSTR_PMULUN}; \ - wildcard bins instr_pmulhhun = {INSTR_PMULHHUN}; \ - wildcard bins instr_pmulurn = {INSTR_PMULURN}; \ - wildcard bins instr_pmulhhurn = {INSTR_PMULHHURN}; \ - wildcard bins instr_pmacsn = {INSTR_PMACSN}; \ - wildcard bins instr_pmachhsn = {INSTR_PMACHHSN}; \ - wildcard bins instr_pmacsrn = {INSTR_PMACSRN}; \ - wildcard bins instr_pmachhsrn = {INSTR_PMACHHSRN}; \ - wildcard bins instr_pmacun = {INSTR_PMACUN}; \ - wildcard bins instr_pmachhun = {INSTR_PMACHHUN}; \ - wildcard bins instr_pmacurn = {INSTR_PMACURN}; \ - wildcard bins instr_pmachhurn = {INSTR_PMACHHURN}; \ - // CUSTOM_3 \ - // SIMD ALU \ - wildcard bins instr_cvaddh = {INSTR_CVADDH}; \ - wildcard bins instr_cvaddsch = {INSTR_CVADDSCH}; \ - wildcard bins instr_cvaddscih = {INSTR_CVADDSCIH}; \ - wildcard bins instr_cvaddb = {INSTR_CVADDB}; \ - wildcard bins instr_cvaddscb = {INSTR_CVADDSCB}; \ - wildcard bins instr_cvaddscib = {INSTR_CVADDSCIB}; \ - wildcard bins instr_cvsubh = {INSTR_CVSUBH}; \ - wildcard bins instr_cvsubsch = {INSTR_CVSUBSCH}; \ - wildcard bins instr_cvsubscih = {INSTR_CVSUBSCIH}; \ - wildcard bins instr_cvsubb = {INSTR_CVSUBB}; \ - wildcard bins instr_cvsubscb = {INSTR_CVSUBSCB}; \ - wildcard bins instr_cvsubscib = {INSTR_CVSUBSCIB}; \ - wildcard bins instr_cvavgh = {INSTR_CVAVGH}; \ - wildcard bins instr_cvavgsch = {INSTR_CVAVGSCH}; \ - wildcard bins instr_cvavgscih = {INSTR_CVAVGSCIH}; \ - wildcard bins instr_cvavgb = {INSTR_CVAVGB}; \ - wildcard bins instr_cvavgscb = {INSTR_CVAVGSCB}; \ - wildcard bins instr_cvavgscib = {INSTR_CVAVGSCIB}; \ - wildcard bins instr_cvavguh = {INSTR_CVAVGUH}; \ - wildcard bins instr_cvavgusch = {INSTR_CVAVGUSCH}; \ - wildcard bins instr_cvavguscih = {INSTR_CVAVGUSCIH}; \ - wildcard bins instr_cvavgub = {INSTR_CVAVGUB}; \ - wildcard bins instr_cvavguscb = {INSTR_CVAVGUSCB}; \ - wildcard bins instr_cvavguscib = {INSTR_CVAVGUSCIB}; \ - wildcard bins instr_cvminh = {INSTR_CVMINH}; \ - wildcard bins instr_cvminsch = {INSTR_CVMINSCH}; \ - wildcard bins instr_cvminscih = {INSTR_CVMINSCIH}; \ - wildcard bins instr_cvminb = {INSTR_CVMINB}; \ - wildcard bins instr_cvminscb = {INSTR_CVMINSCB}; \ - wildcard bins instr_cvminscib = {INSTR_CVMINSCIB}; \ - wildcard bins instr_cvminuh = {INSTR_CVMINUH}; \ - wildcard bins instr_cvminusch = {INSTR_CVMINUSCH}; \ - wildcard bins instr_cvminuscih = {INSTR_CVMINUSCIH}; \ - wildcard bins instr_cvminub = {INSTR_CVMINUB}; \ - wildcard bins instr_cvminuscb = {INSTR_CVMINUSCB}; \ - wildcard bins instr_cvminuscib = {INSTR_CVMINUSCIB}; \ - wildcard bins instr_cvmaxh = {INSTR_CVMAXH}; \ - wildcard bins instr_cvmaxsch = {INSTR_CVMAXSCH}; \ - wildcard bins instr_cvmaxscih = {INSTR_CVMAXSCIH}; \ - wildcard bins instr_cvmaxb = {INSTR_CVMAXB}; \ - wildcard bins instr_cvmaxscb = {INSTR_CVMAXSCB}; \ - wildcard bins instr_cvmaxscib = {INSTR_CVMAXSCIB}; \ - wildcard bins instr_cvmaxuh = {INSTR_CVMAXUH}; \ - wildcard bins instr_cvmaxusch = {INSTR_CVMAXUSCH}; \ - wildcard bins instr_cvmaxuscih = {INSTR_CVMAXUSCIH}; \ - wildcard bins instr_cvmaxub = {INSTR_CVMAXUB}; \ - wildcard bins instr_cvmaxuscb = {INSTR_CVMAXUSCB}; \ - wildcard bins instr_cvmaxuscib = {INSTR_CVMAXUSCIB}; \ - wildcard bins instr_cvsrlh = {INSTR_CVSRLH}; \ - wildcard bins instr_cvsrlsch = {INSTR_CVSRLSCH}; \ - wildcard bins instr_cvsrlscih = {INSTR_CVSRLSCIH}; \ - wildcard bins instr_cvsrlb = {INSTR_CVSRLB}; \ - wildcard bins instr_cvsrlscb = {INSTR_CVSRLSCB}; \ - wildcard bins instr_cvsrlscib = {INSTR_CVSRLSCIB}; \ - wildcard bins instr_cvsrah = {INSTR_CVSRAH}; \ - wildcard bins instr_cvsrasch = {INSTR_CVSRASCH}; \ - wildcard bins instr_cvsrascih = {INSTR_CVSRASCIH}; \ - wildcard bins instr_cvsrab = {INSTR_CVSRAB}; \ - wildcard bins instr_cvsrascb = {INSTR_CVSRASCB}; \ - wildcard bins instr_cvsrascib = {INSTR_CVSRASCIB}; \ - wildcard bins instr_cvsllh = {INSTR_CVSLLH}; \ - wildcard bins instr_cvsllsch = {INSTR_CVSLLSCH}; \ - wildcard bins instr_cvsllscih = {INSTR_CVSLLSCIH}; \ - wildcard bins instr_cvsllb = {INSTR_CVSLLB}; \ - wildcard bins instr_cvsllscb = {INSTR_CVSLLSCB}; \ - wildcard bins instr_cvsllscib = {INSTR_CVSLLSCIB}; \ - wildcard bins instr_cvorh = {INSTR_CVORH}; \ - wildcard bins instr_cvorsch = {INSTR_CVORSCH}; \ - wildcard bins instr_cvorscih = {INSTR_CVORSCIH}; \ - wildcard bins instr_cvorb = {INSTR_CVORB}; \ - wildcard bins instr_cvorscb = {INSTR_CVORSCB}; \ - wildcard bins instr_cvorscib = {INSTR_CVORSCIB}; \ - wildcard bins instr_cvxorh = {INSTR_CVXORH}; \ - wildcard bins instr_cvxorsch = {INSTR_CVXORSCH}; \ - wildcard bins instr_cvxorscih = {INSTR_CVXORSCIH}; \ - wildcard bins instr_cvxorb = {INSTR_CVXORB}; \ - wildcard bins instr_cvxorscb = {INSTR_CVXORSCB}; \ - wildcard bins instr_cvxorscib = {INSTR_CVXORSCIB}; \ - wildcard bins instr_cvandh = {INSTR_CVANDH}; \ - wildcard bins instr_cvandsch = {INSTR_CVANDSCH}; \ - wildcard bins instr_cvandscih = {INSTR_CVANDSCIH}; \ - wildcard bins instr_cvandb = {INSTR_CVANDB}; \ - wildcard bins instr_cvandscb = {INSTR_CVANDSCB}; \ - wildcard bins instr_cvandscib = {INSTR_CVANDSCIB}; \ - wildcard bins instr_cvabsh = {INSTR_CVABSH}; \ - wildcard bins instr_cvabsb = {INSTR_CVABSB}; \ - wildcard bins instr_cvextracth = {INSTR_CVEXTRACTH}; \ - wildcard bins instr_cvextractb = {INSTR_CVEXTRACTB}; \ - wildcard bins instr_cvextractuh = {INSTR_CVEXTRACTUH}; \ - wildcard bins instr_cvextractub = {INSTR_CVEXTRACTUB}; \ - wildcard bins instr_cvinserth = {INSTR_CVINSERTH}; \ - wildcard bins instr_cvinsertb = {INSTR_CVINSERTB}; \ - wildcard bins instr_cvdotuph = {INSTR_CVDOTUPH}; \ - wildcard bins instr_cvdotupsch = {INSTR_CVDOTUPSCH}; \ - wildcard bins instr_cvdotupscih = {INSTR_CVDOTUPSCIH}; \ - wildcard bins instr_cvdotupb = {INSTR_CVDOTUPB}; \ - wildcard bins instr_cvdotupscb = {INSTR_CVDOTUPSCB}; \ - wildcard bins instr_cvdotupscib = {INSTR_CVDOTUPSCIB}; \ - wildcard bins instr_cvdotusph = {INSTR_CVDOTUSPH}; \ - wildcard bins instr_cvdotuspsch = {INSTR_CVDOTUSPSCH}; \ - wildcard bins instr_cvdotuspscih = {INSTR_CVDOTUSPSCIH}; \ - wildcard bins instr_cvdotuspb = {INSTR_CVDOTUSPB}; \ - wildcard bins instr_cvdotuspscb = {INSTR_CVDOTUSPSCB}; \ - wildcard bins instr_cvdotuspscib = {INSTR_CVDOTUSPSCIB}; \ - wildcard bins instr_cvdotsph = {INSTR_CVDOTSPH}; \ - wildcard bins instr_cvdotspsch = {INSTR_CVDOTSPSCH}; \ - wildcard bins instr_cvdotspscih = {INSTR_CVDOTSPSCIH}; \ - wildcard bins instr_cvdotspb = {INSTR_CVDOTSPB}; \ - wildcard bins instr_cvdotspscb = {INSTR_CVDOTSPSCB}; \ - wildcard bins instr_cvdotspscib = {INSTR_CVDOTSPSCIB}; \ - wildcard bins instr_cvsdotuph = {INSTR_CVSDOTUPH}; \ - wildcard bins instr_cvsdotupsch = {INSTR_CVSDOTUPSCH}; \ - wildcard bins instr_cvsdotupscih = {INSTR_CVSDOTUPSCIH}; \ - wildcard bins instr_cvsdotupb = {INSTR_CVSDOTUPB}; \ - wildcard bins instr_cvsdotupscb = {INSTR_CVSDOTUPSCB}; \ - wildcard bins instr_cvsdotupscib = {INSTR_CVSDOTUPSCIB}; \ - wildcard bins instr_cvsdotusph = {INSTR_CVSDOTUSPH}; \ - wildcard bins instr_cvsdotuspsch = {INSTR_CVSDOTUSPSCH}; \ - wildcard bins instr_cvsdotuspscih = {INSTR_CVSDOTUSPSCIH}; \ - wildcard bins instr_cvsdotuspb = {INSTR_CVSDOTUSPB}; \ - wildcard bins instr_cvsdotuspscb = {INSTR_CVSDOTUSPSCB}; \ - wildcard bins instr_cvsdotuspscib = {INSTR_CVSDOTUSPSCIB}; \ - wildcard bins instr_cvsdotsph = {INSTR_CVSDOTSPH}; \ - wildcard bins instr_cvsdotspsch = {INSTR_CVSDOTSPSCH}; \ - wildcard bins instr_cvsdotspscih = {INSTR_CVSDOTSPSCIH}; \ - wildcard bins instr_cvsdotspb = {INSTR_CVSDOTSPB}; \ - wildcard bins instr_cvsdotspscb = {INSTR_CVSDOTSPSCB}; \ - wildcard bins instr_cvsdotspscib = {INSTR_CVSDOTSPSCIB}; \ - wildcard bins instr_cvshuffleh = {INSTR_CVSHUFFLEH}; \ - wildcard bins instr_cvshufflescih = {INSTR_CVSHUFFLESCIH}; \ - wildcard bins instr_cvshuffleb = {INSTR_CVSHUFFLEB}; \ - wildcard bins instr_cvshufflel0scib = {INSTR_CVSHUFFLEL0SCIB}; \ - wildcard bins instr_cvshufflel1scib = {INSTR_CVSHUFFLEL1SCIB}; \ - wildcard bins instr_cvshufflel2scib = {INSTR_CVSHUFFLEL2SCIB}; \ - wildcard bins instr_cvshufflel3scib = {INSTR_CVSHUFFLEL3SCIB}; \ - wildcard bins instr_cvshuffle2h = {INSTR_CVSHUFFLE2H}; \ - wildcard bins instr_cvshuffle2b = {INSTR_CVSHUFFLE2B}; \ - wildcard bins instr_cvpack = {INSTR_CVPACK}; \ - wildcard bins instr_cvpackh = {INSTR_CVPACKH}; \ - wildcard bins instr_cvpackhib = {INSTR_CVPACKHIB}; \ - wildcard bins instr_cvpacklob = {INSTR_CVPACKLOB}; \ - // SIMD COMPARISON \ - wildcard bins instr_cvcmpeqh = {INSTR_CVCMPEQH}; \ - wildcard bins instr_cvcmpeqsch = {INSTR_CVCMPEQSCH}; \ - wildcard bins instr_cvcmpeqscih = {INSTR_CVCMPEQSCIH}; \ - wildcard bins instr_cvcmpeqb = {INSTR_CVCMPEQB}; \ - wildcard bins instr_cvcmpeqscb = {INSTR_CVCMPEQSCB}; \ - wildcard bins instr_cvcmpeqscib = {INSTR_CVCMPEQSCIB}; \ - wildcard bins instr_cvcmpneh = {INSTR_CVCMPNEH}; \ - wildcard bins instr_cvcmpnesch = {INSTR_CVCMPNESCH}; \ - wildcard bins instr_cvcmpnescih = {INSTR_CVCMPNESCIH}; \ - wildcard bins instr_cvcmpneb = {INSTR_CVCMPNEB}; \ - wildcard bins instr_cvcmpnescb = {INSTR_CVCMPNESCB}; \ - wildcard bins instr_cvcmpnescib = {INSTR_CVCMPNESCIB}; \ - wildcard bins instr_cvcmpgth = {INSTR_CVCMPGTH}; \ - wildcard bins instr_cvcmpgtsch = {INSTR_CVCMPGTSCH}; \ - wildcard bins instr_cvcmpgtscih = {INSTR_CVCMPGTSCIH}; \ - wildcard bins instr_cvcmpgtb = {INSTR_CVCMPGTB}; \ - wildcard bins instr_cvcmpgtscb = {INSTR_CVCMPGTSCB}; \ - wildcard bins instr_cvcmpgtscib = {INSTR_CVCMPGTSCIB}; \ - wildcard bins instr_cvcmpgeh = {INSTR_CVCMPGEH}; \ - wildcard bins instr_cvcmpgesch = {INSTR_CVCMPGESCH}; \ - wildcard bins instr_cvcmpgescih = {INSTR_CVCMPGESCIH}; \ - wildcard bins instr_cvcmpgeb = {INSTR_CVCMPGEB}; \ - wildcard bins instr_cvcmpgescb = {INSTR_CVCMPGESCB}; \ - wildcard bins instr_cvcmpgescib = {INSTR_CVCMPGESCIB}; \ - wildcard bins instr_cvcmplth = {INSTR_CVCMPLTH}; \ - wildcard bins instr_cvcmpltsch = {INSTR_CVCMPLTSCH}; \ - wildcard bins instr_cvcmpltscih = {INSTR_CVCMPLTSCIH}; \ - wildcard bins instr_cvcmpltb = {INSTR_CVCMPLTB}; \ - wildcard bins instr_cvcmpltscb = {INSTR_CVCMPLTSCB}; \ - wildcard bins instr_cvcmpltscib = {INSTR_CVCMPLTSCIB}; \ - wildcard bins instr_cvcmpleh = {INSTR_CVCMPLEH}; \ - wildcard bins instr_cvcmplesch = {INSTR_CVCMPLESCH}; \ - wildcard bins instr_cvcmplescih = {INSTR_CVCMPLESCIH}; \ - wildcard bins instr_cvcmpleb = {INSTR_CVCMPLEB}; \ - wildcard bins instr_cvcmplescb = {INSTR_CVCMPLESCB}; \ - wildcard bins instr_cvcmplescib = {INSTR_CVCMPLESCIB}; \ - wildcard bins instr_cvcmpgtuh = {INSTR_CVCMPGTUH}; \ - wildcard bins instr_cvcmpgtusch = {INSTR_CVCMPGTUSCH}; \ - wildcard bins instr_cvcmpgtuscih = {INSTR_CVCMPGTUSCIH}; \ - wildcard bins instr_cvcmpgtub = {INSTR_CVCMPGTUB}; \ - wildcard bins instr_cvcmpgtuscb = {INSTR_CVCMPGTUSCB}; \ - wildcard bins instr_cvcmpgtuscib = {INSTR_CVCMPGTUSCIB}; \ - wildcard bins instr_cvcmpgeuh = {INSTR_CVCMPGEUH}; \ - wildcard bins instr_cvcmpgeusch = {INSTR_CVCMPGEUSCH}; \ - wildcard bins instr_cvcmpgeuscih = {INSTR_CVCMPGEUSCIH}; \ - wildcard bins instr_cvcmpgeub = {INSTR_CVCMPGEUB}; \ - wildcard bins instr_cvcmpgeuscb = {INSTR_CVCMPGEUSCB}; \ - wildcard bins instr_cvcmpgeuscib = {INSTR_CVCMPGEUSCIB}; \ - wildcard bins instr_cvcmpltuh = {INSTR_CVCMPLTUH}; \ - wildcard bins instr_cvcmpltusch = {INSTR_CVCMPLTUSCH}; \ - wildcard bins instr_cvcmpltuscih = {INSTR_CVCMPLTUSCIH}; \ - wildcard bins instr_cvcmpltub = {INSTR_CVCMPLTUB}; \ - wildcard bins instr_cvcmpltuscb = {INSTR_CVCMPLTUSCB}; \ - wildcard bins instr_cvcmpltuscib = {INSTR_CVCMPLTUSCIB}; \ - wildcard bins instr_cvcmpleuh = {INSTR_CVCMPLEUH}; \ - wildcard bins instr_cvcmpleusch = {INSTR_CVCMPLEUSCH}; \ - wildcard bins instr_cvcmpleuscih = {INSTR_CVCMPLEUSCIH}; \ - wildcard bins instr_cvcmpleub = {INSTR_CVCMPLEUB}; \ - wildcard bins instr_cvcmpleuscb = {INSTR_CVCMPLEUSCB}; \ - wildcard bins instr_cvcmpleuscib = {INSTR_CVCMPLEUSCIB}; \ - // SIMD CPLX \ - wildcard bins instr_cvcplxmulr = {INSTR_CVCPLXMULR}; \ - wildcard bins instr_cvcplxmulrdiv2 = {INSTR_CVCPLXMULRDIV2}; \ - wildcard bins instr_cvcplxmulrdiv4 = {INSTR_CVCPLXMULRDIV4}; \ - wildcard bins instr_cvcplxmulrdiv8 = {INSTR_CVCPLXMULRDIV8}; \ - wildcard bins instr_cvcplxmuli = {INSTR_CVCPLXMULI}; \ - wildcard bins instr_cvcplxmulidiv2 = {INSTR_CVCPLXMULIDIV2}; \ - wildcard bins instr_cvcplxmulidiv4 = {INSTR_CVCPLXMULIDIV4}; \ - wildcard bins instr_cvcplxmulidiv8 = {INSTR_CVCPLXMULIDIV8}; \ - wildcard bins instr_cvcplxconj = {INSTR_CVCPLXCONJ}; \ - wildcard bins instr_cvsubrotmj = {INSTR_CVSUBROTMJ}; \ - wildcard bins instr_cvsubrotmjdiv2 = {INSTR_CVSUBROTMJDIV2}; \ - wildcard bins instr_cvsubrotmjdiv4 = {INSTR_CVSUBROTMJDIV4}; \ - wildcard bins instr_cvsubrotmjdiv8 = {INSTR_CVSUBROTMJDIV8}; \ - wildcard bins instr_cvaddiv2 = {INSTR_CVADDIV2}; \ - wildcard bins instr_cvaddiv4 = {INSTR_CVADDIV4}; \ - wildcard bins instr_cvaddiv8 = {INSTR_CVADDIV8}; \ - wildcard bins instr_cvsubiv2 = {INSTR_CVSUBIV2}; \ - wildcard bins instr_cvsubiv4 = {INSTR_CVSUBIV4}; \ - wildcard bins instr_cvsubiv8 = {INSTR_CVSUBIV8}; \ - // Load-Store (RV32F) \ - wildcard bins instr_flw = {INSTR_FLW}; \ - wildcard bins instr_fsw = {INSTR_FSW}; \ + `LOAD_STORE_INSTR_BINS \ + // RV32X \ + `RV32X_PULP_INSTR_BINS \ // user-defined instructions \ wildcard bins instr_illegal_exception = {{INSN_ILLEGAL}}; \ - wildcard bins instr_ebreakm = {{INSN_EBREAKM}}; \ + wildcard bins instr_ebreakm = {{INSN_EBREAKM}}; \ // Others \ - illegal_bins other_instr = default; \ + illegal_bins other_instr = default; \ } \ - ccp_hwloop_type_setup_insn_list : cross cp_hwloop_type, cp_hwloop_setup, cp_insn_list_in_hwloop; \ - ccp_hwloop_type_irq : cross cp_hwloop_type, cp_hwloop_irq; \ - ccp_hwloop_type_dbg_mode : cross cp_hwloop_type, cp_hwloop_dbg_haltreq; \ - ccp_hwloop_type_dbg_trigger : cross cp_hwloop_type, cp_hwloop_dbg_trigger; \ - ccp_hwloop_type_dbg_step_cnt : cross cp_hwloop_type, cp_hwloop_dbg_step_cnt { \ - bins ccp_single_dbg_step_range_1 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_1) && binsof (cp_hwloop_type.single_hwloop); \ - bins ccp_single_dbg_step_range_2 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_2) && binsof (cp_hwloop_type.single_hwloop); \ - bins ccp_single_dbg_step_range_3 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_3) && binsof (cp_hwloop_type.single_hwloop); \ - bins ccp_single_dbg_step_range_4 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_4) && binsof (cp_hwloop_type.single_hwloop); \ - bins ccp_nested_dbg_step_range_1 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_1) && binsof (cp_hwloop_type.nested_hwloop); \ - bins ccp_nested_dbg_step_range_2 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_2) && binsof (cp_hwloop_type.nested_hwloop); \ - bins ccp_nested_dbg_step_range_3 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_3) && binsof (cp_hwloop_type.nested_hwloop); \ - bins ccp_nested_dbg_step_range_4 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_4) && binsof (cp_hwloop_type.nested_hwloop); \ - } /* todo: x with lpcount */ \ + ccp_hwloop_type_setup_insn_list : cross cp_hwloop_type, cp_hwloop_setup, cp_insn_list_in_hwloop; \ + ccp_hwloop_type_irq_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_irq; \ + ccp_hwloop_type_dbg_haltreq_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_dbg_haltreq; \ + ccp_hwloop_type_dbg_ebreakm_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_dbg_ebreakm; \ + ccp_hwloop_type_dbg_trigger_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_dbg_trigger; \ + ccp_hwloop_type_dbg_step_cnt : cross cp_hwloop_type, cp_hwloop_dbg_step_cnt; /* todo: x with lpcount */ \ + ccp_hwloop_type_dbg_step_cnt_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_dbg_step_cnt_loc; \ + ccp_hwloop_type_excp_ebreak_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_excp_ebreak; \ + ccp_hwloop_type_excp_ecall_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_excp_ecall; \ + ccp_hwloop_type_excp_illegal_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_excp_illegal; \ + ccp_hwloop_type_excp_mc_insn_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_mc_insn; \ endgroup : cg_features_of_hwloop_``LOOP_IDX`` `DEF_CG_CSR_HWLOOP(0) @@ -644,6 +314,91 @@ class uvme_rv32x_hwloop_covg # ( end endfunction : build_phase + + // conditions to collect location for different locations + `define CHECK_PC_EQUAL_LPSTART(IN1, IN2, IN3, IN4) is_pc_equal_lpstart(``IN1, ``IN2, ``IN3, ``IN4) + `define CHECK_PC_EQUAL_LPEND(IN1, IN2, IN3, IN4) is_pc_equal_lpend(``IN1, ``IN2, ``IN3, ``IN4) + `define CHECK_PC_WITHIN_LP(IN1, IN2, IN3) is_pc_within_lp(``IN1, ``IN2, ``IN3) + `define IF_CURRENT_IS_MAIN_HWLOOP(LOOP_IDX, EVT) \ + if (``LOOP_IDX`` == 0 || ``LOOP_IDX`` == 1) begin \ + bit temp_in_nested_loop0 = (``LOOP_IDX`` == 0) ? 0 : in_nested_loop0; \ + if (hwloop_stat_main.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_stat_main.track_lp_cnt[``LOOP_IDX``] >= 0 && !temp_in_nested_loop0) begin \ + unique case (``EVT``) \ + EXCP_EBREAK: begin \ + hwloop_stat_main.excp_ebreak_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_OTHERS); \ + end \ + EXCP_ECALL : begin \ + hwloop_stat_main.excp_ecall_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_OTHERS); \ + end \ + EXCP_ILLEGAL : begin \ + hwloop_stat_main.excp_illegal_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_OTHERS); \ + end \ + IS_IRQ : begin \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_OTHERS); \ + irq_vect_main[``LOOP_IDX``].push_back(prev_irq_onehot_priority); \ + end \ + DBG_HALTREQ : begin \ + hwloop_stat_main.dbg_haltreq_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_OTHERS); \ + end \ + DBG_TRIG : begin \ + hwloop_stat_main.dbg_trigger_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_OTHERS); \ + end \ + DBG_STEP : begin \ + hwloop_stat_main.dbg_step_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_OTHERS); \ + end \ + DBG_EBREAKM : begin \ + hwloop_stat_main.dbg_ebreakm_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_OTHERS); \ + end \ + MC_INSN : begin \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_OTHERS); \ + end \ + endcase \ + end \ + end + // task to sample cg_csr_hwloop `define CHECK_N_SAMPLE_CSR_HWLOOP(TYPE) check_n_sample_csr_hwloop_``TYPE``(); `define DEF_CHECK_N_SAMPLE_CSR_HWLOOP(TYPE) task check_n_sample_csr_hwloop_``TYPE``(); \ @@ -697,16 +452,17 @@ class uvme_rv32x_hwloop_covg # ( endtask : check_n_sample_csr_hwloop_``TYPE`` `DEF_CHECK_N_SAMPLE_CSR_HWLOOP(main) - `DEF_CHECK_N_SAMPLE_CSR_HWLOOP(sub) + // `DEF_CHECK_N_SAMPLE_CSR_HWLOOP(sub) // task to sample cg_features_of_hwloop + `define MC_INSN_OP_CODE {OPCODE_OP, OPCODE_OP_FP, OPCODE_OP_FMADD, OPCODE_OP_FNMADD, OPCODE_OP_FMSUB, OPCODE_OP_FNMSUB, OPCODE_LOAD_FP, OPCODE_STORE_FP} `define CHECK_N_SAMPLE_HWLOOP(TYPE) check_n_sample_hwloop_``TYPE``(); `define DEF_CHECK_N_SAMPLE_HWLOOP(TYPE) task check_n_sample_hwloop_``TYPE``(); \ for (int i=0; i= 0); \ + assert(hwloop_stat_``TYPE``.track_lp_cnt[i] >= 0); \ end \ end \ 1 : begin // in nested, skip when executing hwloop0 \ - if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_count[0] != 0) begin \ + in_nested_loop0_d1 = in_nested_loop0; \ + if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_cnt[0] != 0) begin \ in_nested_loop0 = 1; continue; \ end \ - else if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_count[0] == 0 && in_nested_loop0) begin \ + else if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_cnt[0] == 0 && in_nested_loop0) begin \ in_nested_loop0 = 0; continue; \ end \ if (!done_insn_list_capture_``TYPE``[i]) begin \ if (is_illegal) insn_list_in_hwloop_``TYPE``[i].push_back(INSN_ILLEGAL); \ else if (is_ebreakm) insn_list_in_hwloop_``TYPE``[i].push_back(INSN_EBREAKM); \ else insn_list_in_hwloop_``TYPE``[i].push_back(cv32e40p_rvvi_vif.insn); \ + if (cv32e40p_rvvi_vif.insn[6:0] inside `MC_INSN_OP_CODE) begin \ + if ((cv32e40p_rvvi_vif.insn[6:0] == OPCODE_OP && cv32e40p_rvvi_vif.insn[31:25] != 7'b0000001) || \ + (cv32e40p_rvvi_vif.insn[6:0] == OPCODE_OP && cv32e40p_rvvi_vif.insn[14:12] == 3'b000) \ + ) is_mc_insn = 0; \ + else begin \ + is_mc_insn = 1; mc_insn_list_in_hwloop_``TYPE``[i].push_back(cv32e40p_rvvi_vif.insn); \ + `IF_CURRENT_IS_MAIN_HWLOOP(i, MC_INSN) \ + end \ + end \ + else is_mc_insn = 0; \ + check_ebreakm_entry(i); \ end \ else if (is_ebreakm) begin \ insn_list_in_hwloop_``TYPE``[i].push_back(INSN_EBREAKM); \ + check_ebreakm_entry(i); \ end \ - if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i) && hwloop_stat_``TYPE``.track_lp_count[i] != 0) begin \ - hwloop_stat_``TYPE``.track_lp_count[i]--; \ + if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i, 0, cv32e40p_rvvi_vif.pc_rdata) && hwloop_stat_``TYPE``.track_lp_cnt[i] != 0) begin \ + if (pending_irq) lpend_has_pending_irq_``TYPE``[i] = 1; \ + hwloop_stat_``TYPE``.track_lp_cnt[i]--; \ done_insn_list_capture_``TYPE``[i] = 1; \ - assert(hwloop_stat_``TYPE``.track_lp_count[i] >= 0); \ + assert(hwloop_stat_``TYPE``.track_lp_cnt[i] >= 0); \ end \ end \ endcase \ end \ end // COLLECT_INSTR \ if ( \ - (hwloop_stat_``TYPE``.hwloop_type == NESTED && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_count[1] == 0) || \ - (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_count[1] == 0) || \ - (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[0] && hwloop_stat_``TYPE``.track_lp_count[0] == 0) \ + (hwloop_stat_``TYPE``.hwloop_type == NESTED && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_cnt[1] == 0) || \ + (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_cnt[1] == 0) || \ + (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[0] && hwloop_stat_``TYPE``.track_lp_cnt[0] == 0) \ ) begin : SAMPLE_END_OF_HWLOOPS \ for (int i=0; i 0) begin \ + `uvm_info(_header, $sformatf("DEBUG - FOR_CP_HWLOOP_DBG_STEP_CNT - LOOP_%0d - dbg_step_cnt %0d", i, hwloop_stat_``TYPE``.dbg_step_cnt[i]), UVM_DEBUG); \ + unique case (i) \ + 0: begin \ + `CG_FEATURES_OF_HWLOOP(0).sample(.lp_idx(i), .hwloop_stat(hwloop_stat_``TYPE``), .hwloop_cov(hwloop_cov_``TYPE``[i])); \ + end \ + 1: begin \ + `CG_FEATURES_OF_HWLOOP(1).sample(.lp_idx(i), .hwloop_stat(hwloop_stat_``TYPE``), .hwloop_cov(hwloop_cov_``TYPE``[i])); \ + end \ + endcase \ + end \ + hwloop_cov_``TYPE``[i].en_cov_dbg_step_cnt = 0; \ + // FOR_CP_HWLOOP_DBG_STEP_CNT_LOC \ + hwloop_cov_``TYPE``[i].en_cov_dbg_step_cnt_loc = 1; hwloop_cov_``TYPE``[i].en_cov_event_loc = 1; \ + for (int j=0; j= cv32e40p_rvvi_vif.mtvec_base_addr && cv32e40p_rvvi_vif.pc_rdata < (cv32e40p_rvvi_vif.mtvec_base_addr + 32*4)) return 1; // direct or vector mode + else return 0; + endfunction : pc_is_mtvec_addr + + function bit is_mcause_irq(); + return cv32e40p_rvvi_vif.csr_mcause_irq; + endfunction : is_mcause_irq task run_phase(uvm_phase phase); super.run_phase(phase); fork // Background threads - START - forever begin : EXCEPTION_HANDLING - wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.trap && exception_code_t'(cv32e40p_rvvi_vif.csr_mcause_ecp_code) inside {CODE_ILLEGAL, CODE_EBREAK, CODE_ECALL}); - exception_code = exception_code_t'(cv32e40p_rvvi_vif.csr_mcause_ecp_code); - case (cv32e40p_rvvi_vif.insn) - INSTR_EBREAK, INSN_CEBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin @(posedge cv32e40p_rvvi_vif.clk); continue; end else is_ebreak = 1; - INSTR_ECALL : is_ecall = 1; - default : is_illegal = 1; - endcase - `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to %s", exception_code.name()), UVM_DEBUG); - wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == INSTR_MRET); - is_ebreak = 0; is_ecall = 0; is_illegal = 0; - `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Exit"), UVM_DEBUG); + + forever begin : SET_EXCEPTION_FLAG + wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.trap); + if ( + cv32e40p_rvvi_vif.pc_rdata == prev_pc_rdata_main || // set excep when not garbage data during trap (main) + cv32e40p_rvvi_vif.pc_rdata == prev_pc_rdata_sub // set excep when not garbage data during trap (sub) - todo: revise is needed when sub is fully implement + ) begin + is_trap = 0; + wait (!cv32e40p_rvvi_vif.trap); // bypass if garbage data exist + end + else if ( + ((cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0) || prev_irq_onehot_priority_is_0 || cv32e40p_rvvi_vif.csr_dcsr_step) && + !pending_irq && !is_dbg_mode && !is_irq) begin // set excep flag only if no pending irq and not in dbg mode + is_trap = 1; + case (cv32e40p_rvvi_vif.insn) + TB_INSTR_EBREAK, INSTR_CBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin + @(posedge cv32e40p_rvvi_vif.clk); continue; + end + else begin is_ebreak = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to EBREAK"), UVM_DEBUG); end + TB_INSTR_ECALL : begin is_ecall = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to ECALL"), UVM_DEBUG); end + default : begin is_illegal = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to ILLEGAL"), UVM_DEBUG); end + endcase + wait (!(is_ebreak | is_ecall | is_illegal)); + end + else begin + is_trap = 0; + wait (!cv32e40p_rvvi_vif.trap); + end // bypass if pending irq exist end // EXCEPTION_HANDLING - forever begin : IRQ_ENTRY - wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1] | hwloop_stat_sub.execute_instr_in_hwloop[0] | hwloop_stat_sub.execute_instr_in_hwloop[1]); - wait (cv32e40p_rvvi_vif.irq_onehot_priority != 0 && !is_irq); - if (hwloop_stat_main.execute_instr_in_hwloop[0] && hwloop_stat_main.track_lp_count[0] !=0) irq_vect_main[0].push_back(cv32e40p_rvvi_vif.irq_onehot_priority); - if (hwloop_stat_main.execute_instr_in_hwloop[1] && hwloop_stat_main.track_lp_count[1] !=0 && !in_nested_loop0) irq_vect_main[1].push_back(cv32e40p_rvvi_vif.irq_onehot_priority); - if (hwloop_stat_sub.execute_instr_in_hwloop[0] && hwloop_stat_sub.track_lp_count[0] !=0) irq_vect_sub[0].push_back(cv32e40p_rvvi_vif.irq_onehot_priority); - if (hwloop_stat_sub.execute_instr_in_hwloop[1] && hwloop_stat_sub.track_lp_count[1] !=0 && !in_nested_loop0) irq_vect_sub[1].push_back(cv32e40p_rvvi_vif.irq_onehot_priority); - `uvm_info(_header, $sformatf("DEBUG - IRQ Entry"), UVM_DEBUG); - is_irq = 1; - end // IRQ_ENTRY + + forever begin : SET_PENDING_IRQ_FLAG + @(negedge cv32e40p_rvvi_vif.clk); + if (cv32e40p_rvvi_vif.irq_onehot_priority !== prev_irq_onehot_priority) begin + pending_irq = 0; + prev_irq_onehot_priority_is_0 = 0; + if (enter_hwloop_sub) update_prev_irq_onehot_priority(); // within excp period + else if ((hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1])) begin // within main loop + if (prev_irq_onehot_priority === 0) begin prev_irq_onehot_priority_is_0 = 1; update_prev_irq_onehot_priority(); end // new pending + else begin // last irq or any pending irq(s) + if (!is_irq) pending_irq = 1; + else begin + repeat(2) @(negedge cv32e40p_rvvi_vif.clk); + if (!is_irq) pending_irq = 1; + else update_prev_irq_onehot_priority(); + end + end + end + else begin update_prev_irq_onehot_priority(); end // outside hwloop period + end + end // SET_PENDING_IRQ_FLAG forever begin : IRQ_EXIT - wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1] | hwloop_stat_sub.execute_instr_in_hwloop[0] | hwloop_stat_sub.execute_instr_in_hwloop[1]); + wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]); @(posedge cv32e40p_rvvi_vif.clk); - if (is_irq && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == INSTR_MRET) begin + if (is_irq && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == TB_INSTR_MRET) begin `uvm_info(_header, $sformatf("DEBUG - IRQ Exit"), UVM_DEBUG); is_irq = 0; end end // IRQ_EXIT + forever begin : SIGNALS_CHG_WHEN_IS_IRQ_ASSERT + @(posedge is_irq); + if (is_ebreakm) begin + for (int j=0; j= 0 && !temp_in_nested_loop0) begin + // todo logic [31:0] discarded_insn; + // todo if (!done_insn_list_capture_main[j]) begin + // todo discarded_insn = insn_list_in_hwloop_main[j].pop_back(); + // todo `uvm_info(_header, $sformatf("DEBUG - HWLOOP_NB_%0d Discarded insn %8h due to Trap triggered by Debug Entery", j, discarded_insn), UVM_DEBUG); + // todo assert (discarded_insn inside {TB_INSTR_ECALL, TB_INSTR_EBREAK, INSN_ILLEGAL}); + // todo end + // todo `uvm_info(_header, $sformatf("DEBUG - HWLOOP_NB_%0d Trap due to Debug Entry detected", j), UVM_DEBUG); + // todo end + // todo end + end // TRAP_DUETO_DBG_ENTRY + else if (pc_is_mtvec_addr() && !is_mcause_irq()) begin : EXCEPTION_ENTRY + for (int i=0; idbg); currently commented out due to pending for implementation // `CHECK_N_SAMPLE_CSR_HWLOOP(sub); // `CHECK_N_SAMPLE_HWLOOP(sub); - if (!(is_ebreak || is_ecall || is_illegal)) enter_hwloop_sub = 0; + // [optional] todo: mie has effect on irq during exception. Current hwloop tests do not exercise nested irq with mie enabled + + check_exception_exit(); + if (!(is_ebreak || is_ecall || is_illegal || has_pending_trap_due2_dbg)) begin enter_hwloop_sub = 0; enter_hwloop_sub_cnt = 0; end + prev_pc_rdata_sub = cv32e40p_rvvi_vif.pc_rdata; end + else begin : MAIN - if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == INSTR_EBREAK) is_ebreakm = 1; - if (is_irq && cv32e40p_rvvi_vif.insn[6:0] == OPCODE_JAL) begin wait (!is_irq); continue; end - if (is_dbg_mode) begin wait (!is_dbg_mode); continue; end + if (pc_is_mtvec_addr() && is_mcause_irq()) begin : IRQ_ENTRY + if (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]) begin + pending_irq = 0; + `IF_CURRENT_IS_MAIN_HWLOOP(0, IS_IRQ) + `IF_CURRENT_IS_MAIN_HWLOOP(1, IS_IRQ) + update_prev_irq_onehot_priority(); + `uvm_info(_header, $sformatf("DEBUG - IRQ Entry"), UVM_DEBUG); + is_irq = 1; wait (!is_irq); continue; + end + end // IRQ_ENTRY + if (is_dbg_mode) begin wait (!is_dbg_mode); continue; end + if (has_pending_trap_due2_dbg) begin + assert(!cv32e40p_rvvi_vif.csr_dcsr_step); // this is not mean for step debug + if (pc_is_mtvec_addr() || cv32e40p_rvvi_vif.trap) begin enter_hwloop_sub = 1; has_pending_trap_due2_dbg = 0; continue; end + else begin is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; has_pending_trap_due2_dbg = 0; continue; end + end + if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == TB_INSTR_EBREAK) is_ebreakm = 1; else is_ebreakm = 0; `CHECK_N_SAMPLE_CSR_HWLOOP(main); `CHECK_N_SAMPLE_HWLOOP(main); if (is_ebreak || is_ecall || is_illegal) enter_hwloop_sub = 1; + prev_pc_rdata_main = cv32e40p_rvvi_vif.pc_rdata; end + end // VALID_DETECTED end // forever @@ -901,26 +1011,26 @@ class uvme_rv32x_hwloop_covg # ( function void final_phase(uvm_phase phase); super.final_phase(phase); - if (hwloop_stat_main == hwloop_stat_init && hwloop_stat_sub == hwloop_stat_init) begin + if (hwloop_stat_main == hwloop_stat_init) begin `uvm_info(_header, $sformatf("DEBUG - No prematured hwloops when test done"), UVM_DEBUG); end else begin - `uvm_error(_header, $sformatf("Detected prematured hwloops when test done. Please debug ... ")); + `uvm_error(_header, $sformatf("Detected prematured hwloops when test done. Please debug ... ")); // fixme: to be commented out end endfunction : final_phase - function bit is_pc_equal_lpstart(s_csr_hwloop csr_hwloop, int idx=0); - if (cv32e40p_rvvi_vif.pc_rdata == csr_hwloop.lp_start[idx]) return 1; + function bit is_pc_equal_lpstart(s_csr_hwloop csr_hwloop, int csr_idx=0, int fwd_offset=0, logic [31:0] pc_rdata); + if (pc_rdata == csr_hwloop.lp_start[csr_idx]+(fwd_offset*4)) return 1; else return 0; endfunction: is_pc_equal_lpstart - function bit is_pc_equal_lpend(s_csr_hwloop csr_hwloop, int idx=0); - if (cv32e40p_rvvi_vif.pc_rdata == csr_hwloop.lp_end[idx]-4) return 1; + function bit is_pc_equal_lpend(s_csr_hwloop csr_hwloop, int csr_idx=0, int rvs_offset=0, logic [31:0] pc_rdata); + if (pc_rdata == csr_hwloop.lp_end[csr_idx]-4-(rvs_offset*4)) return 1; else return 0; endfunction: is_pc_equal_lpend - function bit is_pc_within_lp(s_csr_hwloop csr_hwloop, int idx=0); - if (cv32e40p_rvvi_vif.pc_rdata >= csr_hwloop.lp_start[idx] && cv32e40p_rvvi_vif.pc_rdata <= csr_hwloop.lp_end[idx]-4) return 1; + function bit is_pc_within_lp(s_csr_hwloop csr_hwloop, int csr_idx=0, logic [31:0] pc_rdata); + if (pc_rdata >= csr_hwloop.lp_start[csr_idx] && cv32e40p_rvvi_vif.pc_rdata <= csr_hwloop.lp_end[csr_idx]-4) return 1; else return 0; endfunction : is_pc_within_lp diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv index 01cdaafe8d..5edb260838 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv @@ -68,6 +68,12 @@ class uvme_cv32e40p_cfg_c extends uvma_core_cntrl_cfg_c; bit max_rand_instr_latency; // variable set by plusarg +max_rand_instr_latency=<> int max_rand_instr_latency_limit; + rand int rv32f_fcov_en; + rand int zfinx_fcov_en; + rand int fpu_latency_addmul; + rand int fpu_latency_others; + rand int fpu_latency; + // Agent cfg handles rand uvma_clknrst_cfg_c clknrst_cfg; rand uvma_interrupt_cfg_c interrupt_cfg; @@ -89,6 +95,9 @@ class uvme_cv32e40p_cfg_c extends uvma_core_cntrl_cfg_c; `uvm_field_int ( trn_log_enabled , UVM_DEFAULT ) `uvm_field_int ( sys_clk_period , UVM_DEFAULT + UVM_DEC) //`uvm_field_int ( debug_clk_period , UVM_DEFAULT + UVM_DEC) + `uvm_field_int ( rv32f_fcov_en, UVM_DEFAULT ) + `uvm_field_int ( zfinx_fcov_en, UVM_DEFAULT ) + `uvm_field_int ( fpu_latency, UVM_DEFAULT ) `uvm_field_object(clknrst_cfg , UVM_DEFAULT) `uvm_field_object(interrupt_cfg , UVM_DEFAULT) @@ -110,6 +119,11 @@ class uvme_cv32e40p_cfg_c extends uvma_core_cntrl_cfg_c; soft trn_log_enabled == 1; soft sys_clk_period == uvme_cv32e40p_sys_default_clk_period; // see uvme_cv32e40p_constants.sv //soft debug_clk_period == uvme_cv32e40p_debug_default_clk_period; + soft rv32f_fcov_en == 0; + soft zfinx_fcov_en == 0; + soft fpu_latency_addmul == FPU_ADDMUL_LAT_DV; + soft fpu_latency_others == FPU_OTHERS_LAT_DV; + soft fpu_latency == FPU_ADDMUL_LAT_DV; } constraint zero_stall_sim_dist_cons { @@ -523,6 +537,18 @@ function void uvme_cv32e40p_cfg_c::post_randomize(); // Disable some CSR checks from all tests configure_disable_csr_checks(); + if(fpu_latency_addmul != fpu_latency_others) begin + `uvm_fatal("uvme_cv32e40p_cfg_c", "FPU Latency Parameter not equal, fpu_latency config value cant be used"); + end + + if (cov_model_enabled && (RV32ZFINX inside {uvme_cv32e40p_pkg::cv32e40p_core_isa_list})) begin + zfinx_fcov_en = 1; + rv32f_fcov_en = 0; + end else if (cov_model_enabled && (RV32F inside {uvme_cv32e40p_pkg::cv32e40p_core_isa_list})) begin + rv32f_fcov_en = 1; + zfinx_fcov_en = 0; + end + endfunction : post_randomize function void uvme_cv32e40p_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cntxt); diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_cntxt.sv b/cv32e40p/env/uvme/uvme_cv32e40p_cntxt.sv index 1902c853da..c953b3a886 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_cntxt.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_cntxt.sv @@ -30,6 +30,7 @@ class uvme_cv32e40p_cntxt_c extends uvm_object; virtual uvmt_cv32e40p_vp_status_if vp_status_vif; ///< Virtual interface for Virtual Peripherals virtual uvma_interrupt_if intr_vif ; ///< Virtual interface for interrupts virtual uvma_debug_if debug_vif ; ///< Virtual interface for debug + virtual uvmt_cv32e40p_cov_if cov_vif ; ///< Virtual interface for custom coverage // Agent context handles uvma_cv32e40p_core_cntrl_cntxt_c core_cntrl_cntxt; diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv b/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv index 3041699ce4..46e9c51950 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv @@ -55,6 +55,124 @@ parameter CV_VP_OBI_SLV_RESP_BASE = CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RES parameter CV_VP_SIG_WRITER_BASE = CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET; parameter CV_VP_FENCEI_TAMPER_BASE = CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET; +parameter TB_OPCODE_SYSTEM = 7'h73; +parameter TB_OPCODE_FENCE = 7'h0f; +parameter TB_OPCODE_OP = 7'h33; +parameter TB_OPCODE_OPIMM = 7'h13; +parameter TB_OPCODE_STORE = 7'h23; +parameter TB_OPCODE_LOAD = 7'h03; +parameter TB_OPCODE_BRANCH = 7'h63; +parameter TB_OPCODE_JALR = 7'h67; +parameter TB_OPCODE_JAL = 7'h6f; +parameter TB_OPCODE_AUIPC = 7'h17; +parameter TB_OPCODE_LUI = 7'h37; +parameter TB_OPCODE_AMO = 7'h2F; + +parameter TB_OPCODE_OP_FP = 7'h53; +parameter TB_OPCODE_OP_FMADD = 7'h43; +parameter TB_OPCODE_OP_FNMADD = 7'h4f; +parameter TB_OPCODE_OP_FMSUB = 7'h47; +parameter TB_OPCODE_OP_FNMSUB = 7'h4b; +parameter TB_OPCODE_STORE_FP = 7'h27; +parameter TB_OPCODE_LOAD_FP = 7'h07; + +// RV32F +parameter TB_INS_FMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FMADD}; +parameter TB_INS_FMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FMSUB}; +parameter TB_INS_FNMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FNMSUB}; +parameter TB_INS_FNMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FNMADD}; +parameter TB_INS_FADD = {5'b00000, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSUB = {5'b00001, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMUL = {5'b00010, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FDIV = {5'b00011, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSQRT = {5'b01011, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSGNJS = {5'b00100, 2'b00, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSGNJNS = {5'b00100, 2'b00, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSGNJXS = {5'b00100, 2'b00, 10'b?, 3'b010, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMIN = {5'b00101, 2'b00, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMAX = {5'b00101, 2'b00, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCVTWS = {5'b11000, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCVTWUS = {5'b11000, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMVXS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FEQS = {5'b10100, 2'b00, 10'b?, 3'b010, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FLTS = {5'b10100, 2'b00, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FLES = {5'b10100, 2'b00, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCLASS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b001, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCVTSW = {5'b11010, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCVTSWU = {5'b11010, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMVSX = {5'b11110, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FLW = {12'b?,5'b?,3'b010,5'b?,TB_OPCODE_LOAD_FP}; +parameter TB_INS_FSW = {7'b?,5'b?,5'b?,3'b010,5'b?,TB_OPCODE_STORE_FP}; + + +parameter TB_INSTR_LUI = {25'b?, TB_OPCODE_LUI}; +parameter TB_INSTR_AUIPC = {25'b?, TB_OPCODE_AUIPC}; +parameter TB_INSTR_JAL = {25'b?, TB_OPCODE_JAL}; +parameter TB_INSTR_JALR = {17'b?, 3'b000, 5'b?, TB_OPCODE_JALR}; +// BRANCH +parameter TB_INSTR_BEQ = {17'b?, 3'b000, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BNE = {17'b?, 3'b001, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BLT = {17'b?, 3'b100, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BGE = {17'b?, 3'b101, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BLTU = {17'b?, 3'b110, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BGEU = {17'b?, 3'b111, 5'b?, TB_OPCODE_BRANCH}; +// OPIMM +parameter TB_INSTR_ADDI = {17'b?, 3'b000, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SLTI = {17'b?, 3'b010, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SLTIU = {17'b?, 3'b011, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_XORI = {17'b?, 3'b100, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_ORI = {17'b?, 3'b110, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_ANDI = {17'b?, 3'b111, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SLLI = {7'b0000000, 10'b?, 3'b001, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SRLI = {7'b0000000, 10'b?, 3'b101, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SRAI = {7'b0100000, 10'b?, 3'b101, 5'b?, TB_OPCODE_OPIMM}; +// OP +parameter TB_INSTR_ADD = {7'b0000000, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SUB = {7'b0100000, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SLL = {7'b0000000, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SLT = {7'b0000000, 10'b?, 3'b010, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SLTU = {7'b0000000, 10'b?, 3'b011, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_XOR = {7'b0000000, 10'b?, 3'b100, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SRL = {7'b0000000, 10'b?, 3'b101, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SRA = {7'b0100000, 10'b?, 3'b101, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_OR = {7'b0000000, 10'b?, 3'b110, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_AND = {7'b0000000, 10'b?, 3'b111, 5'b?, TB_OPCODE_OP}; +// FENCE +parameter TB_INSTR_FENCE = {4'b0, 8'b?, 13'b0, TB_OPCODE_FENCE}; +parameter TB_INSTR_FENCEI = {17'b0, 3'b001, 5'b0, TB_OPCODE_FENCE}; +// SYSTEM +parameter TB_INSTR_CSRRW = {17'b?, 3'b001, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRS = {17'b?, 3'b010, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRC = {17'b?, 3'b011, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRWI = {17'b?, 3'b101, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRSI = {17'b?, 3'b110, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRCI = {17'b?, 3'b111, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_ECALL = {12'b000000000000, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_EBREAK = {12'b000000000001, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_URET = {12'b000000000010, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_SRET = {12'b000100000010, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_MRET = {12'b001100000010, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_DRET = {12'b011110110010, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_WFI = {12'b000100000101, 13'b0, TB_OPCODE_SYSTEM}; +// RV32M +parameter TB_INSTR_DIV = {7'b0000001, 10'b?, 3'b100, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_DIVU = {7'b0000001, 10'b?, 3'b101, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_REM = {7'b0000001, 10'b?, 3'b110, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_REMU = {7'b0000001, 10'b?, 3'b111, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_PMUL = {7'b0000001, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_PMUH = {7'b0000001, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_PMULHSU = {7'b0000001, 10'b?, 3'b010, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_PMULHU = {7'b0000001, 10'b?, 3'b011, 5'b?, TB_OPCODE_OP}; +// LOAD STORE +parameter TB_INSTR_LB = {17'b?, 3'b000, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_LH = {17'b?, 3'b001, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_LW = {17'b?, 3'b010, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_LBU = {17'b?, 3'b100, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_LHU = {17'b?, 3'b101, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_SB = {17'b?, 3'b000, 5'b?, TB_OPCODE_STORE}; +parameter TB_INSTR_SH = {17'b?, 3'b001, 5'b?, TB_OPCODE_STORE}; +parameter TB_INSTR_SW = {17'b?, 3'b010, 5'b?, TB_OPCODE_STORE}; + //XPULP instructions custom opcodes parameter OPCODE_CUSTOM_0 = 7'h0b; parameter OPCODE_CUSTOM_1 = 7'h2b; @@ -99,14 +217,22 @@ parameter INSTR_CV_SB_RR = {7'b0010100, 5'b?, 5'b?, 3'b011, 5'b?, parameter INSTR_CV_SH_RR = {7'b0010101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_SW_RR = {7'b0010110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_STARTI = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_START = {12'b0, 5'b?????, 3'b100, 4'b0001, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_ENDI = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_END = {12'b0, 5'b?????, 3'b100, 4'b0011, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_COUNTI = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_COUNT = {12'b0, 5'b?????, 3'b100, 4'b0101, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_SETUPI = {12'b?, 5'b?????, 3'b100, 4'b0110, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_SETUP = {12'b?, 5'b?????, 3'b100, 4'b0111, 1'b?, OPCODE_CUSTOM_1}; +parameter INSTR_CV_STARTI_0 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_START_0 = {12'b0, 5'b?????, 3'b100, 4'b0001, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_ENDI_0 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_END_0 = {12'b0, 5'b?????, 3'b100, 4'b0011, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_COUNTI_0 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_COUNT_0 = {12'b0, 5'b?????, 3'b100, 4'b0101, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SETUPI_0 = {12'b?, 5'b?????, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SETUP_0 = {12'b?, 5'b?????, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_STARTI_1 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_START_1 = {12'b0, 5'b?????, 3'b100, 4'b0001, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_ENDI_1 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_END_1 = {12'b0, 5'b?????, 3'b100, 4'b0011, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_COUNTI_1 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_COUNT_1 = {12'b0, 5'b?????, 3'b100, 4'b0101, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SETUPI_1 = {12'b?, 5'b?????, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SETUP_1 = {12'b?, 5'b?????, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1}; parameter INSTR_CV_EXTRACTR = {7'b0011000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_EXTRACTUR = {7'b0011001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; @@ -120,8 +246,8 @@ parameter INSTR_CV_CLB = {7'b0100011, 5'b0, 5'b?, 3'b011, 5'b?, parameter INSTR_CV_CNT = {7'b0100100, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_ABS = {7'b0101000, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_SLET = {7'b0101001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_SLETU = {7'b0101010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SLE = {7'b0101001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SLEU = {7'b0101010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_MIN = {7'b0101011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_MINU = {7'b0101100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_MAX = {7'b0101101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; @@ -443,4 +569,63 @@ parameter INSTR_CV_SUB_DIV2 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b0 parameter INSTR_CV_SUB_DIV4 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; parameter INSTR_CV_SUB_DIV8 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; +parameter APU_OP_FMADD = {6'h00}; +parameter APU_OP_FNMSUB = {6'h01}; +parameter APU_OP_FADD = {6'h02}; +parameter APU_OP_FMUL = {6'h03}; +parameter APU_OP_FDIV = {6'h04}; +parameter APU_OP_FSQRT = {6'h05}; +parameter APU_OP_FSGNJ = {6'h06}; +parameter APU_OP_FMINMAX = {6'h07}; +parameter APU_OP_FCMP = {6'h08}; +parameter APU_OP_FCLASSIFY = {6'h09}; +parameter APU_OP_F2F = {6'h0A}; +parameter APU_OP_F2I = {6'h0B}; +parameter APU_OP_I2F = {6'h0C}; + +parameter APU_OP_FMSUB = {6'h10}; +parameter APU_OP_FNMADD = {6'h11}; +parameter APU_OP_FSUB = {6'h12}; +parameter APU_OP_FSGNJ_SE = {6'h16}; +parameter APU_OP_F2I_U = {6'h1B}; +parameter APU_OP_I2F_U = {6'h1C}; + +//Additional defines based on DUT config parameters +`ifdef PULP //PULP = 1 + `ifndef FPU //FPU = 0 + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32X } + `else //FPU = 1 + `ifndef ZFINX + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32X, RV32F, RV32FC } + `else + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32X, RV32ZFINX } + `endif + `endif +`else //PULP = 0, FPU = 1 + `ifdef FPU + `ifndef ZFINX + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32F, RV32FC } + `else + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32ZFINX } + `endif + `endif +`endif + +//Base default ISA for tests if nothing else is defined +`ifndef CV32E40P_ISA_DV + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C } +`endif + +`ifdef FPU_ADDMUL_LAT + parameter FPU_ADDMUL_LAT_DV = `FPU_ADDMUL_LAT; +`else + parameter FPU_ADDMUL_LAT_DV = 0; +`endif + +`ifdef FPU_OTHERS_LAT + parameter FPU_OTHERS_LAT_DV = `FPU_OTHERS_LAT; +`else + parameter FPU_OTHERS_LAT_DV = 0; +`endif + `endif // __UVME_CV32E40P_CONSTANTS_SV__ diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_env.sv b/cv32e40p/env/uvme/uvme_cv32e40p_env.sv index 833d048a41..224198fb77 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_env.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_env.sv @@ -377,6 +377,11 @@ function void uvme_cv32e40p_env_c::retrieve_vifs(); `uvm_fatal("UVME_CV32E40P_ENV", $sformatf("No uvmt_cv32e40p_debug_cov_assert_if found in config database")) end + void'(uvm_config_db#(virtual uvmt_cv32e40p_cov_if)::get(this, "", "cov_vif", cntxt.cov_vif)); + if (cntxt.cov_vif == null) begin + `uvm_fatal("UVME_CV32E40P_ENV", $sformatf("No uvmt_cv32e40p_cov_if found in config database")) + end + endfunction: retrieve_vifs diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv index ebc3294088..6a629368c0 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv @@ -22,5 +22,487 @@ `define UVME_CV32E40P_MEM_SIZE 22 +`define COVIF_CB cntxt.cov_vif.mon_cb + +`define APU_INSTR_WITH_NO_FD \ + APU_OP_FCMP, APU_OP_FCLASSIFY, APU_OP_F2I, APU_OP_F2I_U + +`define RV32F_INSTR_WITH_NO_FS3 \ + TB_INS_FMADD,TB_INS_FMSUB,TB_INS_FNMSUB,TB_INS_FNMADD + +`define RV32_INSTR_WITH_NO_RS2 \ + TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM + +`define RV32F_INSTR_BINS \ + wildcard bins fadd = {TB_INS_FADD}; \ + wildcard bins fsub = {TB_INS_FSUB}; \ + wildcard bins fmul = {TB_INS_FMUL}; \ + wildcard bins fdiv = {TB_INS_FDIV}; \ + wildcard bins fsqrt = {TB_INS_FSQRT}; \ + wildcard bins fsgnjs = {TB_INS_FSGNJS}; \ + wildcard bins fsgnjns = {TB_INS_FSGNJNS}; \ + wildcard bins fsgnjxs = {TB_INS_FSGNJXS}; \ + wildcard bins fmin = {TB_INS_FMIN}; \ + wildcard bins fmax = {TB_INS_FMAX}; \ + wildcard bins fcvtws = {TB_INS_FCVTWS}; \ + wildcard bins fcvtwus = {TB_INS_FCVTWUS}; \ + wildcard bins fmvxs = {TB_INS_FMVXS}; \ + wildcard bins feqs = {TB_INS_FEQS}; \ + wildcard bins flts = {TB_INS_FLTS}; \ + wildcard bins fles = {TB_INS_FLES}; \ + wildcard bins fclass = {TB_INS_FCLASS}; \ + wildcard bins fcvtsw = {TB_INS_FCVTSW}; \ + wildcard bins fcvtswu = {TB_INS_FCVTSWU}; \ + wildcard bins fmvsw = {TB_INS_FMVSX}; \ + wildcard bins fmadd = {TB_INS_FMADD}; \ + wildcard bins fmsub = {TB_INS_FMSUB}; \ + wildcard bins fnmsub = {TB_INS_FNMSUB}; \ + wildcard bins fnmadd = {TB_INS_FNMADD}; \ + wildcard bins flw = {TB_INS_FLW}; \ + wildcard bins fsw = {TB_INS_FSW}; + +`define ZFINX_INSTR_BINS \ + wildcard bins fadd = {TB_INS_FADD}; \ + wildcard bins fsub = {TB_INS_FSUB}; \ + wildcard bins fmul = {TB_INS_FMUL}; \ + wildcard bins fdiv = {TB_INS_FDIV}; \ + wildcard bins fsqrt = {TB_INS_FSQRT}; \ + wildcard bins fsgnjs = {TB_INS_FSGNJS}; \ + wildcard bins fsgnjns = {TB_INS_FSGNJNS}; \ + wildcard bins fsgnjxs = {TB_INS_FSGNJXS}; \ + wildcard bins fmin = {TB_INS_FMIN}; \ + wildcard bins fmax = {TB_INS_FMAX}; \ + wildcard bins fcvtws = {TB_INS_FCVTWS}; \ + wildcard bins fcvtwus = {TB_INS_FCVTWUS}; \ + wildcard bins fmvxs = {TB_INS_FMVXS}; \ + wildcard bins feqs = {TB_INS_FEQS}; \ + wildcard bins flts = {TB_INS_FLTS}; \ + wildcard bins fles = {TB_INS_FLES}; \ + wildcard bins fclass = {TB_INS_FCLASS}; \ + wildcard bins fcvtsw = {TB_INS_FCVTSW}; \ + wildcard bins fcvtswu = {TB_INS_FCVTSWU}; \ + wildcard bins fmvsw = {TB_INS_FMVSX}; \ + wildcard bins fmadd = {TB_INS_FMADD}; \ + wildcard bins fmsub = {TB_INS_FMSUB}; \ + wildcard bins fnmsub = {TB_INS_FNMSUB}; \ + wildcard bins fnmadd = {TB_INS_FNMADD}; + +`define OPIMM_INSTR_BINS \ + wildcard bins addi = {TB_INSTR_ADDI}; \ + wildcard bins slti = {TB_INSTR_SLTI}; \ + wildcard bins sltiu = {TB_INSTR_SLTIU}; \ + wildcard bins xori = {TB_INSTR_XORI}; \ + wildcard bins ori = {TB_INSTR_ORI}; \ + wildcard bins andi = {TB_INSTR_ANDI}; \ + wildcard bins slli = {TB_INSTR_SLLI}; \ + wildcard bins srli = {TB_INSTR_SRLI}; \ + wildcard bins srai = {TB_INSTR_SRAI}; + +`define OP_INSTR_BINS \ + wildcard bins _add = {TB_INSTR_ADD}; \ + wildcard bins _sub = {TB_INSTR_SUB}; \ + wildcard bins _sll = {TB_INSTR_SLL}; \ + wildcard bins _slt = {TB_INSTR_SLT}; \ + wildcard bins _sltu = {TB_INSTR_SLTU}; \ + wildcard bins _xor = {TB_INSTR_XOR}; \ + wildcard bins _srl = {TB_INSTR_SRL}; \ + wildcard bins _sra = {TB_INSTR_SRA}; \ + wildcard bins _or = {TB_INSTR_OR}; \ + wildcard bins _and = {TB_INSTR_AND}; \ + +`define RV32M_INSTR_BINS \ + wildcard bins div = {TB_INSTR_DIV}; \ + wildcard bins divu = {TB_INSTR_DIVU}; \ + wildcard bins rem = {TB_INSTR_REM}; \ + wildcard bins remu = {TB_INSTR_REMU}; \ + wildcard bins pmul = {TB_INSTR_PMUL}; \ + wildcard bins pmuh = {TB_INSTR_PMUH}; \ + wildcard bins pmulhsu = {TB_INSTR_PMULHSU}; \ + wildcard bins pmulhu = {TB_INSTR_PMULHU}; + +`define LOAD_STORE_INSTR_BINS \ + wildcard bins lb = {TB_INSTR_LB}; \ + wildcard bins lh = {TB_INSTR_LH}; \ + wildcard bins lw = {TB_INSTR_LW}; \ + wildcard bins lbu = {TB_INSTR_LBU}; \ + wildcard bins lhu = {TB_INSTR_LHU}; \ + wildcard bins sb = {TB_INSTR_SB}; \ + wildcard bins sh = {TB_INSTR_SH}; \ + wildcard bins sw = {TB_INSTR_SW}; + +`define FPU_OP_BINS \ + bins apu_op_fmadd = {APU_OP_FMADD}; \ + bins apu_op_fnmsub = {APU_OP_FNMSUB}; \ + bins apu_op_fadd = {APU_OP_FADD}; \ + bins apu_op_fmul = {APU_OP_FMUL}; \ + bins apu_op_fdiv = {APU_OP_FDIV}; \ + bins apu_op_fsqrt = {APU_OP_FSQRT}; \ + bins apu_op_fsgnj = {APU_OP_FSGNJ}; \ + bins apu_op_fminmax = {APU_OP_FMINMAX}; \ + bins apu_op_fcmp = {APU_OP_FCMP}; \ + bins apu_op_fclassify = {APU_OP_FCLASSIFY}; \ + bins apu_op_f2f = {APU_OP_F2F}; \ + bins apu_op_f2i = {APU_OP_F2I}; \ + bins apu_op_i2f = {APU_OP_I2F}; \ + bins apu_op_fmsub = {APU_OP_FMSUB}; \ + bins apu_op_fnmadd = {APU_OP_FNMADD}; \ + bins apu_op_fsub = {APU_OP_FSUB}; \ + bins apu_op_fsgnj_se = {APU_OP_FSGNJ_SE}; \ + bins apu_op_f2i_u = {APU_OP_F2I_U}; \ + bins apu_op_i2f_u = {APU_OP_I2F_U}; + +`define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC \ + bins system_opcode = {TB_OPCODE_SYSTEM}; \ + bins fence_opcode = {TB_OPCODE_FENCE}; \ + bins op_opcode = {TB_OPCODE_OP}; \ + bins opimm_opcode = {TB_OPCODE_OPIMM}; \ + bins store_opcode = {TB_OPCODE_STORE}; \ + bins load_opcode = {TB_OPCODE_LOAD}; \ + bins branch_opcode = {TB_OPCODE_BRANCH}; \ + bins jalr_opcode = {TB_OPCODE_JALR}; \ + bins jal_opcode = {TB_OPCODE_JAL}; \ + bins auipc_opcode = {TB_OPCODE_AUIPC}; \ + bins lui_opcode = {TB_OPCODE_LUI}; \ + bins fpu_fp_opcode = {TB_OPCODE_OP_FP}; \ + bins fpu_fmadd_opcode = {TB_OPCODE_OP_FMADD}; \ + bins fpu_fnmadd_opcode = {TB_OPCODE_OP_FNMADD}; \ + bins fpu_fmsub_opcode = {TB_OPCODE_OP_FMSUB}; \ + bins fpu_fnmsub_opcode = {TB_OPCODE_OP_FNMSUB}; \ + bins fpu_str_opcode = {TB_OPCODE_STORE_FP}; \ + bins fpu_ld_opcode = {TB_OPCODE_LOAD_FP}; \ + bins xpulp_custom_0 = {OPCODE_CUSTOM_0}; \ + bins xpulp_custom_1 = {OPCODE_CUSTOM_1}; \ + bins xpulp_custom_2 = {OPCODE_CUSTOM_2}; \ + bins xpulp_custom_3 = {OPCODE_CUSTOM_3}; + +`define RV32X_PULP_INSTR_BINS \ + wildcard bins cv_lb_pi_ri = {INSTR_CV_LB_PI_RI}; \ + wildcard bins cv_lh_pi_ri = {INSTR_CV_LH_PI_RI}; \ + wildcard bins cv_lw_pi_ri = {INSTR_CV_LW_PI_RI}; \ + wildcard bins cv_elw_pi_ri = {INSTR_CV_ELW_PI_RI}; \ + wildcard bins cv_lbu_pi_ri = {INSTR_CV_LBU_PI_RI}; \ + wildcard bins cv_lhu_pi_ri = {INSTR_CV_LHU_PI_RI}; \ + wildcard bins cv_beqimm = {INSTR_CV_BEQIMM}; \ + wildcard bins cv_bneimm = {INSTR_CV_BNEIMM}; \ + wildcard bins cv_lb_pi_rr = {INSTR_CV_LB_PI_RR}; \ + wildcard bins cv_lh_pi_rr = {INSTR_CV_LH_PI_RR}; \ + wildcard bins cv_lw_pi_rr = {INSTR_CV_LW_PI_RR}; \ + wildcard bins cv_lbu_pi_rr = {INSTR_CV_LBU_PI_RR}; \ + wildcard bins cv_lhu_pi_rr = {INSTR_CV_LHU_PI_RR}; \ + wildcard bins cv_lb_rr = {INSTR_CV_LB_RR}; \ + wildcard bins cv_lh_rr = {INSTR_CV_LH_RR}; \ + wildcard bins cv_lw_rr = {INSTR_CV_LW_RR}; \ + wildcard bins cv_lbu_rr = {INSTR_CV_LBU_RR}; \ + wildcard bins cv_lhu_rr = {INSTR_CV_LHU_RR}; \ + wildcard bins cv_sb_pi_ri = {INSTR_CV_SB_PI_RI}; \ + wildcard bins cv_sh_pi_ri = {INSTR_CV_SH_PI_RI}; \ + wildcard bins cv_sw_pi_ri = {INSTR_CV_SW_PI_RI}; \ + wildcard bins cv_sb_pi_rr = {INSTR_CV_SB_PI_RR}; \ + wildcard bins cv_sh_pi_rr = {INSTR_CV_SH_PI_RR}; \ + wildcard bins cv_sw_pi_rr = {INSTR_CV_SW_PI_RR}; \ + wildcard bins cv_sb_rr = {INSTR_CV_SB_RR}; \ + wildcard bins cv_sh_rr = {INSTR_CV_SH_RR}; \ + wildcard bins cv_sw_rr = {INSTR_CV_SW_RR}; \ + wildcard bins cv_starti0 = {INSTR_CV_STARTI_0}; \ + wildcard bins cv_start0 = {INSTR_CV_START_0}; \ + wildcard bins cv_endi0 = {INSTR_CV_ENDI_0}; \ + wildcard bins cv_end0 = {INSTR_CV_END_0}; \ + wildcard bins cv_counti0 = {INSTR_CV_COUNTI_0}; \ + wildcard bins cv_count0 = {INSTR_CV_COUNT_0}; \ + wildcard bins cv_setupi0 = {INSTR_CV_SETUPI_0}; \ + wildcard bins cv_setup0 = {INSTR_CV_SETUP_0}; \ + wildcard bins cv_starti1 = {INSTR_CV_STARTI_1}; \ + wildcard bins cv_start1 = {INSTR_CV_START_1}; \ + wildcard bins cv_endi1 = {INSTR_CV_ENDI_1}; \ + wildcard bins cv_end1 = {INSTR_CV_END_1}; \ + wildcard bins cv_counti1 = {INSTR_CV_COUNTI_1}; \ + wildcard bins cv_count1 = {INSTR_CV_COUNT_1}; \ + wildcard bins cv_setupi1 = {INSTR_CV_SETUPI_1}; \ + wildcard bins cv_setup1 = {INSTR_CV_SETUP_1}; \ + wildcard bins cv_extractr = {INSTR_CV_EXTRACTR}; \ + wildcard bins cv_extractur = {INSTR_CV_EXTRACTUR}; \ + wildcard bins cv_insertr = {INSTR_CV_INSERTR}; \ + wildcard bins cv_bclrr = {INSTR_CV_BCLRR}; \ + wildcard bins cv_bsetr = {INSTR_CV_BSETR}; \ + wildcard bins cv_ror = {INSTR_CV_ROR}; \ + wildcard bins cv_ff1 = {INSTR_CV_FF1}; \ + wildcard bins cv_fl1 = {INSTR_CV_FL1}; \ + wildcard bins cv_clb = {INSTR_CV_CLB}; \ + wildcard bins cv_cnt = {INSTR_CV_CNT}; \ + wildcard bins cv_abs = {INSTR_CV_ABS}; \ + wildcard bins cv_sle = {INSTR_CV_SLE}; \ + wildcard bins cv_sleu = {INSTR_CV_SLEU}; \ + wildcard bins cv_min = {INSTR_CV_MIN}; \ + wildcard bins cv_minu = {INSTR_CV_MINU}; \ + wildcard bins cv_max = {INSTR_CV_MAX}; \ + wildcard bins cv_maxu = {INSTR_CV_MAXU}; \ + wildcard bins cv_exths = {INSTR_CV_EXTHS}; \ + wildcard bins cv_exthz = {INSTR_CV_EXTHZ}; \ + wildcard bins cv_extbs = {INSTR_CV_EXTBS}; \ + wildcard bins cv_extbz = {INSTR_CV_EXTBZ}; \ + wildcard bins cv_clip = {INSTR_CV_CLIP}; \ + wildcard bins cv_clipu = {INSTR_CV_CLIPU}; \ + wildcard bins cv_clipr = {INSTR_CV_CLIPR}; \ + wildcard bins cv_clipur = {INSTR_CV_CLIPUR}; \ + wildcard bins cv_addnr = {INSTR_CV_ADDNR}; \ + wildcard bins cv_addunr = {INSTR_CV_ADDUNR}; \ + wildcard bins cv_addrnr = {INSTR_CV_ADDRNR}; \ + wildcard bins cv_addurnr = {INSTR_CV_ADDURNR}; \ + wildcard bins cv_subnr = {INSTR_CV_SUBNR}; \ + wildcard bins cv_subunr = {INSTR_CV_SUBUNR}; \ + wildcard bins cv_subrnr = {INSTR_CV_SUBRNR}; \ + wildcard bins cv_suburnr = {INSTR_CV_SUBURNR}; \ + wildcard bins cv_mac = {INSTR_CV_MAC}; \ + wildcard bins cv_msu = {INSTR_CV_MSU}; \ + wildcard bins cv_extract = {INSTR_CV_EXTRACT}; \ + wildcard bins cv_extractu = {INSTR_CV_EXTRACTU}; \ + wildcard bins cv_insert = {INSTR_CV_INSERT}; \ + wildcard bins cv_bclr = {INSTR_CV_BCLR}; \ + wildcard bins cv_bset = {INSTR_CV_BSET}; \ + wildcard bins cv_bitrev = {INSTR_CV_BITREV}; \ + wildcard bins cv_addn = {INSTR_CV_ADDN}; \ + wildcard bins cv_addun = {INSTR_CV_ADDUN}; \ + wildcard bins cv_addrn = {INSTR_CV_ADDRN}; \ + wildcard bins cv_addurn = {INSTR_CV_ADDURN}; \ + wildcard bins cv_subn = {INSTR_CV_SUBN}; \ + wildcard bins cv_subun = {INSTR_CV_SUBUN}; \ + wildcard bins cv_subrn = {INSTR_CV_SUBRN}; \ + wildcard bins cv_suburn = {INSTR_CV_SUBURN}; \ + wildcard bins cv_mulsn = {INSTR_CV_MULSN}; \ + wildcard bins cv_mulhhsn = {INSTR_CV_MULHHSN}; \ + wildcard bins cv_mulsrn = {INSTR_CV_MULSRN}; \ + wildcard bins cv_mulhhsrn = {INSTR_CV_MULHHSRN}; \ + wildcard bins cv_mulun = {INSTR_CV_MULUN}; \ + wildcard bins cv_mulhhun = {INSTR_CV_MULHHUN}; \ + wildcard bins cv_mulurn = {INSTR_CV_MULURN}; \ + wildcard bins cv_mulhhurn = {INSTR_CV_MULHHURN}; \ + wildcard bins cv_macsn = {INSTR_CV_MACSN}; \ + wildcard bins cv_machhsn = {INSTR_CV_MACHHSN}; \ + wildcard bins cv_macsrn = {INSTR_CV_MACSRN}; \ + wildcard bins cv_machhsrn = {INSTR_CV_MACHHSRN}; \ + wildcard bins cv_macun = {INSTR_CV_MACUN}; \ + wildcard bins cv_machhun = {INSTR_CV_MACHHUN}; \ + wildcard bins cv_macurn = {INSTR_CV_MACURN}; \ + wildcard bins cv_machhurn = {INSTR_CV_MACHHURN}; \ + wildcard bins cv_add_h = {INSTR_CV_ADD_H}; \ + wildcard bins cv_add_sc_h = {INSTR_CV_ADD_SC_H}; \ + wildcard bins cv_add_sci_h = {INSTR_CV_ADD_SCI_H}; \ + wildcard bins cv_add_b = {INSTR_CV_ADD_B}; \ + wildcard bins cv_add_sc_b = {INSTR_CV_ADD_SC_B}; \ + wildcard bins cv_add_sci_b = {INSTR_CV_ADD_SCI_B}; \ + wildcard bins cv_sub_h = {INSTR_CV_SUB_H}; \ + wildcard bins cv_sub_sc_h = {INSTR_CV_SUB_SC_H}; \ + wildcard bins cv_sub_sci_h = {INSTR_CV_SUB_SCI_H}; \ + wildcard bins cv_sub_b = {INSTR_CV_SUB_B}; \ + wildcard bins cv_sub_sc_b = {INSTR_CV_SUB_SC_B}; \ + wildcard bins cv_sub_sci_b = {INSTR_CV_SUB_SCI_B}; \ + wildcard bins cv_avg_h = {INSTR_CV_AVG_H}; \ + wildcard bins cv_avg_sc_h = {INSTR_CV_AVG_SC_H}; \ + wildcard bins cv_avg_sci_h = {INSTR_CV_AVG_SCI_H}; \ + wildcard bins cv_avg_b = {INSTR_CV_AVG_B}; \ + wildcard bins cv_avg_sc_b = {INSTR_CV_AVG_SC_B}; \ + wildcard bins cv_avg_sci_b = {INSTR_CV_AVG_SCI_B}; \ + wildcard bins cv_avgu_h = {INSTR_CV_AVGU_H}; \ + wildcard bins cv_avgu_sc_h = {INSTR_CV_AVGU_SC_H}; \ + wildcard bins cv_avgu_sci_h = {INSTR_CV_AVGU_SCI_H}; \ + wildcard bins cv_avgu_b = {INSTR_CV_AVGU_B}; \ + wildcard bins cv_avgu_sc_b = {INSTR_CV_AVGU_SC_B}; \ + wildcard bins cv_avgu_sci_b = {INSTR_CV_AVGU_SCI_B}; \ + wildcard bins cv_min_h = {INSTR_CV_MIN_H}; \ + wildcard bins cv_min_sc_h = {INSTR_CV_MIN_SC_H}; \ + wildcard bins cv_min_sci_h = {INSTR_CV_MIN_SCI_H}; \ + wildcard bins cv_min_b = {INSTR_CV_MIN_B}; \ + wildcard bins cv_min_sc_b = {INSTR_CV_MIN_SC_B}; \ + wildcard bins cv_min_sci_b = {INSTR_CV_MIN_SCI_B}; \ + wildcard bins cv_minu_h = {INSTR_CV_MINU_H}; \ + wildcard bins cv_minu_sc_h = {INSTR_CV_MINU_SC_H}; \ + wildcard bins cv_minu_sci_h = {INSTR_CV_MINU_SCI_H}; \ + wildcard bins cv_minu_b = {INSTR_CV_MINU_B}; \ + wildcard bins cv_minu_sc_b = {INSTR_CV_MINU_SC_B}; \ + wildcard bins cv_minu_sci_b = {INSTR_CV_MINU_SCI_B}; \ + wildcard bins cv_max_h = {INSTR_CV_MAX_H}; \ + wildcard bins cv_max_sc_h = {INSTR_CV_MAX_SC_H}; \ + wildcard bins cv_max_sci_h = {INSTR_CV_MAX_SCI_H}; \ + wildcard bins cv_max_b = {INSTR_CV_MAX_B}; \ + wildcard bins cv_max_sc_b = {INSTR_CV_MAX_SC_B}; \ + wildcard bins cv_max_sci_b = {INSTR_CV_MAX_SCI_B}; \ + wildcard bins cv_maxu_h = {INSTR_CV_MAXU_H}; \ + wildcard bins cv_maxu_sc_h = {INSTR_CV_MAXU_SC_H}; \ + wildcard bins cv_maxu_sci_h = {INSTR_CV_MAXU_SCI_H}; \ + wildcard bins cv_maxu_b = {INSTR_CV_MAXU_B}; \ + wildcard bins cv_maxu_sc_b = {INSTR_CV_MAXU_SC_B}; \ + wildcard bins cv_maxu_sci_b = {INSTR_CV_MAXU_SCI_B}; \ + wildcard bins cv_srl_h = {INSTR_CV_SRL_H}; \ + wildcard bins cv_srl_sc_h = {INSTR_CV_SRL_SC_H}; \ + wildcard bins cv_srl_sci_h = {INSTR_CV_SRL_SCI_H}; \ + wildcard bins cv_srl_b = {INSTR_CV_SRL_B}; \ + wildcard bins cv_srl_sc_b = {INSTR_CV_SRL_SC_B}; \ + wildcard bins cv_srl_sci_b = {INSTR_CV_SRL_SCI_B}; \ + wildcard bins cv_sra_h = {INSTR_CV_SRA_H}; \ + wildcard bins cv_sra_sc_h = {INSTR_CV_SRA_SC_H}; \ + wildcard bins cv_sra_sci_h = {INSTR_CV_SRA_SCI_H}; \ + wildcard bins cv_sra_b = {INSTR_CV_SRA_B}; \ + wildcard bins cv_sra_sc_b = {INSTR_CV_SRA_SC_B}; \ + wildcard bins cv_sra_sci_b = {INSTR_CV_SRA_SCI_B}; \ + wildcard bins cv_sll_h = {INSTR_CV_SLL_H}; \ + wildcard bins cv_sll_sc_h = {INSTR_CV_SLL_SC_H}; \ + wildcard bins cv_sll_sci_h = {INSTR_CV_SLL_SCI_H}; \ + wildcard bins cv_sll_b = {INSTR_CV_SLL_B}; \ + wildcard bins cv_sll_sc_b = {INSTR_CV_SLL_SC_B}; \ + wildcard bins cv_sll_sci_b = {INSTR_CV_SLL_SCI_B}; \ + wildcard bins cv_or_h = {INSTR_CV_OR_H}; \ + wildcard bins cv_or_sc_h = {INSTR_CV_OR_SC_H}; \ + wildcard bins cv_or_sci_h = {INSTR_CV_OR_SCI_H}; \ + wildcard bins cv_or_b = {INSTR_CV_OR_B}; \ + wildcard bins cv_or_sc_b = {INSTR_CV_OR_SC_B}; \ + wildcard bins cv_or_sci_b = {INSTR_CV_OR_SCI_B}; \ + wildcard bins cv_xor_h = {INSTR_CV_XOR_H}; \ + wildcard bins cv_xor_sc_h = {INSTR_CV_XOR_SC_H}; \ + wildcard bins cv_xor_sci_h = {INSTR_CV_XOR_SCI_H}; \ + wildcard bins cv_xor_b = {INSTR_CV_XOR_B}; \ + wildcard bins cv_xor_sc_b = {INSTR_CV_XOR_SC_B}; \ + wildcard bins cv_xor_sci_b = {INSTR_CV_XOR_SCI_B}; \ + wildcard bins cv_and_h = {INSTR_CV_AND_H}; \ + wildcard bins cv_and_sc_h = {INSTR_CV_AND_SC_H}; \ + wildcard bins cv_and_sci_h = {INSTR_CV_AND_SCI_H}; \ + wildcard bins cv_and_b = {INSTR_CV_AND_B}; \ + wildcard bins cv_and_sc_b = {INSTR_CV_AND_SC_B}; \ + wildcard bins cv_and_sci_b = {INSTR_CV_AND_SCI_B}; \ + wildcard bins cv_abs_h = {INSTR_CV_ABS_H}; \ + wildcard bins cv_abs_b = {INSTR_CV_ABS_B}; \ + wildcard bins cv_dotup_h = {INSTR_CV_DOTUP_H}; \ + wildcard bins cv_dotup_sc_h = {INSTR_CV_DOTUP_SC_H}; \ + wildcard bins cv_dotup_sci_h = {INSTR_CV_DOTUP_SCI_H}; \ + wildcard bins cv_dotup_b = {INSTR_CV_DOTUP_B}; \ + wildcard bins cv_dotup_sc_b = {INSTR_CV_DOTUP_SC_B}; \ + wildcard bins cv_dotup_sci_b = {INSTR_CV_DOTUP_SCI_B}; \ + wildcard bins cv_dotusp_h = {INSTR_CV_DOTUSP_H}; \ + wildcard bins cv_dotusp_sc_h = {INSTR_CV_DOTUSP_SC_H}; \ + wildcard bins cv_dotusp_sci_h = {INSTR_CV_DOTUSP_SCI_H}; \ + wildcard bins cv_dotusp_b = {INSTR_CV_DOTUSP_B}; \ + wildcard bins cv_dotusp_sc_b = {INSTR_CV_DOTUSP_SC_B}; \ + wildcard bins cv_dotusp_sci_b = {INSTR_CV_DOTUSP_SCI_B}; \ + wildcard bins cv_dotsp_h = {INSTR_CV_DOTSP_H}; \ + wildcard bins cv_dotsp_sc_h = {INSTR_CV_DOTSP_SC_H}; \ + wildcard bins cv_dotsp_sci_h = {INSTR_CV_DOTSP_SCI_H}; \ + wildcard bins cv_dotsp_b = {INSTR_CV_DOTSP_B}; \ + wildcard bins cv_dotsp_sc_b = {INSTR_CV_DOTSP_SC_B}; \ + wildcard bins cv_dotsp_sci_b = {INSTR_CV_DOTSP_SCI_B}; \ + wildcard bins cv_sdotup_h = {INSTR_CV_SDOTUP_H}; \ + wildcard bins cv_sdotup_sc_h = {INSTR_CV_SDOTUP_SC_H}; \ + wildcard bins cv_sdotup_sci_h = {INSTR_CV_SDOTUP_SCI_H}; \ + wildcard bins cv_sdotup_b = {INSTR_CV_SDOTUP_B}; \ + wildcard bins cv_sdotup_sc_b = {INSTR_CV_SDOTUP_SC_B}; \ + wildcard bins cv_sdotup_sci_b = {INSTR_CV_SDOTUP_SCI_B}; \ + wildcard bins cv_sdotusp_h = {INSTR_CV_SDOTUSP_H}; \ + wildcard bins cv_sdotusp_sc_h = {INSTR_CV_SDOTUSP_SC_H}; \ + wildcard bins cv_sdotusp_sci_h = {INSTR_CV_SDOTUSP_SCI_H}; \ + wildcard bins cv_sdotusp_b = {INSTR_CV_SDOTUSP_B}; \ + wildcard bins cv_sdotusp_sc_b = {INSTR_CV_SDOTUSP_SC_B}; \ + wildcard bins cv_sdotusp_sci_b = {INSTR_CV_SDOTUSP_SCI_B}; \ + wildcard bins cv_sdotsp_h = {INSTR_CV_SDOTSP_H}; \ + wildcard bins cv_sdotsp_sc_h = {INSTR_CV_SDOTSP_SC_H}; \ + wildcard bins cv_sdotsp_sci_h = {INSTR_CV_SDOTSP_SCI_H}; \ + wildcard bins cv_sdotsp_b = {INSTR_CV_SDOTSP_B}; \ + wildcard bins cv_sdotsp_sc_b = {INSTR_CV_SDOTSP_SC_B}; \ + wildcard bins cv_sdotsp_sci_b = {INSTR_CV_SDOTSP_SCI_B}; \ + wildcard bins cv_extract_h = {INSTR_CV_EXTRACT_H}; \ + wildcard bins cv_extract_b = {INSTR_CV_EXTRACT_B}; \ + wildcard bins cv_extractu_h = {INSTR_CV_EXTRACTU_H}; \ + wildcard bins cv_extractu_b = {INSTR_CV_EXTRACTU_B}; \ + wildcard bins cv_insert_h = {INSTR_CV_INSERT_H}; \ + wildcard bins cv_insert_b = {INSTR_CV_INSERT_B}; \ + wildcard bins cv_shuffle_h = {INSTR_CV_SHUFFLE_H}; \ + wildcard bins cv_shuffle_sci_h = {INSTR_CV_SHUFFLE_SCI_H}; \ + wildcard bins cv_shuffle_b = {INSTR_CV_SHUFFLE_B}; \ + wildcard bins cv_shufflei0_sci_b = {INSTR_CV_SHUFFLEI0_SCI_B}; \ + wildcard bins cv_shufflei1_sci_b = {INSTR_CV_SHUFFLEI1_SCI_B}; \ + wildcard bins cv_shufflei2_sci_b = {INSTR_CV_SHUFFLEI2_SCI_B}; \ + wildcard bins cv_shufflei3_sci_b = {INSTR_CV_SHUFFLEI3_SCI_B}; \ + wildcard bins cv_shuffle2_h = {INSTR_CV_SHUFFLE2_H}; \ + wildcard bins cv_shuffle2_b = {INSTR_CV_SHUFFLE2_B}; \ + wildcard bins cv_pack = {INSTR_CV_PACK}; \ + wildcard bins cv_pack_h = {INSTR_CV_PACK_H}; \ + wildcard bins cv_packhi_b = {INSTR_CV_PACKHI_B}; \ + wildcard bins cv_packlo_b = {INSTR_CV_PACKLO_B}; \ + wildcard bins cv_cmpeq_h = {INSTR_CV_CMPEQ_H}; \ + wildcard bins cv_cmpeq_sc_h = {INSTR_CV_CMPEQ_SC_H}; \ + wildcard bins cv_cmpeq_sci_h = {INSTR_CV_CMPEQ_SCI_H}; \ + wildcard bins cv_cmpeq_b = {INSTR_CV_CMPEQ_B}; \ + wildcard bins cv_cmpeq_sc_b = {INSTR_CV_CMPEQ_SC_B}; \ + wildcard bins cv_cmpeq_sci_b = {INSTR_CV_CMPEQ_SCI_B}; \ + wildcard bins cv_cmpne_h = {INSTR_CV_CMPNE_H}; \ + wildcard bins cv_cmpne_sc_h = {INSTR_CV_CMPNE_SC_H}; \ + wildcard bins cv_cmpne_sci_h = {INSTR_CV_CMPNE_SCI_H}; \ + wildcard bins cv_cmpne_b = {INSTR_CV_CMPNE_B}; \ + wildcard bins cv_cmpne_sc_b = {INSTR_CV_CMPNE_SC_B}; \ + wildcard bins cv_cmpne_sci_b = {INSTR_CV_CMPNE_SCI_B}; \ + wildcard bins cv_cmpgt_h = {INSTR_CV_CMPGT_H}; \ + wildcard bins cv_cmpgt_sc_h = {INSTR_CV_CMPGT_SC_H}; \ + wildcard bins cv_cmpgt_sci_h = {INSTR_CV_CMPGT_SCI_H}; \ + wildcard bins cv_cmpgt_b = {INSTR_CV_CMPGT_B}; \ + wildcard bins cv_cmpgt_sc_b = {INSTR_CV_CMPGT_SC_B}; \ + wildcard bins cv_cmpgt_sci_b = {INSTR_CV_CMPGT_SCI_B}; \ + wildcard bins cv_cmpge_h = {INSTR_CV_CMPGE_H}; \ + wildcard bins cv_cmpge_sc_h = {INSTR_CV_CMPGE_SC_H}; \ + wildcard bins cv_cmpge_sci_h = {INSTR_CV_CMPGE_SCI_H}; \ + wildcard bins cv_cmpge_b = {INSTR_CV_CMPGE_B}; \ + wildcard bins cv_cmpge_sc_b = {INSTR_CV_CMPGE_SC_B}; \ + wildcard bins cv_cmpge_sci_b = {INSTR_CV_CMPGE_SCI_B}; \ + wildcard bins cv_cmplt_h = {INSTR_CV_CMPLT_H}; \ + wildcard bins cv_cmplt_sc_h = {INSTR_CV_CMPLT_SC_H}; \ + wildcard bins cv_cmplt_sci_h = {INSTR_CV_CMPLT_SCI_H}; \ + wildcard bins cv_cmplt_b = {INSTR_CV_CMPLT_B}; \ + wildcard bins cv_cmplt_sc_b = {INSTR_CV_CMPLT_SC_B}; \ + wildcard bins cv_cmplt_sci_b = {INSTR_CV_CMPLT_SCI_B}; \ + wildcard bins cv_cmple_h = {INSTR_CV_CMPLE_H}; \ + wildcard bins cv_cmple_sc_h = {INSTR_CV_CMPLE_SC_H}; \ + wildcard bins cv_cmple_sci_h = {INSTR_CV_CMPLE_SCI_H}; \ + wildcard bins cv_cmple_b = {INSTR_CV_CMPLE_B}; \ + wildcard bins cv_cmple_sc_b = {INSTR_CV_CMPLE_SC_B}; \ + wildcard bins cv_cmple_sci_b = {INSTR_CV_CMPLE_SCI_B}; \ + wildcard bins cv_cmpgtu_h = {INSTR_CV_CMPGTU_H}; \ + wildcard bins cv_cmpgtu_sc_h = {INSTR_CV_CMPGTU_SC_H}; \ + wildcard bins cv_cmpgtu_sci_h = {INSTR_CV_CMPGTU_SCI_H}; \ + wildcard bins cv_cmpgtu_b = {INSTR_CV_CMPGTU_B}; \ + wildcard bins cv_cmpgtu_sc_b = {INSTR_CV_CMPGTU_SC_B}; \ + wildcard bins cv_cmpgtu_sci_b = {INSTR_CV_CMPGTU_SCI_B}; \ + wildcard bins cv_cmpgeu_h = {INSTR_CV_CMPGEU_H}; \ + wildcard bins cv_cmpgeu_sc_h = {INSTR_CV_CMPGEU_SC_H}; \ + wildcard bins cv_cmpgeu_sci_h = {INSTR_CV_CMPGEU_SCI_H}; \ + wildcard bins cv_cmpgeu_b = {INSTR_CV_CMPGEU_B}; \ + wildcard bins cv_cmpgeu_sc_b = {INSTR_CV_CMPGEU_SC_B}; \ + wildcard bins cv_cmpgeu_sci_b = {INSTR_CV_CMPGEU_SCI_B}; \ + wildcard bins cv_cmpltu_h = {INSTR_CV_CMPLTU_H}; \ + wildcard bins cv_cmpltu_sc_h = {INSTR_CV_CMPLTU_SC_H}; \ + wildcard bins cv_cmpltu_sci_h = {INSTR_CV_CMPLTU_SCI_H}; \ + wildcard bins cv_cmpltu_b = {INSTR_CV_CMPLTU_B}; \ + wildcard bins cv_cmpltu_sc_b = {INSTR_CV_CMPLTU_SC_B}; \ + wildcard bins cv_cmpltu_sci_b = {INSTR_CV_CMPLTU_SCI_B}; \ + wildcard bins cv_cmpleu_h = {INSTR_CV_CMPLEU_H}; \ + wildcard bins cv_cmpleu_sc_h = {INSTR_CV_CMPLEU_SC_H}; \ + wildcard bins cv_cmpleu_sci_h = {INSTR_CV_CMPLEU_SCI_H}; \ + wildcard bins cv_cmpleu_b = {INSTR_CV_CMPLEU_B}; \ + wildcard bins cv_cmpleu_sc_b = {INSTR_CV_CMPLEU_SC_B}; \ + wildcard bins cv_cmpleu_sci_b = {INSTR_CV_CMPLEU_SCI_B}; \ + wildcard bins cv_cplxmul_r = {INSTR_CV_CPLXMUL_R}; \ + wildcard bins cv_cplxmul_r_div2 = {INSTR_CV_CPLXMUL_R_DIV2}; \ + wildcard bins cv_cplxmul_r_div4 = {INSTR_CV_CPLXMUL_R_DIV4}; \ + wildcard bins cv_cplxmul_r_div8 = {INSTR_CV_CPLXMUL_R_DIV8}; \ + wildcard bins cv_cplxmul_i = {INSTR_CV_CPLXMUL_I}; \ + wildcard bins cv_cplxmul_i_div2 = {INSTR_CV_CPLXMUL_I_DIV2}; \ + wildcard bins cv_cplxmul_i_div4 = {INSTR_CV_CPLXMUL_I_DIV4}; \ + wildcard bins cv_cplxmul_i_div8 = {INSTR_CV_CPLXMUL_I_DIV8}; \ + wildcard bins cv_cplxconj = {INSTR_CV_CPLXCONJ}; \ + wildcard bins cv_subrotmj = {INSTR_CV_SUBROTMJ}; \ + wildcard bins cv_subrotmj_div2 = {INSTR_CV_SUBROTMJ_DIV2}; \ + wildcard bins cv_subrotmj_div4 = {INSTR_CV_SUBROTMJ_DIV4}; \ + wildcard bins cv_subrotmj_div8 = {INSTR_CV_SUBROTMJ_DIV8}; \ + wildcard bins cv_add_div2 = {INSTR_CV_ADD_DIV2}; \ + wildcard bins cv_add_div4 = {INSTR_CV_ADD_DIV4}; \ + wildcard bins cv_add_div8 = {INSTR_CV_ADD_DIV8}; \ + wildcard bins cv_sub_div2 = {INSTR_CV_SUB_DIV2}; \ + wildcard bins cv_sub_div4 = {INSTR_CV_SUB_DIV4}; \ + wildcard bins cv_sub_div8 = {INSTR_CV_SUB_DIV8}; `endif // __UVME_CV32E40P_MACROS_SV__ diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv b/cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv deleted file mode 100644 index 6bbfc0ba4e..0000000000 --- a/cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv +++ /dev/null @@ -1,624 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2023 Dolphin Design -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40P_PARAM_ALL_INSN__ -`define __UVME_CV32E40P_PARAM_ALL_INSN__ - -// note: -// 1) below instructions parameters are mirror copy of cv32e40p_pkg.sv and cv32e40p_tracer_pkg.sv -// 2) cv32e40p_pkg.sv is available at /cv32e40p/rtl/include -// 3) cv32e40p_tracer_pkg.sv is available at /cv32e40p/bhv/include - - //////////////////////////////////////////////// - // ___ ____ _ // - // / _ \ _ __ / ___|___ __| | ___ ___ // - // | | | | '_ \| | / _ \ / _` |/ _ \/ __| // - // | |_| | |_) | |__| (_) | (_| | __/\__ \ // - // \___/| .__/ \____\___/ \__,_|\___||___/ // - // |_| // - //////////////////////////////////////////////// - - parameter OPCODE_SYSTEM = 7'h73; - parameter OPCODE_FENCE = 7'h0f; - parameter OPCODE_OP = 7'h33; - parameter OPCODE_OPIMM = 7'h13; - parameter OPCODE_STORE = 7'h23; - parameter OPCODE_LOAD = 7'h03; - parameter OPCODE_BRANCH = 7'h63; - parameter OPCODE_JALR = 7'h67; - parameter OPCODE_JAL = 7'h6f; - parameter OPCODE_AUIPC = 7'h17; - parameter OPCODE_LUI = 7'h37; - parameter OPCODE_OP_FP = 7'h53; - parameter OPCODE_OP_FMADD = 7'h43; - parameter OPCODE_OP_FNMADD = 7'h4f; - parameter OPCODE_OP_FMSUB = 7'h47; - parameter OPCODE_OP_FNMSUB = 7'h4b; - parameter OPCODE_STORE_FP = 7'h27; - parameter OPCODE_LOAD_FP = 7'h07; - parameter OPCODE_AMO = 7'h2F; - // Those custom opcodes are used for PULP custom instructions - // parameter OPCODE_CUSTOM_0 = 7'h0b; - // parameter OPCODE_CUSTOM_1 = 7'h2b; - // parameter OPCODE_CUSTOM_2 = 7'h5b; - // parameter OPCODE_CUSTOM_3 = 7'h7b; - - // Atomic operations - parameter AMO_LR = 5'b00010; - parameter AMO_SC = 5'b00011; - parameter AMO_SWAP = 5'b00001; - parameter AMO_ADD = 5'b00000; - parameter AMO_XOR = 5'b00100; - parameter AMO_AND = 5'b01100; - parameter AMO_OR = 5'b01000; - parameter AMO_MIN = 5'b10000; - parameter AMO_MAX = 5'b10100; - parameter AMO_MINU = 5'b11000; - parameter AMO_MAXU = 5'b11100; - - // instruction masks (for tracer) - parameter INSTR_LUI = {25'b?, OPCODE_LUI}; - parameter INSTR_AUIPC = {25'b?, OPCODE_AUIPC}; - parameter INSTR_JAL = {25'b?, OPCODE_JAL}; - parameter INSTR_JALR = {17'b?, 3'b000, 5'b?, OPCODE_JALR}; - // BRANCH - parameter INSTR_BEQ = {17'b?, 3'b000, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BNE = {17'b?, 3'b001, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BLT = {17'b?, 3'b100, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BGE = {17'b?, 3'b101, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BLTU = {17'b?, 3'b110, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BGEU = {17'b?, 3'b111, 5'b?, OPCODE_BRANCH}; - // OPIMM - parameter INSTR_ADDI = {17'b?, 3'b000, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SLTI = {17'b?, 3'b010, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SLTIU = {17'b?, 3'b011, 5'b?, OPCODE_OPIMM}; - parameter INSTR_XORI = {17'b?, 3'b100, 5'b?, OPCODE_OPIMM}; - parameter INSTR_ORI = {17'b?, 3'b110, 5'b?, OPCODE_OPIMM}; - parameter INSTR_ANDI = {17'b?, 3'b111, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SLLI = {7'b0000000, 10'b?, 3'b001, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SRLI = {7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SRAI = {7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OPIMM}; - // OP - parameter INSTR_ADD = {7'b0000000, 10'b?, 3'b000, 5'b?, OPCODE_OP}; - parameter INSTR_SUB = {7'b0100000, 10'b?, 3'b000, 5'b?, OPCODE_OP}; - parameter INSTR_SLL = {7'b0000000, 10'b?, 3'b001, 5'b?, OPCODE_OP}; - parameter INSTR_SLT = {7'b0000000, 10'b?, 3'b010, 5'b?, OPCODE_OP}; - parameter INSTR_SLTU = {7'b0000000, 10'b?, 3'b011, 5'b?, OPCODE_OP}; - parameter INSTR_XOR = {7'b0000000, 10'b?, 3'b100, 5'b?, OPCODE_OP}; - parameter INSTR_SRL = {7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OP}; - parameter INSTR_SRA = {7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OP}; - parameter INSTR_OR = {7'b0000000, 10'b?, 3'b110, 5'b?, OPCODE_OP}; - parameter INSTR_AND = {7'b0000000, 10'b?, 3'b111, 5'b?, OPCODE_OP}; - - parameter INSTR_PAVG = {7'b0000010, 10'b?, 3'b000, 5'b?, OPCODE_OP}; - parameter INSTR_PAVGU = {7'b0000010, 10'b?, 3'b001, 5'b?, OPCODE_OP}; - - // FENCE - parameter INSTR_FENCE = {4'b0, 8'b?, 13'b0, OPCODE_FENCE}; - parameter INSTR_FENCEI = {17'b0, 3'b001, 5'b0, OPCODE_FENCE}; - // SYSTEM - parameter INSTR_CSRRW = {17'b?, 3'b001, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRS = {17'b?, 3'b010, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRC = {17'b?, 3'b011, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRWI = {17'b?, 3'b101, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRSI = {17'b?, 3'b110, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRCI = {17'b?, 3'b111, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_ECALL = {12'b000000000000, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_EBREAK = {12'b000000000001, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_URET = {12'b000000000010, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_SRET = {12'b000100000010, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_MRET = {12'b001100000010, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_DRET = {12'b011110110010, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_WFI = {12'b000100000101, 13'b0, OPCODE_SYSTEM}; - - // RV32M - parameter INSTR_DIV = {7'b0000001, 10'b?, 3'b100, 5'b?, OPCODE_OP}; - parameter INSTR_DIVU = {7'b0000001, 10'b?, 3'b101, 5'b?, OPCODE_OP}; - parameter INSTR_REM = {7'b0000001, 10'b?, 3'b110, 5'b?, OPCODE_OP}; - parameter INSTR_REMU = {7'b0000001, 10'b?, 3'b111, 5'b?, OPCODE_OP}; - parameter INSTR_PMUL = {7'b0000001, 10'b?, 3'b000, 5'b?, OPCODE_OP}; - parameter INSTR_PMUH = {7'b0000001, 10'b?, 3'b001, 5'b?, OPCODE_OP}; - parameter INSTR_PMULHSU = {7'b0000001, 10'b?, 3'b010, 5'b?, OPCODE_OP}; - parameter INSTR_PMULHU = {7'b0000001, 10'b?, 3'b011, 5'b?, OPCODE_OP}; - - // RV32F - parameter INSTR_FMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FMADD}; - parameter INSTR_FMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FMSUB}; - parameter INSTR_FNMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FNMSUB}; - parameter INSTR_FNMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FNMADD}; - - parameter INSTR_FADD = {5'b00000, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSUB = {5'b00001, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMUL = {5'b00010, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FDIV = {5'b00011, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSQRT = {5'b01011, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSGNJS = {5'b00100, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSGNJNS = {5'b00100, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSGNJXS = {5'b00100, 2'b00, 10'b?, 3'b010, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMIN = {5'b00101, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMAX = {5'b00101, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCVTWS = {5'b11000, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCVTWUS = {5'b11000, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMVXS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FEQS = {5'b10100, 2'b00, 10'b?, 3'b010, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FLTS = {5'b10100, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FLES = {5'b10100, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCLASS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b001, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCVTSW = {5'b11010, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCVTSWU = {5'b11010, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMVSX = {5'b11110, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - - // RV32A - parameter INSTR_LR = {AMO_LR, 2'b?, 5'b0, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_SC = {AMO_SC, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOSWAP = {AMO_SWAP, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOADD = {AMO_ADD, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOXOR = {AMO_XOR, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOAND = {AMO_AND, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOOR = {AMO_OR, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOMIN = {AMO_MIN, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOMAX = {AMO_MAX, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOMINU = {AMO_MINU, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOMAXU = {AMO_MAXU, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - - - // LOAD STORE - parameter INSTR_LB = {17'b?, 3'b000, 5'b?, OPCODE_LOAD}; - parameter INSTR_LH = {17'b?, 3'b001, 5'b?, OPCODE_LOAD}; - parameter INSTR_LW = {17'b?, 3'b010, 5'b?, OPCODE_LOAD}; - parameter INSTR_LBU = {17'b?, 3'b100, 5'b?, OPCODE_LOAD}; - parameter INSTR_LHU = {17'b?, 3'b101, 5'b?, OPCODE_LOAD}; - - parameter INSTR_SB = {17'b?, 3'b000, 5'b?, OPCODE_STORE}; - parameter INSTR_SH = {17'b?, 3'b001, 5'b?, OPCODE_STORE}; - parameter INSTR_SW = {17'b?, 3'b010, 5'b?, OPCODE_STORE}; - - // parameter INSTR_FL = {OPCODE_LOAD_FP}; - // parameter INSTR_FS = {OPCODE_STORE_FP} - - // CUSTOM_0 - parameter INSTR_BEQIMM = {17'b?, 3'b110, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_BNEIMM = {17'b?, 3'b111, 5'b?, OPCODE_CUSTOM_0}; - - // Post-Increment Register-Immediate Load - parameter INSTR_CVLBI = {17'b?, 3'b000, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_CVLBUI = {17'b?, 3'b100, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_CVLHI = {17'b?, 3'b001, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_CVLHUI = {17'b?, 3'b101, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_CVLWI = {17'b?, 3'b010, 5'b?, OPCODE_CUSTOM_0}; - - // Event Load - parameter INSTR_CVELW = {17'b?, 3'b011, 5'b?, OPCODE_CUSTOM_0}; - - // CUSTOM_1 - // Post-Increment Register-Register Load - parameter INSTR_CVLBR = {7'b0000000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLBUR = {7'b0001000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLHR = {7'b0000001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLHUR = {7'b0001001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLWR = {7'b0000010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // Register-Register Load - parameter INSTR_CVLBRR = {7'b0000100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLBURR = {7'b0001100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLHRR = {7'b0000101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLHURR = {7'b0001101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLWRR = {7'b0000110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // Post-Increment Register-Immediate Store - parameter INSTR_CVSBI = {17'b?, 3'b000, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSHI = {17'b?, 3'b001, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSWI = {17'b?, 3'b010, 5'b?, OPCODE_CUSTOM_1}; - - // Post-Increment Register-Register Store operations encoding - parameter INSTR_CVSBR = {7'b0010000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSHR = {7'b0010001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSWR = {7'b0010010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // Register-Register Store operations - parameter INSTR_CVSBRR = {7'b0010100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSHRR = {7'b0010101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSWRR = {7'b0010110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // Hardware Loops - parameter INSTR_CVSTARTI0 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVSTART0 = {12'b000000000000, 5'b?, 3'b100, 4'b0001, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVSENDI0 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVEND0 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVCOUNTI0 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVCOUNT0 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVSETUPI0 = {17'b?, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVSETUP0 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1}; - - parameter INSTR_CVSTARTI1 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVSTART1 = {12'b000000000000, 5'b?, 3'b100, 4'b0001, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVSENDI1 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVEND1 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVCOUNTI1 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVCOUNT1 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVSETUPI1 = {17'b?, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVSETUP1 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1}; - - - parameter INSTR_FF1 = {7'b0100001, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_FL1 = {7'b0100010, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CLB = {7'b0100011, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CNT = {7'b0100100, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_EXTHS = {7'b0110000, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_EXTHZ = {7'b0110001, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_EXTBS = {7'b0110010, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_EXTBZ = {7'b0110011, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PADDNR = {7'b1000000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PADDUNR = {7'b1000001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PADDRNR = {7'b1000010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PADDURNR = {7'b1000011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSUBNR = {7'b1000100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSUBUNR = {7'b1000101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSUBRNR = {7'b1000110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSUBURNR = {7'b1000111, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PABS = {7'b0101000, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PCLIP = {7'b0111000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PCLIPU = {7'b0111001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PCLIPR = {7'b0111010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PCLIPUR = {7'b0111011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PSLET = {7'b0101001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSLETU = {7'b0101010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMIN = {7'b0101011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMINU = {7'b0101100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMAX = {7'b0101101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMAXU = {7'b0101110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_ROR = {7'b0100000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PBEXTR = {7'b0011000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PBEXTUR = {7'b0011001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PBINSR = {7'b0011010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PBCLRR = {7'b0011100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PBSETR = {7'b0011101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PMAC = {7'b1001000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMSU = {7'b1001001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // CUSTOM_2 - parameter INSTR_PBEXT = {2'b00, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBEXTU = {2'b01, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBINS = {2'b10, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBCLR = {2'b00, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBSET = {2'b01, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBREV = {2'b11, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_2}; - - parameter INSTR_PADDN = {2'b00, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PADDUN = {2'b01, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PADDRN = {2'b10, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PADDURN = {2'b11, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PSUBN = {2'b00, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PSUBUN = {2'b01, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PSUBRN = {2'b10, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PSUBURN = {2'b11, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; - - parameter INSTR_PMULSN = {2'b00, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULHHSN = {2'b01, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULSRN = {2'b10, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULHHSRN = {2'b11, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULUN = {2'b00, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULHHUN = {2'b01, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULURN = {2'b10, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULHHURN = {2'b11, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACSN = {2'b00, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACHHSN = {2'b01, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACSRN = {2'b10, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACHHSRN = {2'b11, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACUN = {2'b00, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACHHUN = {2'b01, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACURN = {2'b10, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACHHURN = {2'b11, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; - - - // CUSTOM_3 - // SIMD ALU - parameter INSTR_CVADDH = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDSCH = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDSCIH = {5'b00000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDB = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDSCB = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDSCIB = {5'b00000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSUBH = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBSCH = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBSCIH = {5'b00001, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBB = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBSCB = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBSCIB = {5'b00001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVAVGH = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGSCH = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGSCIH = {5'b00010, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGB = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGSCB = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGSCIB = {5'b00010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVAVGUH = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUSCH = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUSCIH = {5'b00011, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUB = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUSCB = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUSCIB = {5'b00011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVMINH = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINSCH = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINSCIH = {5'b00100, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINB = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINSCB = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINSCIB = {5'b00100, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVMINUH = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUSCH = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUSCIH = {5'b00101, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUB = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUSCB = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUSCIB = {5'b00101, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVMAXH = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXSCH = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXSCIH = {5'b00110, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXB = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXSCB = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXSCIB = {5'b00110, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVMAXUH = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUSCH = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUSCIH = {5'b00111, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUB = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUSCB = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUSCIB = {5'b00111, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSRLH = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLSCH = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLSCIH = {5'b01000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLB = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLSCB = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLSCIB = {5'b01000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSRAH = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRASCH = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRASCIH = {5'b01001, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRAB = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRASCB = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRASCIB = {5'b01001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSLLH = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLSCH = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLSCIH = {5'b01010, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLB = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLSCB = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLSCIB = {5'b01010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVORH = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORSCH = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORSCIH = {5'b01011, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORB = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORSCB = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORSCIB = {5'b01011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVXORH = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORSCH = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORSCIH = {5'b01100, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORB = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORSCB = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORSCIB = {5'b01100, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVANDH = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDSCH = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDSCIH = {5'b01101, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDB = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDSCB = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDSCIB = {5'b01101, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVABSH = {5'b01110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVABSB = {5'b01110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVEXTRACTH = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVEXTRACTB = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVEXTRACTUH = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVEXTRACTUB = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVINSERTH = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVINSERTB = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVDOTUPH = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPSCH = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPSCIH = {5'b10000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPB = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPSCB = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPSCIB = {5'b10000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVDOTUSPH = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPSCH = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPSCIH = {5'b10001, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPB = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPSCB = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPSCIB = {5'b10001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVDOTSPH = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPSCH = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPSCIH = {5'b10010, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPB = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPSCB = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPSCIB = {5'b10010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSDOTUPH = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPSCH = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPSCIH = {5'b10011, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPB = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPSCB = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPSCIB = {5'b10011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSDOTUSPH = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPSCH = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPSCIH = {5'b10100, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPB = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPSCB = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPSCIB = {5'b10100, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSDOTSPH = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPSCH = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPSCIH = {5'b10101, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPB = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPSCB = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPSCIB = {5'b10101, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSHUFFLEH = {5'b11000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLESCIH = {5'b11000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEB = {5'b11000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEL0SCIB = {5'b11000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEL1SCIB = {5'b11001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEL2SCIB = {5'b11010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEL3SCIB = {5'b11011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSHUFFLE2H = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLE2B = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVPACK = {5'b11110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVPACKH = {5'b11110, 1'b0, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVPACKHIB = {5'b11111, 1'b0, 1'b1, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVPACKLOB = {5'b11111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - - // SIMD COMPARISON - parameter INSTR_CVCMPEQH = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQSCH = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQSCIH = {5'b00000, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQB = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQSCB = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQSCIB = {5'b00000, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPNEH = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNESCH = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNESCIH = {5'b00001, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNEB = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNESCB = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNESCIB = {5'b00001, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPGTH = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTSCH = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTSCIH = {5'b00010, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTB = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTSCB = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTSCIB = {5'b00010, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPGEH = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGESCH = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGESCIH = {5'b00011, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEB = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGESCB = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGESCIB = {5'b00011, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPLTH = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTSCH = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTSCIH = {5'b00100, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTB = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTSCB = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTSCIB = {5'b00100, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPLEH = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLESCH = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLESCIH = {5'b00101, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEB = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLESCB = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLESCIB = {5'b00101, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPGTUH = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUSCH = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUSCIH = {5'b00110, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUB = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUSCB = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUSCIB = {5'b00110, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPGEUH = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUSCH = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUSCIH = {5'b00111, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUB = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUSCB = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUSCIB = {5'b00111, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPLTUH = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUSCH = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUSCIH = {5'b01000, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUB = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUSCB = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUSCIB = {5'b01000, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPLEUH = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUSCH = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUSCIH = {5'b01001, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUB = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUSCB = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUSCIB = {5'b01001, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - // SIMD CPLX - parameter INSTR_CVCPLXMULR = {5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCPLXMULRDIV2 = { - 5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVCPLXMULRDIV4 = { - 5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVCPLXMULRDIV8 = { - 5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3 - }; - - parameter INSTR_CVCPLXMULI = {5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCPLXMULIDIV2 = { - 5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVCPLXMULIDIV4 = { - 5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVCPLXMULIDIV8 = { - 5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3 - }; - - parameter INSTR_CVCPLXCONJ = { - 5'b01011, 1'b1, 1'b0, 5'b00000, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3 - }; - - parameter INSTR_CVSUBROTMJ = {5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBROTMJDIV2 = { - 5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVSUBROTMJDIV4 = { - 5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVSUBROTMJDIV8 = { - 5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3 - }; - - parameter INSTR_CVADDIV2 = {5'b01101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDIV4 = {5'b01101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDIV8 = {5'b01101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSUBIV2 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBIV4 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBIV8 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - - // Load-Store (RV32F) - parameter INSTR_FLW = {17'b?, 3'b010, 5'b?, OPCODE_LOAD_FP}; - parameter INSTR_FSW = {17'b?, 3'b010, 5'b?, OPCODE_STORE_FP}; - -`endif diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv index 3e03846598..18d50f4ed4 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv @@ -27,6 +27,7 @@ `include "uvma_clknrst_macros.sv" `include "uvme_cv32e40p_macros.sv" + /** * Encapsulates all the types needed for an UVM environment capable of driving/ * monitoring and verifying the behavior of an CV32E40P design. @@ -50,9 +51,10 @@ package uvme_cv32e40p_pkg; // Constants / Structs / Enums `include "uvme_cv32e40p_constants.sv" - `include "uvme_cv32e40p_param_all_insn.sv" // fixme: remove this and import package from core-v-cores (e.g cv32e40p_tracer_pkg.sv) `include "uvme_cv32e40p_tdefs.sv" + cv32e40p_isa_ext_t cv32e40p_core_isa_list[$] = `CV32E40P_ISA_DV; // CV32E40P supported ISAs + // Objects `include "uvma_cv32e40p_core_cntrl_cntxt.sv" `include "uvme_cv32e40p_cfg.sv" @@ -85,6 +87,8 @@ package uvme_cv32e40p_pkg; `include "uvme_interrupt_covg.sv" `include "uvme_debug_covg.sv" `include "uvme_rv32isa_covg.sv" + `include "uvme_cv32e40p_fp_instr_covg.sv" + `include "uvme_cv32e40p_zfinx_instr_covg.sv" `include "uvme_cv32e40p_cov_model.sv" `include "uvme_cv32e40p_sb.sv" `include "uvme_cv32e40p_vsqr.sv" diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv b/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv index cfd7abf688..0d09994bbf 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv @@ -125,17 +125,27 @@ typedef enum { } fetch_toggle_t; typedef enum logic [2:0] { - EBREAKM = 1, - TRIGGER = 2, - HALTREQ = 3, - STEP = 4, - RESETHALTREQ = 5 + EBREAKM = 1, + TRIGGER = 2, + HALTREQ = 3, + STEP = 4, + RESETHALTREQ = 5 } dcsr_cause_t; typedef enum logic [4:0] { - CODE_ILLEGAL = 2, - CODE_EBREAK = 3, - CODE_ECALL = 11 + CODE_ILLEGAL = 2, + CODE_EBREAK = 3, + CODE_ECALL = 11 } exception_code_t; +typedef enum { + RV32I, + RV32M, + RV32C, + RV32F, + RV32FC, + RV32ZFINX, + RV32X +} cv32e40p_isa_ext_t; + `endif // __UVME_CV32E40P_TDEFS_SV__ diff --git a/cv32e40p/regress/cv32e40p_debug.yaml b/cv32e40p/regress/cv32e40p_debug.yaml index cd41ad2953..644933da4d 100644 --- a/cv32e40p/regress/cv32e40p_debug.yaml +++ b/cv32e40p/regress/cv32e40p_debug.yaml @@ -35,8 +35,8 @@ tests: build: uvmt_cv32e40p description: Debug reset test with random boot set dir: cv32e40p/sim/uvmt - cmd: make test TEST=debug_test_boot_set - num: 50 + cmd: make test TEST=debug_test_boot_set SEED=1 VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + num: 1 corev_rand_debug: build: uvmt_cv32e40p diff --git a/cv32e40p/regress/cv32e40p_full_covg_no_pulp.yaml b/cv32e40p/regress/cv32e40p_full_covg_no_pulp.yaml index 92e2b1d84e..b0349d91db 100644 --- a/cv32e40p/regress/cv32e40p_full_covg_no_pulp.yaml +++ b/cv32e40p/regress/cv32e40p_full_covg_no_pulp.yaml @@ -283,8 +283,8 @@ tests: build: uvmt_cv32e40p description: Debug test target debug_req at BOOT_SET dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set - num: 50 + cmd: make test COREV=YES TEST=debug_test_boot_set SEED=1 VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + num: 1 interrupt_bootstrap: build: uvmt_cv32e40p diff --git a/cv32e40p/regress/cv32e40pv2_ci_check.yaml b/cv32e40p/regress/cv32e40pv2_ci_check.yaml index 04227a5d4c..d06a3289a9 100644 --- a/cv32e40p/regress/cv32e40pv2_ci_check.yaml +++ b/cv32e40p/regress/cv32e40pv2_ci_check.yaml @@ -48,40 +48,40 @@ builds: cfg: pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - uvmt_cv32e40p_pulp_cluster: - cmd: make comp comp_corev-dv - cfg: pulp_cluster - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_1cyclat: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_1cyclat - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_2cyclat: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_2cyclat - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_zfinx - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx_1cyclat: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_zfinx_1cyclat - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx_2cyclat: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_zfinx_2cyclat - dir: cv32e40p/sim/uvmt +# uvmt_cv32e40p_pulp_cluster: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_1cyclat: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_1cyclat +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_2cyclat: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_2cyclat +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_zfinx: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_zfinx +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_zfinx_1cyclat: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_zfinx_1cyclat +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_zfinx_2cyclat: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_zfinx_2cyclat +# dir: cv32e40p/sim/uvmt tests: hello-world: @@ -95,13 +95,6 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat - - uvmt_cv32e40p_pulp_cluster - - uvmt_cv32e40p_pulp_cluster_fpu - - uvmt_cv32e40p_pulp_cluster_fpu_1cyclat - - uvmt_cv32e40p_pulp_cluster_fpu_2cyclat - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx_1cyclat - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx_2cyclat description: UVM Hello World Test dir: cv32e40p/sim/uvmt cmd: make test COREV=YES TEST=hello-world CFG_PLUSARGS="+UVM_TIMEOUT=1000000" @@ -111,13 +104,13 @@ tests: build: uvmt_cv32e40p_pulp_fpu description: Interrupt directed on PULP+FPU HW dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + cmd: make test COREV=YES TEST=interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 debug_test: build: uvmt_cv32e40p_pulp_fpu dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + cmd: make test COREV=YES TEST=debug_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 corev_rand_fp_instr_sanity_test: @@ -147,4 +140,4 @@ tests: corev_rand_pulp_hwloop_test: build: uvmt_cv32e40p_pulp dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" diff --git a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml index 29971116e8..5c385a26dd 100644 --- a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml @@ -34,11 +34,6 @@ tests: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_sanity_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" - num: 1 - skip_sim: - - pulp_fpu_zfinx - - pulp_fpu_zfinx_1cyclat - - pulp_fpu_zfinx_2cyclat corev_rand_fp_instr_test: build: uvmt_cv32e40p @@ -50,6 +45,12 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_w_special_ops_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + corev_fp_mstatus_fs_test: + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_fp_mstatus_fs_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + num: 1 + fpu_bugs_test: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index 4b1eee87a1..576ec53a3f 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -95,7 +95,7 @@ tests: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=15000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000" num: 1 debug_test: @@ -109,7 +109,8 @@ tests: build: uvmt_cv32e40p description: debug_test_boot_set (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + seed: 1 num: 1 debug_test_known_miscompares: @@ -186,6 +187,8 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" test_cfg: gen_rand_int +# list of corev_rand_pulp_hwloop_debug - START + corev_rand_pulp_hwloop_debug: build: uvmt_cv32e40p description: hwloop debug random test @@ -259,7 +262,92 @@ tests: test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en num: 1 - corev_rand_pulp_hwloop_interrupt_test: +# list of corev_rand_pulp_hwloop_debug - END + +# list of corev_directed_pulp_hwloop_debug - START + + corev_directed_pulp_hwloop_debug: + build: uvmt_cv32e40p + description: hwloop debug random test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + num: 1 + + corev_directed_pulp_hwloop_debug_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop ebreak debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop single-step debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_single_step_en + num: 1 + + corev_directed_pulp_hwloop_debug_trigger: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger on instr addr match + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_trigger_basic + num: 1 + + corev_directed_pulp_hwloop_debug_trigger_with_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_trigger_basic,debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_trigger_with_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_trigger_basic,debug_single_step_en + num: 1 + + corev_directed_pulp_hwloop_debug_with_interrupt: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt and debug trigger random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int,debug_trigger_basic + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and single step random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + num: 1 + +# list of corev_directed_pulp_hwloop_debug - END + + corev_rand_pulp_hwloop_test_interrupt: testname: corev_rand_pulp_hwloop_test description: hwloop test with random interrupts build: uvmt_cv32e40p @@ -267,6 +355,15 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: gen_rand_int + corev_directed_pulp_hwloop_test_with_interrupt: + testname: corev_directed_pulp_hwloop_test + description: hwloop test with random interrupts + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int + num: 1 + corev_rand_pulp_hwloop_exception_single_step_debug: testname: corev_rand_pulp_hwloop_exception description: hwloop exception test with single step debug @@ -291,4 +388,3 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" test_cfg: gen_rand_int,debug_trigger_basic - diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml index e401209091..abacae938b 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml @@ -85,7 +85,9 @@ tests: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=15000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000" + +# list of corev_rand_pulp_hwloop_debug - START corev_rand_pulp_hwloop_debug_single_step: testname: corev_rand_pulp_hwloop_debug @@ -103,6 +105,14 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic,debug_single_step_en + corev_rand_pulp_hwloop_debug_with_int_debug_trigger_and_ebreak: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and ebreak random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak + corev_rand_pulp_hwloop_debug_with_int_debug_trigger_single_step: testname: corev_rand_pulp_hwloop_debug description: hwloop debug with interrupt, debug trigger and single step random test @@ -111,6 +121,48 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en +# list of corev_rand_pulp_hwloop_debug - END + +# list of corev_directed_pulp_hwloop_debug - START + + corev_directed_pulp_hwloop_debug_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop single-step debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_single_step_en + num: 1 + + corev_directed_pulp_hwloop_debug_trigger_with_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_trigger_basic,debug_single_step_en + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger_and_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and ebreak random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and single step random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + num: 1 + +# list of corev_directed_pulp_hwloop_debug - END + corev_rand_pulp_hwloop_exception_single_step_debug: testname: corev_rand_pulp_hwloop_exception description: hwloop exception test with single step debug @@ -119,3 +171,11 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_single_step_en + corev_rand_pulp_hwloop_exception_with_int_debug_trigger: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + test_cfg: gen_rand_int,debug_trigger_basic + diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 215d5c1d3a..e2a074e6d9 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -21,30 +21,78 @@ builds: # List of tests tests: - corev_rand_pulp_instr_ebreak_debug_test: + corev_rand_pulp_instr_random_debug_test: testname: corev_rand_pulp_instr_test - description: pulp rand test with ebreak debug + description: pulp instr test with random debug halt req build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_debug_req + + corev_rand_pulp_instr_ebreak_debug_test: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with ebreak debug + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_ebreak corev_rand_pulp_instr_single_step_debug_test: - testname: corev_rand_pulp_instr_test + testname: corev_rand_pulp_instr_debug description: pulp rand test with single-step debug build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_single_step_en corev_rand_pulp_instr_debug_trigger_test: - testname: corev_rand_pulp_instr_test + testname: corev_rand_pulp_instr_debug description: pulp rand test with debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_trigger_basic + corev_rand_pulp_instr_debug_trigger_with_ebreak: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with debug trigger and ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_ebreak + + corev_rand_pulp_instr_debug_trigger_with_single_step: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_single_step_en + + corev_rand_pulp_instr_debug_trigger_with_random_debug_req: + testname: corev_rand_pulp_instr_test + description: pulp rand test with debug trigger and random debug req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,gen_rand_debug_req + + corev_rand_pulp_instr_debug_ebreak_with_random_debug_req: + testname: corev_rand_pulp_instr_test + description: pulp rand test with debug ebreak and random debug req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_ebreak,gen_rand_debug_req + + corev_rand_pulp_instr_debug_single_step_with_random_debug_req: + testname: corev_rand_pulp_instr_test + description: pulp rand test with debug ebreak and random debug req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_single_step_en,gen_rand_debug_req + corev_rand_pulp_instr_interrupt_test: testname: corev_rand_pulp_instr_test description: pulp instr test with random interrupts @@ -53,18 +101,127 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: gen_rand_int + corev_rand_pulp_instr_interrupt_debug_test: + testname: corev_rand_pulp_instr_test + description: pulp instr test with random interrupts and debug halt req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,gen_rand_debug_req + + corev_rand_pulp_instr_debug_test_with_int_and_debug_trigger: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic + + corev_rand_pulp_instr_debug_test_with_int_and_debug_single_step: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_single_step_en + + corev_rand_pulp_instr_debug_test_with_int_and_debug_ebreak: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt and debug ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_ebreak + + corev_rand_pulp_instr_debug_test_with_int_debug_trigger_and_ebreak: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt, debug trigger and debug ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak + + corev_rand_pulp_instr_debug_test_with_int_debug_trigger_and_single_step: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt, debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + +# Add corev_rand_fp_instr_debug similar to corev_rand_pulp_instr_debug/test with f/zfinx insn included - START + + corev_rand_fp_instr_debug_test_with_int_and_debug: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int + skip_sim: pulp + + corev_rand_fp_instr_debug_test_with_int_and_debug_trigger: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic + skip_sim: pulp + + corev_rand_fp_instr_debug_test_with_int_and_debug_single_step: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_single_step_en + skip_sim: pulp + +# note: current fp streams excluding ebreak insn +# corev_rand_fp_instr_debug_test_with_int_and_debug_ebreak: +# testname: corev_rand_fp_instr_debug +# description: pulp instr random test with random interrupt and debug ebreak +# build: uvmt_cv32e40p +# dir: cv32e40p/sim/uvmt +# cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" +# test_cfg: gen_rand_int,debug_ebreak +# skip_sim: pulp +# +# corev_rand_fp_instr_debug_test_with_int_debug_trigger_and_ebreak: +# testname: corev_rand_fp_instr_debug +# description: pulp instr random test with random interrupt, debug trigger and debug ebreak +# build: uvmt_cv32e40p +# dir: cv32e40p/sim/uvmt +# cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" +# test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak +# skip_sim: pulp + + corev_rand_fp_instr_debug_test_with_int_debug_trigger_and_single_step: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt, debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + skip_sim: pulp + +# Add corev_rand_fp_instr_debug similar to corev_rand_pulp_instr_debug with f/zfinx insn included - END + +# list of corev_rand_pulp_hwloop_debug - START + corev_rand_pulp_hwloop_debug: build: uvmt_cv32e40p description: hwloop debug random test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_pulp_hwloop_debug_ebreak: testname: corev_rand_pulp_hwloop_debug description: hwloop ebreak debug random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_ebreak corev_rand_pulp_hwloop_debug_trigger: @@ -72,7 +229,7 @@ tests: description: hwloop debug random test with debug trigger on instr addr match build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic corev_rand_pulp_hwloop_debug_trigger_with_ebreak: @@ -80,7 +237,7 @@ tests: description: hwloop debug random test with debug trigger and ebreak build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic,debug_ebreak corev_rand_pulp_hwloop_debug_with_interrupt: @@ -88,7 +245,7 @@ tests: description: hwloop debug with interrupt random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int corev_rand_pulp_hwloop_debug_with_int_debug_trigger: @@ -96,32 +253,133 @@ tests: description: hwloop debug with interrupt and debug trigger random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic + + corev_rand_pulp_hwloop_debug_with_int_debug_ebreak: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt and debug ebreak random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_ebreak + +# list of corev_rand_pulp_hwloop_debug - END + +# list of corev_directed_pulp_hwloop_debug - START + + corev_directed_pulp_hwloop_debug: + build: uvmt_cv32e40p + description: hwloop debug random test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + num: 1 + + corev_directed_pulp_hwloop_debug_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop ebreak debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_trigger: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger on instr addr match + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_trigger_basic + num: 1 + + corev_directed_pulp_hwloop_debug_trigger_with_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_trigger_basic,debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_with_interrupt: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt and debug trigger random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_trigger_basic + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt and debug ebreak random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_ebreak + num: 1 + +# list of corev_directed_pulp_hwloop_debug - END + +# list of corev_rand_pulp_hwloop_test - START + + corev_rand_pulp_hwloop_test_with_random_debug: + testname: corev_rand_pulp_hwloop_test + description: hwloop random debug req test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_debug_req corev_rand_pulp_hwloop_interrupt_test: testname: corev_rand_pulp_hwloop_test description: hwloop test with random interrupts build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int - corev_rand_pulp_hwloop_exception_debug_trigger: - testname: corev_rand_pulp_hwloop_exception - description: hwloop exception test with debug trigger +# list of corev_rand_pulp_hwloop_test - END + +# list of corev_directed_pulp_hwloop_test - START + + corev_directed_pulp_hwloop_test_with_random_debug: + testname: corev_directed_pulp_hwloop_test + description: hwloop random debug req test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: debug_trigger_basic + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_debug_req + num: 1 - corev_rand_pulp_hwloop_exception_with_int_debug_trigger: + corev_directed_pulp_hwloop_test_with_interrupt: + testname: corev_directed_pulp_hwloop_test + description: hwloop test with random interrupts + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int + num: 1 + +# list of corev_directed_pulp_hwloop_test - END + + corev_rand_pulp_hwloop_exception_debug_trigger: testname: corev_rand_pulp_hwloop_exception - description: hwloop exception test with interrupt and debug trigger + description: hwloop exception test with debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: gen_rand_int,debug_trigger_basic + test_cfg: debug_trigger_basic,gen_limit_debug_req debug_test: build: uvmt_cv32e40p @@ -134,7 +392,8 @@ tests: build: uvmt_cv32e40p description: debug_test_boot_set (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + seed: 1 num: 1 debug_test_known_miscompares: diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index 9212df1ff1..e98dd04993 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -28,7 +28,7 @@ tests: build: uvmt_cv32e40p description: corev_rand_pulp_hwloop_test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_pulp_instr_test: build: uvmt_cv32e40p @@ -52,7 +52,7 @@ tests: build: uvmt_cv32e40p description: hwloop exception test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=15000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_pulp_illegal_instr_test: testname: corev_rand_pulp_instr_test @@ -84,6 +84,14 @@ tests: cmd: make test COREV=YES TEST=pulp_hardware_loop_interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 + custom_opcode_illegal_test: + build: uvmt_cv32e40p + description: custom_opcode_illegal_test directed test, for illegal instructions inside custom-[0-3] opcodes + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=custom_opcode_illegal_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + num: 1 + + # pulp_hardware_loop_debug_test: # build: uvmt_cv32e40p # description: pulp_hardware_loop directed test diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index e4f22c4d8b..ed088f9f11 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= 1d0ec8d83091bda8e65c36c48614a41065f5fc10 +CV_CORE_HASH ?= head CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. diff --git a/cv32e40p/tb/uvmt/imperas_dv.flist b/cv32e40p/tb/uvmt/imperas_dv.flist index 735e764513..ea7f2cd08c 100644 --- a/cv32e40p/tb/uvmt/imperas_dv.flist +++ b/cv32e40p/tb/uvmt/imperas_dv.flist @@ -25,7 +25,7 @@ +incdir+${IMPERAS_HOME}/ImpProprietary/include/host +incdir+${IMPERAS_HOME}/ImpProprietary/source/host/CV32E40Pv2_riscvISACOV/source -//${TBSRC_HOME}/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh +${TBSRC_HOME}/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh -f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f -f ${IMPERAS_HOME}/ImpProprietary/source/host/idv/idv.f diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv index 77c95dafc6..555c64f53b 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv @@ -39,6 +39,7 @@ module uvmt_cv32e40p_debug_assert logic exception_addr_at_entry_flag; logic [31:0] tdata2_at_entry; // Locally track which debug cause should be used + logic is_decoding_v1; logic [2:0] debug_cause_pri; logic [31:0] boot_addr_at_entry; @@ -51,21 +52,29 @@ module uvmt_cv32e40p_debug_assert // Clocking blocks // --------------------------------------------------------------------------- + assign is_decoding_v1 = cov_assert_if.is_decoding || + (((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE && !cov_assert_if.branch_taken_ex_i && + !cov_assert_if.data_err_i && !cov_assert_if.is_fetch_failed_i) || + cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP + ) && cov_assert_if.id_stage_instr_valid_i && + (cov_assert_if.debug_req_i || cov_assert_if.trigger_match_i) && !cov_assert_if.debug_mode_q + ); + // Single clock, single reset design, use default clocking default clocking @(posedge cov_assert_if.clk_i); endclocking default disable iff !(cov_assert_if.rst_ni); - assign cov_assert_if.is_ebreak = cov_assert_if.is_decoding & + assign cov_assert_if.is_ebreak = is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i & (cov_assert_if.id_stage_instr_rdata_i == 32'h00100073) & cov_assert_if.id_stage_is_compressed == 1'b0; - assign cov_assert_if.is_cebreak = cov_assert_if.is_decoding & + assign cov_assert_if.is_cebreak = is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i & (cov_assert_if.id_stage_instr_rdata_i == 32'h00100073) & cov_assert_if.id_stage_is_compressed == 1'b1; - assign cov_assert_if.is_mulhsu = cov_assert_if.is_decoding & + assign cov_assert_if.is_mulhsu = is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i & cov_assert_if.id_stage_instr_rdata_i[31:25] == 7'h1 & cov_assert_if.id_stage_instr_rdata_i[14:12] == 3'b010 & @@ -131,7 +140,7 @@ module uvmt_cv32e40p_debug_assert // Exclude single stepping as the sequence gets very complicated property p_cebreak_exception; disable iff(cov_assert_if.debug_req_i | !cov_assert_if.rst_ni) - $rose(cov_assert_if.is_cebreak) && cov_assert_if.dcsr_q[15] == 1'b0 && !cov_assert_if.debug_mode_q && cov_assert_if.is_decoding && cov_assert_if.id_valid && + $rose(cov_assert_if.is_cebreak) && cov_assert_if.dcsr_q[15] == 1'b0 && !cov_assert_if.debug_mode_q && is_decoding_v1 && cov_assert_if.id_valid && !cov_assert_if.debug_req_i && !cov_assert_if.dcsr_q[2] |-> (decode_valid) [->1:2] ##0 !cov_assert_if.debug_mode_q && (cov_assert_if.mcause_q[5:0] === cv32e40p_pkg::EXC_CAUSE_BREAKPOINT) && (cov_assert_if.mepc_q == pc_at_ebreak) && @@ -146,7 +155,7 @@ module uvmt_cv32e40p_debug_assert // Exclude single stepping as the sequence gets very complicated property p_ebreak_exception; disable iff(cov_assert_if.debug_req_i | !cov_assert_if.rst_ni) - $rose(cov_assert_if.is_ebreak) && cov_assert_if.dcsr_q[15] == 1'b0 && !cov_assert_if.debug_mode_q && cov_assert_if.is_decoding && cov_assert_if.id_valid && + $rose(cov_assert_if.is_ebreak) && cov_assert_if.dcsr_q[15] == 1'b0 && !cov_assert_if.debug_mode_q && is_decoding_v1 && cov_assert_if.id_valid && !cov_assert_if.debug_req_i && !cov_assert_if.dcsr_q[2] |-> (decode_valid) [->1:2] ##0 !cov_assert_if.debug_mode_q && (cov_assert_if.mcause_q[5:0] === cv32e40p_pkg::EXC_CAUSE_BREAKPOINT) && (cov_assert_if.mepc_q == pc_at_ebreak) && @@ -180,7 +189,7 @@ module uvmt_cv32e40p_debug_assert // Trigger match results in debug mode property p_trigger_match; - cov_assert_if.trigger_match_i ##0 cov_assert_if.tdata1[2] ##0 !cov_assert_if.debug_mode_q ##0 cov_assert_if.id_stage_instr_valid_i + cov_assert_if.trigger_match_i ##0 cov_assert_if.tdata1[2] ##0 !cov_assert_if.debug_mode_q ##0 cov_assert_if.id_stage_instr_valid_i ##0 is_decoding_v1 |-> decode_valid [->2] ##0 (cov_assert_if.debug_mode_q && (cov_assert_if.dcsr_q[8:6]=== cv32e40p_pkg::DBG_CAUSE_TRIGGER) && (cov_assert_if.depc_q == tdata2_at_entry)) && (cov_assert_if.id_stage_pc == halt_addr_at_entry); @@ -201,7 +210,7 @@ module uvmt_cv32e40p_debug_assert // Exception in debug mode results in pc->dm_exception_addr_i property p_debug_mode_exception; - $rose(cov_assert_if.illegal_insn_i) && cov_assert_if.debug_mode_q && cov_assert_if.is_decoding |-> (decode_valid & cov_assert_if.id_valid) [->2] ##0 cov_assert_if.debug_mode_q && (cov_assert_if.id_stage_pc == exception_addr_at_entry); + $rose(cov_assert_if.illegal_insn_i) && cov_assert_if.debug_mode_q && is_decoding_v1 |-> (decode_valid & cov_assert_if.id_valid) [->2] ##0 cov_assert_if.debug_mode_q && (cov_assert_if.id_stage_pc == exception_addr_at_entry); endproperty a_debug_mode_exception : assert property(p_debug_mode_exception) @@ -210,7 +219,7 @@ module uvmt_cv32e40p_debug_assert // ECALL in debug mode results in pc->dm_exception_addr_i property p_debug_mode_ecall; - $rose(cov_assert_if.ecall_insn_i) && cov_assert_if.debug_mode_q && cov_assert_if.is_decoding && cov_assert_if.id_stage_instr_valid_i + $rose(cov_assert_if.ecall_insn_i) && cov_assert_if.debug_mode_q && is_decoding_v1 && cov_assert_if.id_stage_instr_valid_i |-> (decode_valid & cov_assert_if.id_valid) [->1:3] ##0 cov_assert_if.debug_mode_q && (cov_assert_if.id_stage_pc == exception_addr_at_entry); endproperty @@ -422,7 +431,7 @@ module uvmt_cv32e40p_debug_assert else begin // Enter wfi if we have a valid instruction, not in debug mode and not // single stepping - if (cov_assert_if.is_wfi && !cov_assert_if.debug_mode_q && cov_assert_if.is_decoding && cov_assert_if.id_stage_instr_valid_i & !cov_assert_if.dcsr_q[2]) begin + if (cov_assert_if.is_wfi && !cov_assert_if.debug_mode_q && is_decoding_v1 && cov_assert_if.id_stage_instr_valid_i & !cov_assert_if.dcsr_q[2]) begin cov_assert_if.in_wfi <= 1'b1; end else if (cov_assert_if.pending_enabled_irq || cov_assert_if.debug_req_i) @@ -463,7 +472,7 @@ module uvmt_cv32e40p_debug_assert assign cov_assert_if.is_wfi = cov_assert_if.id_stage_instr_valid_i & cov_assert_if.id_valid & ((cov_assert_if.id_stage_instr_rdata_i & WFI_INSTR_MASK) == WFI_INSTR_DATA); assign cov_assert_if.pending_enabled_irq = |(cov_assert_if.irq_i & cov_assert_if.mie_q); - assign cov_assert_if.is_dret = cov_assert_if.id_valid & cov_assert_if.id_stage_instr_valid_i & cov_assert_if.is_decoding & (cov_assert_if.id_stage_instr_rdata_i == 32'h7B200073); + assign cov_assert_if.is_dret = cov_assert_if.id_valid & cov_assert_if.id_stage_instr_valid_i & is_decoding_v1 & (cov_assert_if.id_stage_instr_rdata_i == 32'h7B200073); // Track which debug cause should be expected always@ (posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin @@ -471,17 +480,18 @@ module uvmt_cv32e40p_debug_assert debug_cause_pri <= 3'b000; end else begin // Debug evaluated in decode state with valid instructions only - if((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE || cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP) & !cov_assert_if.debug_mode_q) begin - if(cov_assert_if.id_stage_instr_valid_i) begin + //if(cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE & !cov_assert_if.debug_mode_q) begin + if((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE || cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP)) begin + if(is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i) begin if(cov_assert_if.trigger_match_i) debug_cause_pri <= 3'b010; - else if(cov_assert_if.is_decoding & (cov_assert_if.dcsr_q[15]) & (cov_assert_if.is_ebreak | cov_assert_if.is_cebreak)) + else if((cov_assert_if.dcsr_q[15]) & (cov_assert_if.is_ebreak | cov_assert_if.is_cebreak)) debug_cause_pri <= 3'b001; else if(cov_assert_if.debug_req_i) debug_cause_pri <= 3'b011; - else if(cov_assert_if.is_decoding & cov_assert_if.dcsr_q[2]) + else if(cov_assert_if.dcsr_q[2]) debug_cause_pri <= 3'b100; - else if(cov_assert_if.is_decoding) + else debug_cause_pri <= 3'b000; end @@ -507,7 +517,7 @@ module uvmt_cv32e40p_debug_assert first_debug_ins <= 1'b0; if(cov_assert_if.debug_mode_q) begin if(!first_debug_ins_flag) begin - if(cov_assert_if.is_decoding & cov_assert_if.id_stage_instr_valid_i) begin + if(is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i) begin first_debug_ins_flag <= 1'b1; first_debug_ins <= 1'b1; end diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh index b82a2c2ddd..af76cecb24 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh @@ -6,11 +6,11 @@ `define IDV_INCLUDE_TRACE2COV `define COVER_BASE_RV32I `define COVER_LEVEL_COMPL_BAS - `define COVER_LEVEL_COMPL_EXT - `define COVER_LEVEL_DV_UP_BAS - `define COVER_LEVEL_DV_UP_EXT - `define COVER_LEVEL_DV_PR_BAS - `define COVER_LEVEL_DV_PR_EXT + //`define COVER_LEVEL_COMPL_EXT + // `define COVER_LEVEL_DV_UP_BAS // fixme: this is needed for some f/zfinx cp + //`define COVER_LEVEL_DV_UP_EXT + //`define COVER_LEVEL_DV_PR_BAS + //`define COVER_LEVEL_DV_PR_EXT `define COVER_RV32I `define COVER_RV32M `define COVER_RV32C diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index e52641cc31..16c8fd73ae 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -441,6 +441,9 @@ module uvmt_cv32e40p_tb; .id_stage_is_compressed(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.is_compressed_i), .id_valid(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.id_valid_i), .is_decoding(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.is_decoding_o), + .branch_taken_ex_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.branch_taken_ex_i), + .data_err_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.data_err_i), + .is_fetch_failed_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.is_fetch_failed_i), .id_stage_pc(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.pc_id_i), .if_stage_pc(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.pc_if_o), .mie_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mie_q), @@ -504,6 +507,41 @@ module uvmt_cv32e40p_tb; .pending_enabled_irq() ); + //Interface for coverage components + uvmt_cv32e40p_cov_if cov_if( + .clk_i(clknrst_if.clk), + .rst_ni(clknrst_if.reset_n), + .if_stage_instr_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.instr_rvalid_i), + .if_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.instr_rdata_i), + .id_stage_instr_valid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.instr_valid_i), + .id_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.instr_rdata_i), + .apu_req(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_req_o), + .apu_gnt(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_gnt_i), + .apu_busy(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_busy_i), + .apu_op(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_op_o), + .apu_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_rvalid_i), + .apu_perf_wb_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_perf_wb_o), + .id_stage_apu_op_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_op_ex_o), + .id_stage_apu_en_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_en_ex_o), + .regfile_waddr_wb_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_waddr_wb_o), + .regfile_we_wb_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_we_wb_o), + .regfile_alu_waddr_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_waddr_fw_o), + .regfile_alu_we_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_we_fw_o), + .ex_mulh_active(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.mulh_active), + .ex_mult_op_ex(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.mult_operator_i), + .ex_data_misaligned_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_misaligned_i), + .ex_data_misaligned_ex_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_misaligned_ex_i), + .ex_data_req_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_req_i), + .ex_data_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_rvalid_i), + .ex_regfile_alu_we_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_we_i), + .ex_apu_valid(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_valid), + .ex_apu_rvalid_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_rvalid_q), + .debug_req_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.debug_req_pending), + .debug_mode_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.debug_mode_q), + .dcsr_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.dcsr_q), + .trigger_match_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.trigger_match_i) + ); + // Instantiate debug assertions uvmt_cv32e40p_debug_assert u_debug_assert(.cov_assert_if(debug_cov_assert_if)); @@ -517,13 +555,16 @@ module uvmt_cv32e40p_tb; .pc_rdata (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_pc_rdata), .interrupt_if (interrupt_if), .debug_if (debug_if), + .wa_csr_mip (dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mip), `PORTMAP_CSR_RVFI_2_RVVI(lpstart0) `PORTMAP_CSR_RVFI_2_RVVI(lpend0) `PORTMAP_CSR_RVFI_2_RVVI(lpcount0) `PORTMAP_CSR_RVFI_2_RVVI(lpstart1) `PORTMAP_CSR_RVFI_2_RVVI(lpend1) `PORTMAP_CSR_RVFI_2_RVVI(lpcount1) + `PORTMAP_CSR_RVFI_2_RVVI(mstatus) `PORTMAP_CSR_RVFI_2_RVVI(mie) + `PORTMAP_CSR_RVFI_2_RVVI(mtvec) `PORTMAP_CSR_RVFI_2_RVVI(mcause) `PORTMAP_CSR_RVFI_2_RVVI(mip) `PORTMAP_CSR_RVFI_2_RVVI(dcsr) @@ -601,6 +642,7 @@ module uvmt_cv32e40p_tb; uvm_config_db#(virtual uvmt_cv32e40p_debug_cov_assert_if)::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_cov_vif"), .value(debug_cov_assert_if) ); uvm_config_db#(virtual uvmt_cv32e40p_isa_covg_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("isa_covg_vif"), .value(isa_covg_if) ); uvm_config_db#(virtual uvma_debug_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_vif"), .value(debug_if) ); + uvm_config_db#(virtual uvmt_cv32e40p_cov_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("cov_vif"), .value(cov_if) ); `RVFI_CSR_UVM_CONFIG_DB_SET(fflags) `RVFI_CSR_UVM_CONFIG_DB_SET(frm) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 06ed86a768..e9261b4c70 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -207,6 +207,9 @@ interface uvmt_cv32e40p_debug_cov_assert_if input [31:0] id_stage_pc, // Program counter in decode input [31:0] if_stage_pc, // Program counter in fetch input is_decoding, + input branch_taken_ex_i, + input data_err_i, + input is_fetch_failed_i, input id_valid, input wire ctrl_state_e ctrl_fsm_cs, // Controller FSM states with debug_req input illegal_insn_i, @@ -283,6 +286,10 @@ interface uvmt_cv32e40p_debug_cov_assert_if id_stage_is_compressed, id_stage_pc, if_stage_pc, + is_decoding, + branch_taken_ex_i, + is_fetch_failed_i, + id_valid, ctrl_fsm_cs, illegal_insn_i, illegal_insn_q, @@ -390,6 +397,7 @@ interface uvmt_cv32e40p_rvvi_if #( input logic [(ILEN-1):0] insn, input trap, input logic [31:0] pc_rdata, + input logic [31:0] wa_csr_mip, uvma_interrupt_if interrupt_if, uvma_debug_if debug_if, @@ -401,7 +409,9 @@ interface uvmt_cv32e40p_rvvi_if #( `DEF_CSR_PORTS(lpstart1) `DEF_CSR_PORTS(lpend1) `DEF_CSR_PORTS(lpcount1) + `DEF_CSR_PORTS(mstatus) `DEF_CSR_PORTS(mie) + `DEF_CSR_PORTS(mtvec) `DEF_CSR_PORTS(mcause) `DEF_CSR_PORTS(mip) `DEF_CSR_PORTS(dcsr) @@ -419,9 +429,14 @@ interface uvmt_cv32e40p_rvvi_if #( wire [31:0] csr_trig_pc; logic [31:0] irq_onehot_priority; + logic [31:0] mtvec_base_addr; + logic [31:0] mip; - assign valid_irq = csr[`CSR_MIP_ADDR] & csr[`CSR_MIE_ADDR]; // fixme: rvfi misses mip (pending for resolution) + // assign valid_irq = csr[`CSR_MIP_ADDR] & csr[`CSR_MIE_ADDR]; // fixme: rvfi misses mip (pending rvfi fixes; workaround probe rtl signals - wa_csr_mip) + assign valid_irq = wa_csr_mip & csr[`CSR_MIE_ADDR]; assign dbg_req = debug_if.debug_req; + assign mie = csr[`CSR_MSTATUS_ADDR][3]; + assign mip = csr[`CSR_MIP_ADDR]; assign csr_mcause_irq = csr[`CSR_MCAUSE_ADDR][31]; assign csr_mcause_ecp_code = csr[`CSR_MCAUSE_ADDR][4:0]; @@ -432,6 +447,8 @@ interface uvmt_cv32e40p_rvvi_if #( assign csr_trig_execute = csr[`CSR_TDATA1_ADDR][2]; assign csr_trig_pc = csr[`CSR_TDATA2_ADDR]; + assign mtvec_base_addr = {csr[`CSR_MTVEC_ADDR][31:8], 8'h0}; + // can be expanded. Currently only define for current usage `ASSIGN_CSR_N_WB(`CSR_LPSTART0_ADDR, lpstart0) `ASSIGN_CSR_N_WB(`CSR_LPEND0_ADDR, lpend0) @@ -439,14 +456,16 @@ interface uvmt_cv32e40p_rvvi_if #( `ASSIGN_CSR_N_WB(`CSR_LPSTART1_ADDR, lpstart1) `ASSIGN_CSR_N_WB(`CSR_LPEND1_ADDR, lpend1) `ASSIGN_CSR_N_WB(`CSR_LPCOUNT1_ADDR, lpcount1) + `ASSIGN_CSR_N_WB(`CSR_MSTATUS_ADDR, mstatus) `ASSIGN_CSR_N_WB(`CSR_MIE_ADDR, mie) + `ASSIGN_CSR_N_WB(`CSR_MTVEC_ADDR, mtvec) `ASSIGN_CSR_N_WB(`CSR_MCAUSE_ADDR, mcause) `ASSIGN_CSR_N_WB(`CSR_MIP_ADDR, mip) `ASSIGN_CSR_N_WB(`CSR_DCSR_ADDR, dcsr) `ASSIGN_CSR_N_WB_VEC(`CSR_TDATA1_ADDR, tdata, 1); `ASSIGN_CSR_N_WB_VEC(`CSR_TDATA2_ADDR, tdata, 2); - // irq_onehot_priority assignment + // irq_onehot_priority assignment (refer cv32e40p user manual, section 10.2) // priority order (high->low) is irq[31]...irq[16], irq[11], irq[3], irq[7] always @(valid_irq) begin irq_onehot_priority = 0; @@ -460,4 +479,252 @@ interface uvmt_cv32e40p_rvvi_if #( endinterface +// +//Interface for custom TB coverage component +// +interface uvmt_cv32e40p_cov_if + + import uvm_pkg::*; + import uvme_cv32e40p_pkg::*; + ( + input clk_i, + input rst_ni, + input if_stage_instr_rvalid_i, + input [31:0] if_stage_instr_rdata_i, + input id_stage_instr_valid_i, + input [31:0] id_stage_instr_rdata_i, + input apu_req, + input apu_gnt, + input apu_busy, + input [5:0] apu_op, + input apu_rvalid_i, + input apu_perf_wb_o, + input [5:0] id_stage_apu_op_ex_o, + input id_stage_apu_en_ex_o, + input [5:0] regfile_waddr_wb_o, // regfile write port A addr from WB stage + input regfile_we_wb_o, + input [5:0] regfile_alu_waddr_ex_o, // regfile write port B addr from EX stage + input regfile_alu_we_ex_o, + input ex_mulh_active, + input [2:0] ex_mult_op_ex, + input ex_data_misaligned_i, + input ex_data_misaligned_ex_i, + input ex_data_req_i, + input ex_data_rvalid_i, + input ex_regfile_alu_we_i, + input ex_apu_valid, + input ex_apu_rvalid_q, + input debug_req_i, + input debug_mode_q, + input [31:0] dcsr_q, + input trigger_match_i, + + output logic[5:0] o_curr_fpu_apu_op_if, + output logic[5:0] o_last_fpu_apu_op_if, + output logic[4:0] if_clk_cycle_window, + output [4:0] curr_fpu_fd, + output [4:0] curr_fpu_rd, + output [5:0] curr_rd_at_ex_regfile_wr_contention, + output [5:0] curr_rd_at_wb_regfile_wr_contention, + output [5:0] prev_rd_waddr_contention, + output logic[1:0] contention_state, + output b2b_contention, + output is_mulh_ex, + output is_misaligned_data_req_ex, + output is_post_inc_ld_st_inst_ex, + output ex_apu_valid_memorised + ); + + logic [4:0] clk_cycle_window; + logic [5:0] curr_fpu_apu_op_if; + logic [5:0] last_fpu_contention_op_if; + logic [5:0] prev_regfile_waddr_contention; + logic [4:0] regfile_waddr_wb_fd; + logic [4:0] regfile_alu_waddr_ex_fd; + logic [4:0] regfile_waddr_wb_rd; + logic [4:0] regfile_alu_waddr_ex_rd; + logic [5:0] regfile_waddr_ex_contention; + logic [5:0] regfile_waddr_wb_contention; + logic [1:0] contention_valid; + logic b2b_contention_valid; + + initial begin + clk_cycle_window = 0; + curr_fpu_apu_op_if = 0; + regfile_waddr_wb_fd = 0; + regfile_alu_waddr_ex_fd = 0; + regfile_waddr_wb_rd = 0; + regfile_alu_waddr_ex_rd = 0; + regfile_waddr_ex_contention = 0; + regfile_waddr_wb_contention = 0; + contention_valid = 0; + b2b_contention_valid = 0; + end + + clocking mon_cb @(posedge clk_i); + default input #1step output #1ns; + input if_stage_instr_rvalid_i; + input if_stage_instr_rdata_i; + input id_stage_instr_valid_i; + input id_stage_instr_rdata_i; + input apu_req; + input apu_gnt; + input apu_busy; + input apu_op; + input apu_rvalid_i; + input apu_perf_wb_o; + input id_stage_apu_op_ex_o; + input id_stage_apu_en_ex_o; + input debug_req_i; + input debug_mode_q; + input trigger_match_i; + input dcsr_q; + inout is_mulh_ex; + inout is_misaligned_data_req_ex; + inout is_post_inc_ld_st_inst_ex; + inout ex_apu_valid_memorised; + endclocking : mon_cb + + //calculate each APU operation's current clock cycle number during execution for functional coverage use + always @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + clk_cycle_window = 0; + curr_fpu_apu_op_if = 0; + end + else begin + if((clk_cycle_window == 0) && (apu_req == 1)) begin + clk_cycle_window = 1; + curr_fpu_apu_op_if = apu_op; + end + else if((clk_cycle_window != 0) && (apu_req == 1)) begin + clk_cycle_window = 1; + curr_fpu_apu_op_if = apu_op; + end + else if((clk_cycle_window != 0) && (apu_busy == 1)) begin + clk_cycle_window += 1; + end + else begin + clk_cycle_window = 0; + end + end + end + + //Model APU contention state in EX/WB for functional coverage + always @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + contention_valid <= 0; + b2b_contention_valid <= 0; + last_fpu_contention_op_if <= 0; + prev_regfile_waddr_contention <= 0; + end + else begin + if (((contention_valid == 0) || (contention_valid == 2)) && (apu_perf_wb_o)) begin + contention_valid <= 1; //set contention_valid + b2b_contention_valid <= 0; + `ifndef FPU_LAT_1_CYC + prev_regfile_waddr_contention <= regfile_alu_waddr_ex_o; + `else + prev_regfile_waddr_contention <= regfile_waddr_wb_o; + last_fpu_contention_op_if <= curr_fpu_apu_op_if; + `endif + end + else if((contention_valid == 1) && (apu_perf_wb_o)) begin + contention_valid <= 1; //reset contention_valid + b2b_contention_valid <= 1; + //if no APU execution during contention then nothing to do + //else TODO: check if during contention another APU transaction + //can go through? + `ifndef FPU_LAT_1_CYC + prev_regfile_waddr_contention <= regfile_alu_waddr_ex_o; + `else + prev_regfile_waddr_contention <= regfile_waddr_wb_o; + `endif + end + else if((contention_valid == 1) && (!apu_perf_wb_o)) begin + contention_valid <= 2; //stalled write complete after contention + b2b_contention_valid <= 0; + end + else begin + contention_valid <= 0; + b2b_contention_valid <= 0; + end + end + end + + + //sample each APU operation's destination register address for functional coverage + always @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + regfile_alu_waddr_ex_fd <= 0; + regfile_alu_waddr_ex_rd <= 0; + regfile_waddr_wb_fd <= 0; + regfile_waddr_wb_rd <= 0; + regfile_waddr_wb_contention <= 0; + regfile_waddr_ex_contention <= 0; + end + else begin +`ifndef FPU_LAT_1_CYC //Case for FPU Latency {0,2,3,4}, with regfile write from EX stage with highest priority of APU + if (((apu_req == 1) || (apu_busy == 1)) && (regfile_alu_we_ex_o == 1) && (apu_rvalid_i == 1)) begin + regfile_alu_waddr_ex_fd <= (regfile_alu_waddr_ex_o - 32); + regfile_alu_waddr_ex_rd <= (regfile_alu_waddr_ex_o < 32) ? regfile_alu_waddr_ex_o : 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention <= 0; + end + else if ((contention_valid == 1) && (regfile_alu_we_ex_o == 1) && !apu_perf_wb_o) begin // write for stalled regfile wr at contention + regfile_alu_waddr_ex_fd <= 0; + regfile_alu_waddr_ex_rd <= 0; + regfile_waddr_ex_contention <= regfile_alu_waddr_ex_o; //should not be >31, check for illegal in coverage + regfile_waddr_wb_contention <= 0; + end + `else + //Case FPU Latency = 1; regfile wr from WB;LSU > priority;no LSU contention, F-inst regfile wr succeed + if ((apu_busy == 1) && (regfile_we_wb_o == 1) && (apu_rvalid_i == 1) && (!apu_perf_wb_o)) begin + regfile_waddr_wb_fd <= (regfile_waddr_wb_o - 32); + regfile_waddr_wb_rd <= (regfile_waddr_wb_o < 32) ? regfile_waddr_wb_o : 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention <= 0; + end + //Case FPU Latency = 1; regfile wr from WB;LSU > priority;LSU contention,F-inst regfile wr stall + else if((apu_busy == 1) && (regfile_we_wb_o == 1) && (apu_rvalid_i == 1) && (apu_perf_wb_o)) begin + regfile_waddr_wb_fd <= 0 + regfile_waddr_wb_rd <= 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention = regfile_waddr_wb_o; //should not be >31, check for illegal in coverage + end + //Case FPU Latency = 1;regfile wr from WB;LSU > priority;LSU contention - FPU reg write cycle after contention + else if((contention_valid == 1) && (regfile_we_wb_o == 1) && !apu_perf_wb_o) begin + regfile_waddr_wb_fd <= (regfile_waddr_wb_o - 32); + regfile_waddr_wb_rd <= (regfile_waddr_wb_o < 32) ? regfile_waddr_wb_o : 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention <= 0; + end + `endif + else begin + regfile_alu_waddr_ex_fd <= 0; + regfile_alu_waddr_ex_rd <= 0; + regfile_waddr_wb_fd <= 0; + regfile_waddr_wb_rd <= 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention <= 0; + end + end + end + + assign curr_fpu_fd = regfile_alu_waddr_ex_fd | regfile_waddr_wb_fd; + assign curr_fpu_rd = regfile_alu_waddr_ex_rd | regfile_waddr_wb_rd; + assign if_clk_cycle_window = clk_cycle_window; + assign o_curr_fpu_apu_op_if = curr_fpu_apu_op_if; + assign o_last_fpu_apu_op_if = last_fpu_contention_op_if; + assign curr_rd_at_ex_regfile_wr_contention = regfile_waddr_ex_contention; + assign curr_rd_at_wb_regfile_wr_contention = regfile_waddr_wb_contention; + assign contention_state = contention_valid; + assign b2b_contention = b2b_contention_valid; + assign prev_rd_waddr_contention = prev_regfile_waddr_contention; + assign is_mulh_ex = ex_mulh_active && (ex_mult_op_ex == 3'h6); + assign is_misaligned_data_req_ex = ex_data_misaligned_i || ex_data_misaligned_ex_i; + assign is_post_inc_ld_st_inst_ex = (ex_data_req_i || ex_data_rvalid_i) && ex_regfile_alu_we_i; + assign ex_apu_valid_memorised = ex_apu_valid & ex_apu_rvalid_q; + +endinterface : uvmt_cv32e40p_cov_if + `endif // __UVMT_CV32E40P_TB_IFS_SV__ diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml new file mode 100644 index 0000000000..5aff998588 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml @@ -0,0 +1,31 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for corev-dv test generator +# corev-dv generator test +name: corev_directed_pulp_hwloop_debug +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated directed hwloop tests with random debug +plusargs: > + +instr_cnt=200 + +num_of_sub_program=0 + +insert_rand_directed_instr_stream=1 + +test_rand_directed_instr_stream_num=2 + +rand_directed_instr_0=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +rand_directed_instr_1=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +no_fence=1 + +no_data_page=0 + +randomize_csr=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +no_wfi=1 + +no_dret=1 + +enable_misaligned_instr=1 + +enable_ebreak_in_debug_rom=0 + +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 + +gen_debug_section=1 + +is_hwloop_test=1 + +include_xpulp_instr_in_debug_rom diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/test.yaml new file mode 100644 index 0000000000..148f7eed66 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/test.yaml @@ -0,0 +1,10 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for random hwloop debug test +name: corev_directed_pulp_hwloop_debug +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Random debug in xpulp hwloop stream +plusargs: > + +gen_reduced_rand_dbg_req diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml new file mode 100644 index 0000000000..9589b79c1b --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml @@ -0,0 +1,29 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for corev-dv test generator +# corev-dv generator test +name: corev_directed_pulp_hwloop_test +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated directed hwloop test +plusargs: > + +instr_cnt=1000 + +num_of_sub_program=0 + +insert_rand_directed_instr_stream=1 + +test_rand_directed_instr_stream_num=2 + +rand_directed_instr_0=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +rand_directed_instr_1=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +no_fence=0 + +no_data_page=0 + +randomize_csr=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +no_wfi=1 + +no_ebreak=1 + +no_dret=1 + +enable_misaligned_instr=0 + +set_dcsr_ebreak=0 + +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/test.yaml new file mode 100644 index 0000000000..144234739d --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/test.yaml @@ -0,0 +1,9 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for random pulp hwloop test +name: corev_directed_pulp_hwloop_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + xpulp hwloop stream +plusargs: > diff --git a/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/corev-dv.yaml new file mode 100644 index 0000000000..732c15ba62 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/corev-dv.yaml @@ -0,0 +1,39 @@ +# +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Test definition YAML for corev-dv test generator + +name: corev_fp_mstatus_fs_test +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated to test on mstatus fs +plusargs: > + +instr_cnt=1000 + +num_of_sub_program=0 + +test_override_riscv_instr_stream=1 + +no_branch_jump=1 + +directed_instr_0=cv32e40p_mstatus_fs_stream,1 + +# note: + # 1) example yaml template for fp test with f_extension + # 2) above setting running streams with rand instrs; +directed_instr_=, + # 3) runcmd: make gen_corev-dv test TEST=corev_sanity_fp_instr_test USE_ISS=no CFG=pulp_fpu CFG_PLUSARGS="+UVM_VERBOSITY=UVM_DEBUG" + # 4) [Must have plusarg] enable_floating_point for extension f + # 5) [Must have plusarg] test_override_riscv_instr_stream=1 + # - ==1: is to tune the streams not to overlap with other streams during streams placement + # 6) [recomendation] for single directed_instr_, try not to use apply too many streams else it might lead to placement issue + # 7) [recomendation] no branch/jump for non-directed streams + # 8) Must use together with test_cfg = floating_pt_instr_en OR floating_pt_zfinx_instr_en diff --git a/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/test.yaml new file mode 100644 index 0000000000..36bbf8dd57 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/test.yaml @@ -0,0 +1,22 @@ +# +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Test definition YAML for generated corev arithmetic base test + +name: corev_fp_mstatus_fs_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Math test generated by corev-dv diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml new file mode 100644 index 0000000000..c7c4d3e3b8 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml @@ -0,0 +1,39 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for corev-dv test generator +# corev-dv generator test +name: corev_rand_fp_instr_debug +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated random fp instr with random debug +plusargs: > + +instr_cnt=1000 + +num_of_sub_program=0 + +insert_rand_directed_instr_stream=2 + +test_rand_directed_instr_stream_num=8 + +directed_instr_0=cv32e40p_constraint_mc_fp_instr_stream,2 + +directed_instr_1=cv32e40p_fp_op_fwd_instr_stream,2 + +directed_instr_2=cv32e40p_fp_op_fwd_instr_w_loadstore_stream,2 + +rand_directed_instr_0=riscv_load_store_rand_instr_stream,1 + +rand_directed_instr_1=riscv_load_store_hazard_instr_stream,1 + +rand_directed_instr_2=riscv_multi_page_load_store_instr_stream,1 + +rand_directed_instr_3=riscv_jal_instr,1 + +rand_directed_instr_4=riscv_hazard_instr_stream,1 + +rand_directed_instr_5=cv32e40p_xpulp_simd_stream_test,1 + +rand_directed_instr_6=cv32e40p_xpulp_mac_stream_test,1 + +rand_directed_instr_7=riscv_int_numeric_corner_stream,1 + +no_fence=0 + +hint_instr_ratio=2 + +no_data_page=0 + +randomize_csr=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +no_wfi=1 + +no_dret=1 + +fix_sp=1 + +enable_misaligned_instr=1 + +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 + +gen_debug_section=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml new file mode 100644 index 0000000000..14f38d205a --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml @@ -0,0 +1,10 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for random pulp instr test +name: corev_rand_fp_instr_debug +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Random debug in fp instruction stream +plusargs: > + +gen_reduced_rand_dbg_req diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml index 34b73c2b94..ac245087aa 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml @@ -33,7 +33,7 @@ plusargs: > +directed_instr_5=cv32e40p_constraint_mc_fp_instr_stream,1 +directed_instr_6=cv32e40p_fp_op_fwd_instr_stream,1 +directed_instr_7=cv32e40p_fp_op_fwd_instr_w_loadstore_stream,1 - +directed_instr_8=cv32e40p_mstatus_fs_stream,1 + # +directed_instr_8=cv32e40p_mstatus_fs_stream,1 # note: # 1) example yaml template for fp test with f_extension diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/corev-dv.yaml new file mode 100644 index 0000000000..e3a496e0b0 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/corev-dv.yaml @@ -0,0 +1,39 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for corev-dv test generator +# corev-dv generator test +name: corev_rand_pulp_instr_debug +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated random pulp instr test +plusargs: > + +instr_cnt=2000 + +num_of_sub_program=0 + +insert_rand_directed_instr_stream=1 + +test_rand_directed_instr_stream_num=9 + +directed_instr_0=cv32e40p_xpulp_rand_stream,2 + +directed_instr_1=cv32e40p_xpulp_short_rand_stream,4 + +directed_instr_2=riscv_load_store_rand_instr_stream,1 + +rand_directed_instr_0=riscv_load_store_rand_instr_stream,2 + +rand_directed_instr_1=riscv_mem_region_stress_test,2 + +rand_directed_instr_2=riscv_load_store_hazard_instr_stream,2 + +rand_directed_instr_3=riscv_multi_page_load_store_instr_stream,2 + +rand_directed_instr_4=riscv_jal_instr,2 + +rand_directed_instr_5=riscv_hazard_instr_stream,2 + +rand_directed_instr_6=cv32e40p_xpulp_simd_stream_test,2 + +rand_directed_instr_7=cv32e40p_xpulp_mac_stream_test,2 + +rand_directed_instr_8=riscv_int_numeric_corner_stream,2 + +no_fence=0 + +hint_instr_ratio=2 + +no_data_page=0 + +randomize_csr=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +no_wfi=1 + +no_dret=1 + +fix_sp=1 + +enable_misaligned_instr=1 + +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/test.yaml new file mode 100644 index 0000000000..82e2020742 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/test.yaml @@ -0,0 +1,10 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for random pulp instr test +name: corev_rand_pulp_instr_debug +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Random debug in xpulp instruction stream +plusargs: > + +gen_reduced_rand_dbg_req diff --git a/cv32e40p/tests/programs/custom/coremark/test.yaml b/cv32e40p/tests/programs/custom/coremark/test.yaml index c59b6eadcc..64b6f00651 100644 --- a/cv32e40p/tests/programs/custom/coremark/test.yaml +++ b/cv32e40p/tests/programs/custom/coremark/test.yaml @@ -3,7 +3,8 @@ uvm_test: uvmt_cv32e40p_firmware_test_c default_cflags: > -O3 -mabi=ilp32 - -march=rv32im + -march=$(RISCV_MARCH) + -msave-restore -falign-functions=16 -funroll-all-loops -falign-jumps=4 @@ -14,6 +15,6 @@ default_cflags: > -DPERFORMANCE_RUN=1 -DITERATIONS=30 -DHAS_STDIO=1 -DHAS_PRINTF=1 -DHAS_FLOAT=1 - -DFLAGS_STR=\""-mabi=ilp32 -march=rv32im -O3 -falign-functions=16 -funroll-all-loops -falign-jumps=4 -finline-functions -Wall -pedantic -nostartfiles -static -DPERFORMANCE_RUN=1 -DITERATIONS=30 -DHAS_STDIO=1 -DHAS_PRINTF=1 -DHAS_FLOAT=1"\" + -DFLAGS_STR=\""-O3 -mabi=ilp32 -march=$(RISCV_MARCH) -msave-restore -falign-functions=16 -funroll-all-loops -falign-jumps=4 -finline-functions -Wall -static -pedantic -nostartfiles -DPERFORMANCE_RUN=1 -DITERATIONS=30 -DHAS_STDIO=1 -DHAS_PRINTF=1 -DHAS_FLOAT=1"\" description: > Runs the CoreMark benchmark diff --git a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S new file mode 100644 index 0000000000..3cb4f75898 --- /dev/null +++ b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S @@ -0,0 +1,5154 @@ +# Copyright 2024 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.include "user_define.h" +.section .text.start + +.section .mtvec_bootstrap, "ax" +.globl _mtvec_bootstrap + j mtvec_handler + +.globl _start +.section .init +#.include "user_init.s" +.type _start, @function + +_start: + j _start_main + +.globl _start_main +.globl mtvec_handler +.section .text +_start_main: +h0_start: + li x22, 0x40801104 + csrw 0x301, x22 +kernel_sp: + la x31, kernel_stack_end + +trap_vec_init: + la x22, mtvec_handler + ori x22, x22, 1 + csrw 0x305, x22 # MTVEC + +mepc_setup: + la x22, init + csrw mepc, x22 + +custom_csr_setup: + nop + +init_machine_mode: + li x22, 0x58401844 + csrw 0x300, x22 # MSTATUS + li x22, 0x62079444 + csrw 0x304, x22 # MIE + mret +init: + li a0, 0x80000000 + li s0, 0x19 + li x0, 0x0 + li x1, 0x0 + li x3, 0x9d413784 + li x4, 0xe + li x5, 0xfeae9769 + li x6, 0x80000000 + li x7, 0xf7bf2feb + li x8, 0x0 + li x9, 0x38d06566 + li x10, 0x0 + li x11, 0x0 + li x12, 0x6 + li x13, 0x80000000 + li x14, 0x93130db0 + li x15, 0xa + li x16, 0x0 + li x17, 0x9bbac4e2 + li x18, 0x0 + li x19, 0x80000000 + li x20, 0x80000000 + li x21, 0x80000000 + li x22, 0x80000000 + li x23, 0xf5e35c4d + li x24, 0xd18d2d96 + li x25, 0xf5321cad + li x26, 0xffc4b9d7 + li x27, 0xb + li x28, 0x6 + li x29, 0x80000000 + li x30, 0x0 + li a0, 0x80000000 + li s0, 0xd0 + la x2, user_stack_end +main: fence.i + slli t4, s1, 18 + lui s1, 389032 + sub s3, s6, t0 + and t2, s5, s3 + fence + c.srli s1, 23 + addi t2, t0, 337 + sll t0, t2, t0 + c.nop + + # Manual instructions + .4byte 0x80fe4c33 # manual: opcode = OP, func7 = 1000000 + .4byte 0x00200073 # manual: instr uret, opcode = SYSTEM, [31:20] = h002 + .4byte 0xb1600073 # manual: random [31:20], opcode = SYSTEM + + + # Generated instructions + .4byte 0x3e0003fb # custom-3 + .4byte 0xb286bdfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x5f57cbfb # custom-3 cv.cplxconj block + .4byte 0xe097acfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd6433aab # custom-1 Plane A illegal func7 + .4byte 0x0207bbfb # custom-3 + .4byte 0xb68748ab # custom-1 plane B + .4byte 0x0ad450fb # custom-3 + .4byte 0x6abd057b # custom-3 + .4byte 0x6657eefb # custom-3 cv.subrotmj block + .4byte 0x2baa46fb # custom-3 + .4byte 0x872c4cab # custom-1 plane B + .4byte 0x1f5f0dfb # custom-3 + .4byte 0x2665817b # custom-3 + .4byte 0xb2dcbd2b # custom-1 Plane A illegal func7 + .4byte 0xa80616db # custom-2 + .4byte 0x935e422b # custom-1 plane B + .4byte 0xe9bf917b # all the groups of 8 illegal instr in custom-3 + .4byte 0x4977c42b # custom-1 plane B + .4byte 0xd8eecdab # custom-1 plane B + .4byte 0x63a51d7b # custom-3 + .4byte 0x5ca58c7b # custom-3 cv.cplxconj block + .4byte 0x6205c4ab # custom-1 plane B + .4byte 0x22d5bd7b # custom-3 + .4byte 0x5bb4c57b # custom-3 + .4byte 0xb30a827b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe273d6ab # custom-1 func3 = 101 + .4byte 0x7ecdb1fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xc6df492b # custom-1 plane B + .4byte 0x6784b62b # legal func7 but non-zero value for rs2 + .4byte 0x712de1fb # custom-3 cv.abs(.h/.b) & below + .4byte 0x6cfbfc7b # custom-3 cv.add/sub.div blocks + .4byte 0x73a4997b # custom-3 cv.abs(.h/.b) & below + .4byte 0xe8c65dfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x7d1ee3fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xf96a9efb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x6f826e7b # custom-3 cv.add/sub.div blocks + .4byte 0x9002442b # custom-1 plane B + .4byte 0xc98f247b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x175eb97b # custom-3 + .4byte 0xb1cc547b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe1844c2b # custom-1 plane B + .4byte 0xf9500f7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7e793dab # custom-1 Plane A illegal func7 + .4byte 0xeeef1adb # custom-2 bitrev 29:27 + .4byte 0x8aa344fb # custom-3 + .4byte 0xe09c985b # custom-2 bitrev 29:27 + .4byte 0xe93b847b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe84988db # custom-2 + .4byte 0xb795195b # custom-2 + .4byte 0xef279ddb # custom-2 bitrev 29:27 + .4byte 0x22f4447b # custom-3 + .4byte 0x7f02237b # all the groups of 8 illegal instr in custom-3 + .4byte 0x969cb5ab # custom-1 Plane A illegal func7 + .4byte 0xe8d3c8ab # custom-1 plane B + .4byte 0x60f4b3ab # legal func7 but non-zero value for rs2 + .4byte 0xf7cf41ab # custom-1 plane B + .4byte 0xd04494db # custom-2 bitrev 29:27 + .4byte 0x6d25547b # custom-3 cv.add/sub.div blocks + .4byte 0xa267537b # custom-3 + .4byte 0xd19e35fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x93ff12fb # custom-3 + .4byte 0xaabea37b # custom-3 + .4byte 0x658ab92b # legal func7 but non-zero value for rs2 + .4byte 0x0c304bab # custom-1 plane B + .4byte 0x7b44eafb # all the groups of 8 illegal instr in custom-3 + .4byte 0xdf5006db # custom-2 + .4byte 0xbc81985b # custom-2 + .4byte 0x56974b2b # custom-1 plane B + .4byte 0xc86257fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x5b4a257b # custom-3 + .4byte 0x528e957b # custom-3 + .4byte 0x0f4a247b # custom-3 + .4byte 0x72685d7b # custom-3 cv.abs(.h/.b) & below + .4byte 0x0b02b87b # custom-3 + .4byte 0x3a484d7b # custom-3 + .4byte 0xca413e0b # cv.elw + .4byte 0x21bd452b # custom-1 plane B + .4byte 0xe2a0c1fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7659c37b # custom-3 cv.sub.div + .4byte 0xfcbf0e5b # custom-2 + .4byte 0xbfe4caab # custom-1 plane B + .4byte 0x6b3d3eab # custom-1 Plane A illegal func7 + .4byte 0xfc954d2b # custom-1 plane B + .4byte 0xe1c04f2b # custom-1 plane B + .4byte 0xcd6ac82b # custom-1 plane B + .4byte 0xfe77b0ab # custom-1 Plane A illegal func7 + .4byte 0x7bf6c77b # all the groups of 8 illegal instr in custom-3 + .4byte 0xcb03875b # custom-2 + .4byte 0xcb07667b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf8dd11db # custom-2 bitrev 29:27 + .4byte 0x2eccac7b # custom-3 + .4byte 0x7f550cfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x338b9efb # custom-3 + .4byte 0x3202257b # custom-3 + .4byte 0x503deaab # custom-1 func3 = 110 + .4byte 0x752290fb # custom-3 cv.sub.div + .4byte 0x794274fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xed218d5b # custom-2 + .4byte 0x54f6957b # custom-3 cv.cplxmul block + .4byte 0xab7481fb # custom-3 + .4byte 0x0cfe41ab # custom-1 plane B + .4byte 0xda8b36ab # custom-1 Plane A illegal func7 + .4byte 0x52c9d67b # custom-3 + .4byte 0x4a4bf1ab # custom-1 func3 = 111 + .4byte 0xcbcab72b # custom-1 Plane A illegal func7 + .4byte 0xc9e6bb2b # custom-1 Plane A illegal func7 + .4byte 0x4a4e5b7b # custom-3 + .4byte 0xfaba2c7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf32bb72b # custom-1 Plane A illegal func7 + .4byte 0x778c567b # custom-3 cv.sub.div + .4byte 0xae4fc3ab # custom-1 plane B + .4byte 0xeac39a7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x93df50fb # custom-3 + .4byte 0xf0c65d7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xaa7c4efb # custom-3 + .4byte 0x6bdcbd7b # custom-3 + .4byte 0x76bb9b7b # custom-3 cv.sub.div + .4byte 0xd1c442ab # custom-1 plane B + .4byte 0x4fad05fb # custom-3 + .4byte 0x477c157b # custom-3 + .4byte 0xe39e847b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x6c44c32b # custom-1 plane B + .4byte 0x0ff840ab # custom-1 plane B + .4byte 0x72d04afb # custom-3 cv.abs(.h/.b) & below + .4byte 0x2e8cba7b # custom-3 + .4byte 0x4501bdab # legal func7 but non-zero value for rs2 + .4byte 0xab8c567b # custom-3 + .4byte 0xd192caab # custom-1 plane B + .4byte 0x71519cfb # custom-3 cv.abs(.h/.b) & below + .4byte 0xdb13ae7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xe1e3cdfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd07c9bdb # custom-2 bitrev 29:27 + .4byte 0x03b598fb # custom-3 + .4byte 0xc34ec77b # custom-3 cv.shuffle block + .4byte 0x7fa1dcfb # all the groups of 8 illegal instr in custom-3 + .4byte 0xcbdf337b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x9b232cfb # custom-3 + .4byte 0xc571005b # custom-2 + .4byte 0x0b781cfb # custom-3 + .4byte 0xfbf039fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x4f1611fb # custom-3 + .4byte 0x5c63d87b # custom-3 cv.cplxconj block + .4byte 0x9a9fb52b # custom-1 Plane A illegal func7 + .4byte 0x0e70d37b # custom-3 + .4byte 0xe9cdf47b # all the groups of 8 illegal instr in custom-3 + .4byte 0x43efddfb # custom-3 + .4byte 0x31f5caab # custom-1 plane B + .4byte 0x0a6a45fb # custom-3 + .4byte 0x7bd2b87b # all the groups of 8 illegal instr in custom-3 + .4byte 0xcbaa427b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7849457b # all the groups of 8 illegal instr in custom-3 + .4byte 0x1b0c4c2b # custom-1 plane B + .4byte 0x8fa5ca2b # custom-1 plane B + .4byte 0xce15b0ab # custom-1 Plane A illegal func7 + .4byte 0xce2842ab # custom-1 plane B + .4byte 0xf0df987b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x644dceab # custom-1 plane B + .4byte 0x189fc22b # custom-1 plane B + .4byte 0xc833b1fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x491a36ab # legal func7 but non-zero value for rs2 + .4byte 0xdbc4857b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x2374997b # custom-3 + .4byte 0xbb9b6c7b # custom-3 cv.extract/insert block + .4byte 0xc369d6fb # custom-3 cv.shuffle block + .4byte 0x1f3e427b # custom-3 + .4byte 0xa31bbc7b # custom-3 + .4byte 0x277dc1ab # custom-1 plane B + .4byte 0x06f78afb # custom-3 + .4byte 0xf86fdf7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xbc3e93db # custom-2 + .4byte 0xd03706fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7d79b22b # custom-1 Plane A illegal func7 + .4byte 0x17fa4efb # custom-3 + .4byte 0x4c21c0ab # custom-1 plane B + .4byte 0x074dbefb # custom-3 + .4byte 0xd0434dfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x82a022fb # custom-3 + .4byte 0x76283d7b # custom-3 cv.sub.div + .4byte 0x1bf15f7b # custom-3 + .4byte 0xd1bcd9fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd85888fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd051342b # custom-1 Plane A illegal func7 + .4byte 0x4b1a41fb # custom-3 + .4byte 0xe1c883fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x6dc1937b # custom-3 cv.add/sub.div blocks + .4byte 0xa253a77b # custom-3 + .4byte 0xa7db3dab # custom-1 Plane A illegal func7 + .4byte 0xab5cbffb # custom-3 + .4byte 0x7b41442b # custom-1 plane B + .4byte 0xcb0b007b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xc424ceab # custom-1 plane B + .4byte 0x4afcc8ab # custom-1 plane B + .4byte 0x1311127b # custom-3 + .4byte 0x3354c2ab # custom-1 plane B + .4byte 0x88e04a2b # custom-1 plane B + .4byte 0xf595b92b # custom-1 Plane A illegal func7 + .4byte 0x625baffb # custom-3 + .4byte 0x7841847b # all the groups of 8 illegal instr in custom-3 + .4byte 0xf7aeb5ab # custom-1 Plane A illegal func7 + .4byte 0x6c3a3afb # custom-3 cv.add/sub.div blocks + .4byte 0xeb23d6fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xe2c9137b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x37f20b7b # custom-3 + .4byte 0xf39d697b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x5e3fe8fb # custom-3 cv.cplxconj block + .4byte 0x07afa9fb # custom-3 + .4byte 0x6af8227b # custom-3 + .4byte 0x7441847b # custom-3 cv.sub.div + .4byte 0x32be3a7b # custom-3 + .4byte 0x569f1e7b # custom-3 cv.cplxmul block + .4byte 0x1a8fbc7b # custom-3 + .4byte 0x2e3cb7ab # custom-1 Plane A illegal func7 + .4byte 0xb25ff5fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x1554c1ab # custom-1 plane B + .4byte 0x94754e2b # custom-1 plane B + .4byte 0x80d54fab # custom-1 plane B + .4byte 0xf0ce3d2b # custom-1 Plane A illegal func7 + .4byte 0x75ffb4fb # custom-3 cv.sub.div + .4byte 0xcddc00db # custom-2 + .4byte 0x42a1beab # legal func7 but non-zero value for rs2 + .4byte 0xe7debc2b # custom-1 Plane A illegal func7 + .4byte 0x6f4bbe7b # custom-3 cv.add/sub.div blocks + .4byte 0xbcdfbc2b # custom-1 Plane A illegal func7 + .4byte 0x7cab427b # all the groups of 8 illegal instr in custom-3 + .4byte 0x32794eab # custom-1 plane B + .4byte 0x63cbdcfb # custom-3 + .4byte 0x2eef99fb # custom-3 + .4byte 0xf84dcbfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xac8f38ab # custom-1 Plane A illegal func7 + .4byte 0xd9fd65fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x9c0291db # custom-2 + .4byte 0xea9cc97b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe9e210db # custom-2 bitrev 29:27 + .4byte 0xdd4f4dab # custom-1 plane B + .4byte 0x5202377b # custom-3 + .4byte 0x806a1bdb # custom-2 + .4byte 0xcc4abcab # custom-1 Plane A illegal func7 + .4byte 0x2211aafb # custom-3 + .4byte 0xce96855b # custom-2 + .4byte 0x9247c87b # custom-3 + .4byte 0x7467537b # custom-3 cv.sub.div + .4byte 0x7b824bab # custom-1 plane B + .4byte 0xfeffc82b # custom-1 plane B + .4byte 0xd8c235fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3f38117b # custom-3 + .4byte 0xd2bec52b # custom-1 plane B + .4byte 0x6f061dfb # custom-3 cv.add/sub.div blocks + .4byte 0xd2b411db # custom-2 bitrev 29:27 + .4byte 0xe4c4ba2b # custom-1 Plane A illegal func7 + .4byte 0xca5c1f7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xb7d693db # custom-2 + .4byte 0xd9284d7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x07a2537b # custom-3 + .4byte 0x2bdf11fb # custom-3 + .4byte 0xc05e422b # custom-1 plane B + .4byte 0x76a022fb # custom-3 cv.sub.div + .4byte 0xfc454e2b # custom-1 plane B + .4byte 0x3f895afb # custom-3 + .4byte 0x1fc79efb # custom-3 + .4byte 0x7940167b # all the groups of 8 illegal instr in custom-3 + .4byte 0x9bd336fb # custom-3 + .4byte 0x2846c32b # custom-1 plane B + .4byte 0xfcf5075b # custom-2 + .4byte 0x4e1020fb # custom-3 + .4byte 0xe3f1392b # custom-1 Plane A illegal func7 + .4byte 0xeabb62fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x1ab2097b # custom-3 + .4byte 0x70743ffb # custom-3 cv.abs(.h/.b) & below + .4byte 0xe2ebd37b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x32f247fb # custom-3 + .4byte 0x372bccfb # custom-3 + .4byte 0x86f3402b # custom-1 plane B + .4byte 0x22444fab # custom-1 plane B + .4byte 0xf24632fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xfa67e4fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x92b644ab # custom-1 plane B + .4byte 0xfbe585fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3f5b2a7b # custom-3 + .4byte 0xf3b6a87b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xcb5c25fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x9828c9ab # custom-1 plane B + .4byte 0xe27cab7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x70b073fb # custom-3 cv.abs(.h/.b) & below + .4byte 0x2bc0aefb # custom-3 + .4byte 0xb5a343ab # custom-1 plane B + .4byte 0xd3a73ffb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xdfac165b # custom-2 bitrev 29:27 + .4byte 0x3a351efb # custom-3 + .4byte 0xb862115b # custom-2 + .4byte 0xe7f24cab # custom-1 plane B + .4byte 0x7738e07b # custom-3 cv.sub.div + .4byte 0x7318f9fb # custom-3 cv.abs(.h/.b) & below + .4byte 0xd2bf25fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xe993175b # custom-2 bitrev 29:27 + .4byte 0xf1f80f7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x8ff7935b # custom-2 + .4byte 0xf1c347fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf5b7105b # custom-2 bitrev 29:27 + .4byte 0xbe86392b # custom-1 Plane A illegal func7 + .4byte 0xc1a55b7b # custom-3 cv.shuffle block + .4byte 0x5b7e967b # custom-3 + .4byte 0x2abf442b # custom-1 plane B + .4byte 0xd17ea07b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x6851b72b # custom-1 Plane A illegal func7 + .4byte 0xd9f8a1fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x5ae25e7b # custom-3 + .4byte 0xea21377b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe9c664fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xb01830ab # custom-1 Plane A illegal func7 + .4byte 0xb02ce77b # all the groups of 8 illegal instr in custom-3 + .4byte 0xd247005b # custom-2 + .4byte 0xd138e07b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3ccdc3ab # custom-1 plane B + .4byte 0x5289827b # custom-3 + .4byte 0x26114c7b # custom-3 + .4byte 0x64394eab # custom-1 plane B + .4byte 0x765675fb # custom-3 cv.sub.div + .4byte 0xcde78edb # custom-2 + .4byte 0x7dcab4fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x87e91adb # custom-2 + .4byte 0x078c117b # custom-3 + .4byte 0x321ec9ab # custom-1 plane B + .4byte 0x3ee9bbab # custom-1 Plane A illegal func7 + .4byte 0xde02402b # custom-1 plane B + .4byte 0x5e0b0d7b # custom-3 cv.cplxconj block + .4byte 0xe1a917fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x135d8c7b # custom-3 + .4byte 0x46d5c0fb # custom-3 + .4byte 0x5edd302b # custom-1 Plane A illegal func7 + .4byte 0xaa0f3c2b # custom-1 Plane A illegal func7 + .4byte 0xba137efb # custom-3 cv.extract/insert block + .4byte 0x0e0f967b # custom-3 + .4byte 0x92e1aefb # custom-3 + .4byte 0x4e1754fb # custom-3 + .4byte 0x7694847b # custom-3 cv.sub.div + .4byte 0x1632d6fb # custom-3 + .4byte 0x279423fb # custom-3 + .4byte 0x6e47f27b # custom-3 cv.add/sub.div blocks + .4byte 0x832f17fb # custom-3 + .4byte 0x836acbab # custom-1 plane B + .4byte 0xa61d4d2b # custom-1 plane B + .4byte 0xb43339ab # custom-1 Plane A illegal func7 + .4byte 0xb10021fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xf1ef65fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3631d6fb # custom-3 + .4byte 0xde82195b # custom-2 bitrev 29:27 + .4byte 0x5ad8ba7b # custom-3 + .4byte 0xdd4a9edb # custom-2 bitrev 29:27 + .4byte 0x7a7fa8fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x5d31c8fb # custom-3 cv.cplxconj block + .4byte 0x3b19517b # custom-3 + .4byte 0x2fe708fb # custom-3 + .4byte 0xfaa91cfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x8b5f837b # custom-3 + .4byte 0x5e10a5fb # custom-3 cv.cplxconj block + .4byte 0xe90e24fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xf880e2fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xe656412b # custom-1 plane B + .4byte 0x067832ab # custom-1 Plane A illegal func7 + .4byte 0xa2e0c6fb # custom-3 + .4byte 0x55abda7b # custom-3 cv.cplxmul block + .4byte 0xf99fbb2b # custom-1 Plane A illegal func7 + .4byte 0x9a59c37b # custom-3 + .4byte 0x1f5130ab # custom-1 Plane A illegal func7 + .4byte 0x57f25ffb # custom-3 cv.cplxmul block + .4byte 0x269b9bfb # custom-3 + .4byte 0x66d5bafb # custom-3 cv.subrotmj block + .4byte 0xee9b36ab # custom-1 Plane A illegal func7 + .4byte 0xdfa6402b # custom-1 plane B + .4byte 0xeedd88db # custom-2 + .4byte 0x0f5933fb # custom-3 + .4byte 0x6ec3d77b # custom-3 cv.add/sub.div blocks + .4byte 0x9cde9ddb # custom-2 + .4byte 0xe86eba2b # custom-1 Plane A illegal func7 + .4byte 0x6e053bab # custom-1 Plane A illegal func7 + .4byte 0x02724d7b # custom-3 + .4byte 0xd28313fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xe15fd87b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xa1bb9bdb # custom-2 + .4byte 0x750f777b # custom-3 cv.sub.div + .4byte 0x8bb891fb # custom-3 + .4byte 0x3e4f307b # custom-3 + .4byte 0x7f75eb7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x7db2a2fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x63ab3cfb # custom-3 + .4byte 0x57f7cf2b # custom-1 plane B + .4byte 0xa1da135b # custom-2 + .4byte 0xdfd782db # custom-2 + .4byte 0xdb9b10db # custom-2 bitrev 29:27 + .4byte 0xe327c32b # custom-1 plane B + .4byte 0x3613967b # custom-3 + .4byte 0xb8b963fb # custom-3 cv.extract/insert block + .4byte 0xce3308db # custom-2 + .4byte 0x67f01dfb # custom-3 cv.subrotmj block + .4byte 0xef2d4dab # custom-1 plane B + .4byte 0xea3b362b # custom-1 Plane A illegal func7 + .4byte 0xf21c877b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x4615067b # custom-3 + .4byte 0x1250a9fb # custom-3 + .4byte 0xe061377b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x8b5e43ab # custom-1 plane B + .4byte 0x3ca7b6ab # custom-1 Plane A illegal func7 + .4byte 0xe91cbb7b # all the groups of 8 illegal instr in custom-3 + .4byte 0xa14bb2ab # custom-1 Plane A illegal func7 + .4byte 0x72a6047b # custom-3 cv.abs(.h/.b) & below + .4byte 0xd9fa1bdb # custom-2 bitrev 29:27 + .4byte 0x9a8a9e5b # custom-2 + .4byte 0xdbbb5e7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7d5afe7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x3c45cf2b # custom-1 plane B + .4byte 0xeb642f7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x13f335fb # custom-3 + .4byte 0x6eeec87b # custom-3 cv.add/sub.div blocks + .4byte 0xd848987b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x4ef2b2fb # custom-3 + .4byte 0xb55992db # custom-2 + .4byte 0x1681b9ab # custom-1 Plane A illegal func7 + .4byte 0xf375005b # custom-2 + .4byte 0x3e864c2b # custom-1 plane B + .4byte 0x8e34422b # custom-1 plane B + .4byte 0x1c8d3bab # custom-1 Plane A illegal func7 + .4byte 0x9562b5ab # custom-1 Plane A illegal func7 + .4byte 0x8bffb4fb # custom-3 + .4byte 0xda0b177b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x16f91efb # custom-3 + .4byte 0x9f34b0ab # custom-1 Plane A illegal func7 + .4byte 0x5dbbf0fb # custom-3 cv.cplxconj block + .4byte 0x6dd845ab # custom-1 plane B + .4byte 0xe8a44bfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x7d2290fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x1a6f2dfb # custom-3 + .4byte 0xd3a54b7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x5b38017b # custom-3 + .4byte 0xcbfc815b # custom-2 + .4byte 0xb32d94db # custom-2 + .4byte 0x0ddf4aab # custom-1 plane B + .4byte 0xde5a875b # custom-2 + .4byte 0x0bac287b # custom-3 + .4byte 0x1fa9d7fb # custom-3 + .4byte 0x6b65d87b # custom-3 + .4byte 0x02b02a7b # custom-3 + .4byte 0x37983dab # custom-1 Plane A illegal func7 + .4byte 0x7988ac7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x07314d7b # custom-3 + .4byte 0x4fc6c9fb # custom-3 + .4byte 0x55fefb7b # custom-3 cv.cplxmul block + .4byte 0xf220195b # custom-2 bitrev 29:27 + .4byte 0x33d8017b # custom-3 + .4byte 0xd3ffdafb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xb0d24dfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x224759fb # custom-3 + .4byte 0x82fa07fb # custom-3 + .4byte 0x42b51afb # custom-3 + .4byte 0xa5223c2b # custom-1 Plane A illegal func7 + .4byte 0xf09199db # custom-2 bitrev 29:27 + .4byte 0x7925ecfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x7fab7e7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x5c342cfb # custom-3 cv.cplxconj block + .4byte 0xdafe66fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x70488bfb # custom-3 cv.abs(.h/.b) & below + .4byte 0x17e80dfb # custom-3 + .4byte 0xfa8ad5fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xa22dca2b # custom-1 plane B + .4byte 0xe9060f5b # custom-2 + .4byte 0xeb6948ab # custom-1 plane B + .4byte 0x9ade11fb # custom-3 + .4byte 0x6bcd1bfb # custom-3 + .4byte 0xeff1185b # custom-2 bitrev 29:27 + .4byte 0x6ab04e7b # custom-3 + .4byte 0x0f174e2b # custom-1 plane B + .4byte 0x5333c37b # custom-3 + .4byte 0xe858035b # custom-2 + .4byte 0xb22b905b # custom-2 + .4byte 0x92430f7b # custom-3 + .4byte 0x7ebb9b7b # all the groups of 8 illegal instr in custom-3 + .4byte 0xb1b191fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xbbd8b3ab # custom-1 Plane A illegal func7 + .4byte 0x6c1db9ab # custom-1 Plane A illegal func7 + .4byte 0x7b7d587b # all the groups of 8 illegal instr in custom-3 + .4byte 0x5f13737b # custom-3 cv.cplxconj block + .4byte 0x43d3ad7b # custom-3 + .4byte 0x83a0ccfb # custom-3 + .4byte 0xf3f5015b # custom-2 + .4byte 0xb2e44d2b # custom-1 plane B + .4byte 0xdbadb77b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xa3931d5b # custom-2 + .4byte 0x0e12cfab # custom-1 plane B + .4byte 0x264ed67b # custom-3 + .4byte 0xa46a19db # custom-2 + .4byte 0x366caafb # custom-3 + .4byte 0x70ef247b # custom-3 cv.abs(.h/.b) & below + .4byte 0x46c0352b # legal func7 but non-zero value for rs2 + .4byte 0x9b080c7b # custom-3 + .4byte 0x8b14c5ab # custom-1 plane B + .4byte 0xc4e03e2b # custom-1 Plane A illegal func7 + .4byte 0xb2bd607b # all the groups of 8 illegal instr in custom-3 + .4byte 0xb846492b # custom-1 plane B + .4byte 0x73c92f7b # custom-3 cv.abs(.h/.b) & below + .4byte 0x9d2ebc2b # custom-1 Plane A illegal func7 + .4byte 0xc323b9ab # custom-1 Plane A illegal func7 + .4byte 0xb193f1fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xfb8a195b # custom-2 bitrev 29:27 + .4byte 0x958892db # custom-2 + .4byte 0xe3556bfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x1a64977b # custom-3 + .4byte 0x23ec87fb # custom-3 + .4byte 0x03bd85fb # custom-3 + .4byte 0xb14e0afb # all the groups of 8 illegal instr in custom-3 + .4byte 0xa70c9bdb # custom-2 + .4byte 0xd91f3c2b # custom-1 Plane A illegal func7 + .4byte 0x85e811db # custom-2 + .4byte 0x273739fb # custom-3 + .4byte 0xb01e432b # custom-1 plane B + .4byte 0xc39629fb # custom-3 cv.shuffle block + .4byte 0x7a8bb52b # custom-1 Plane A illegal func7 + .4byte 0x7a94847b # all the groups of 8 illegal instr in custom-3 + .4byte 0xa2d6127b # custom-3 + .4byte 0x4656a4fb # custom-3 + .4byte 0xc967077b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x0390547b # custom-3 + .4byte 0x9df999db # custom-2 + .4byte 0x5ee249ab # custom-1 plane B + .4byte 0xda93427b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x4d6034ab # custom-1 Plane A illegal func7 + .4byte 0x624bc02b # custom-1 plane B + .4byte 0xe18fe2fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x0b9e8e7b # custom-3 + .4byte 0xd4e317db # custom-2 bitrev 29:27 + .4byte 0x476c58fb # custom-3 + .4byte 0x1266d27b # custom-3 + .4byte 0x7ff645fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xd6e2c4ab # custom-1 plane B + .4byte 0xe332b9fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x2b2a86fb # custom-3 + .4byte 0xe36ac92b # custom-1 plane B + .4byte 0x3af98cfb # custom-3 + .4byte 0xaa0298fb # custom-3 + .4byte 0x1f81b27b # custom-3 + .4byte 0x73ecb8fb # custom-3 cv.abs(.h/.b) & below + .4byte 0xca9e5ffb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf3340fdb # custom-2 + .4byte 0x8e8f4b2b # custom-1 plane B + .4byte 0x35fa4b2b # custom-1 plane B + .4byte 0xc115372b # custom-1 Plane A illegal func7 + .4byte 0xe7f081db # custom-2 + .4byte 0x78f7dc7b # all the groups of 8 illegal instr in custom-3 + .4byte 0xccd7055b # custom-2 + .4byte 0x2e08447b # custom-3 + .4byte 0x4358477b # custom-3 + .4byte 0x6fb3a17b # custom-3 cv.add/sub.div blocks + .4byte 0x8293da7b # custom-3 + .4byte 0xa92cbcab # custom-1 Plane A illegal func7 + .4byte 0xeabecbab # custom-1 plane B + .4byte 0xd4dc805b # custom-2 + .4byte 0xc2fe3bfb # custom-3 cv.shuffle block + .4byte 0xd3f60cfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd1c29f5b # custom-2 bitrev 29:27 + .4byte 0x5fa55d7b # custom-3 cv.cplxconj block + .4byte 0xc6733cab # custom-1 Plane A illegal func7 + .4byte 0x9d08c0ab # custom-1 plane B + .4byte 0x42198d7b # custom-3 + .4byte 0xa92f4cab # custom-1 plane B + .4byte 0x98de382b # custom-1 Plane A illegal func7 + .4byte 0x1f84a6fb # custom-3 + .4byte 0xee00175b # custom-2 bitrev 29:27 + .4byte 0x83543c7b # custom-3 + .4byte 0x5575b97b # custom-3 cv.cplxmul block + .4byte 0xb25f5cfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x6368b5ab # legal func7 but non-zero value for rs2 + .4byte 0x5f12b07b # custom-3 cv.cplxconj block + .4byte 0xb02a3c7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x58a8cc2b # custom-1 plane B + .4byte 0xb3a7c87b # all the groups of 8 illegal instr in custom-3 + .4byte 0xbd3f9adb # custom-2 + .4byte 0x7c38d0fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x7024dc7b # custom-3 cv.abs(.h/.b) & below + .4byte 0xd1cb1d5b # custom-2 bitrev 29:27 + .4byte 0x8bd8227b # custom-3 + .4byte 0xae9a965b # custom-2 + .4byte 0x9cf09adb # custom-2 + .4byte 0x26e8b12b # custom-1 Plane A illegal func7 + .4byte 0x84a8115b # custom-2 + .4byte 0x53412e7b # custom-3 + .4byte 0xa3fb38ab # custom-1 Plane A illegal func7 + .4byte 0xf367147b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x16f64b2b # custom-1 plane B + .4byte 0x7203c12b # custom-1 plane B + .4byte 0xd2aa16db # custom-2 bitrev 29:27 + .4byte 0xf8c11bdb # custom-2 bitrev 29:27 + .4byte 0x7b7afd7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x5d8acd2b # custom-1 plane B + .4byte 0x1abd4dfb # custom-3 + .4byte 0x5dfd9b7b # custom-3 cv.cplxconj block + .4byte 0x73aaeffb # custom-3 cv.abs(.h/.b) & below + .4byte 0x4a29b52b # custom-1 Plane A illegal func7 + .4byte 0x66e7c0fb # custom-3 cv.subrotmj block + .4byte 0x5f6617fb # custom-3 cv.cplxconj block + .4byte 0xd28c3c2b # custom-1 Plane A illegal func7 + .4byte 0x5cd965fb # custom-3 cv.cplxconj block + .4byte 0xb98738ab # custom-1 Plane A illegal func7 + .4byte 0x7aaa492b # custom-1 plane B + .4byte 0x8fc29bdb # custom-2 + .4byte 0xa3d4097b # custom-3 + .4byte 0x57d97afb # custom-3 cv.cplxmul block + .4byte 0xfa233bab # custom-1 Plane A illegal func7 + .4byte 0x9a9a5cfb # custom-3 + .4byte 0xf0c9975b # custom-2 bitrev 29:27 + .4byte 0xec65005b # custom-2 + .4byte 0x1322407b # custom-3 + .4byte 0x6fa505fb # custom-3 cv.add/sub.div blocks + .4byte 0xedfe995b # custom-2 bitrev 29:27 + .4byte 0xd5e4312b # custom-1 Plane A illegal func7 + .4byte 0x92283d7b # custom-3 + .4byte 0xf00f9edb # custom-2 bitrev 29:27 + .4byte 0x67f2287b # custom-3 cv.subrotmj block + .4byte 0xd81b1fdb # custom-2 bitrev 29:27 + .4byte 0xf9f2a3fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf10399db # custom-2 bitrev 29:27 + .4byte 0xc0c949fb # custom-3 cv.shuffle block + .4byte 0xbdbb40ab # custom-1 plane B + .4byte 0xd89ccf2b # custom-1 plane B + .4byte 0x86a01c5b # custom-2 + .4byte 0x7b121f7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x4361377b # custom-3 + .4byte 0xe53f915b # custom-2 bitrev 29:27 + .4byte 0xf2dfc6fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd39e6b7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xc0c835fb # custom-3 cv.shuffle block + .4byte 0x78c4bf2b # custom-1 Plane A illegal func7 + .4byte 0xc92919fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xef01c52b # custom-1 plane B + .4byte 0x630789fb # custom-3 + .4byte 0x56eeb0fb # custom-3 cv.cplxmul block + .4byte 0xd0a6937b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf6d5cdab # custom-1 plane B + .4byte 0xd88b44ab # custom-1 plane B + .4byte 0xcd410d5b # custom-2 + .4byte 0xfa181a5b # custom-2 bitrev 29:27 + .4byte 0x66aadffb # custom-3 cv.subrotmj block + .4byte 0xf93c02db # custom-2 + .4byte 0x3942482b # custom-1 plane B + .4byte 0x36e03bfb # custom-3 + .4byte 0x4f18332b # custom-1 Plane A illegal func7 + .4byte 0x0f5d05fb # custom-3 + .4byte 0x3e36c1fb # custom-3 + .4byte 0xc961467b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xc98d6a7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x2a52387b # custom-3 + .4byte 0x32815c7b # custom-3 + .4byte 0xa2bf1cdb # custom-2 + .4byte 0x0ec6cf7b # custom-3 + .4byte 0xf15837fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xc129247b # custom-3 cv.shuffle block + .4byte 0x1727a2fb # custom-3 + .4byte 0xea9bf6fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xfb0b4b7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xb8eb7b7b # custom-3 cv.extract/insert block + .4byte 0x947f9c5b # custom-2 + .4byte 0x4b6a257b # custom-3 + .4byte 0x8b81d8fb # custom-3 + .4byte 0x3afdaafb # custom-3 + .4byte 0x6d390d7b # custom-3 cv.add/sub.div blocks + .4byte 0xcd7388db # custom-2 + .4byte 0x630dc2fb # custom-3 + .4byte 0xe03600db # custom-2 + .4byte 0xb368a6fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x2d19c2ab # custom-1 plane B + .4byte 0xb5b2ccab # custom-1 plane B + .4byte 0xeab580fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x2a49d2fb # custom-3 + .4byte 0x09fc412b # custom-1 plane B + .4byte 0x5c66b5fb # custom-3 cv.cplxconj block + .4byte 0x4bde1e7b # custom-3 + .4byte 0x977818db # custom-2 + .4byte 0x8f3645ab # custom-1 plane B + .4byte 0x17a1482b # custom-1 plane B + .4byte 0x2f87dcfb # custom-3 + .4byte 0xb44145ab # custom-1 plane B + .4byte 0x471f3dfb # custom-3 + .4byte 0x7944347b # all the groups of 8 illegal instr in custom-3 + .4byte 0x66ea097b # custom-3 cv.subrotmj block + .4byte 0x7d648cfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x4b870e7b # custom-3 + .4byte 0xe1f7b0ab # custom-1 Plane A illegal func7 + .4byte 0xb4d7c12b # custom-1 plane B + .4byte 0x71fa42fb # custom-3 cv.abs(.h/.b) & below + .4byte 0x51b7b8ab # legal func7 but non-zero value for rs2 + .4byte 0xfc2fb6ab # custom-1 Plane A illegal func7 + .4byte 0x154f372b # custom-1 Plane A illegal func7 + .4byte 0xb2d1147b # all the groups of 8 illegal instr in custom-3 + .4byte 0x4971ca2b # custom-1 plane B + .4byte 0xec3fb3ab # custom-1 Plane A illegal func7 + .4byte 0xc08c49ab # custom-1 plane B + .4byte 0xb605392b # custom-1 Plane A illegal func7 + .4byte 0xf072acfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xaf3838ab # custom-1 Plane A illegal func7 + .4byte 0x881b452b # custom-1 plane B + .4byte 0x4ad1337b # custom-3 + .4byte 0xf9c2b87b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x0f60b1ab # custom-1 Plane A illegal func7 + .4byte 0xd9b85cfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3b1ab8fb # custom-3 + .4byte 0xc7588c5b # custom-2 + .4byte 0xdea4baab # custom-1 Plane A illegal func7 + .4byte 0xeb90015b # custom-2 + .4byte 0xf4b40cdb # custom-2 + .4byte 0xa0824fab # custom-1 plane B + .4byte 0xf21257fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x16794e2b # custom-1 plane B + .4byte 0xdd363aab # custom-1 Plane A illegal func7 + .4byte 0x6667f4fb # custom-3 cv.subrotmj block + la x16, test_done + jalr x0, x16, 0 + +#Start: Extracted from riscv_compliance_tests/riscv_test.h +test_done: + csrrci x0,mstatus,0x8 # Clear MSTATUS.MIE to avoid interrupts during test_done + lui s3,print_port>>12 + addi s6,zero,'\n' + sw s6,0(s3) + addi s6,zero,'C' + sw s6,0(s3) + addi s6,zero,'V' + sw s6,0(s3) + addi s6,zero,'3' + sw s6,0(s3) + addi s6,zero,'2' + sw s6,0(s3) + addi s6,zero,' ' + sw s6,0(s3) + addi s6,zero,'D' + sw s6,0(s3) + addi s6,zero,'O' + sw s6,0(s3) + addi s6,zero,'N' + sw s6,0(s3) + addi s6,zero,'E' + sw s6,0(s3) + addi s6,zero,'\n' + sw s6,0(s3) + sw s6,0(s3) + + li s3, test_ret_val + lw s6, test_results /* report result */ + sw s6,0(s3) + + csrrwi x0,mie,0 /* clear mie so that final wfi never awakens */ + wfi /* we are done */ +#End: Extracted from riscv_compliance_tests/riscv_test.h + +write_tohost: + sw gp, tohost, t5 + +_exit: + j write_tohost + +.section .debugger, "ax" +debug_rom: + dret + +.section .debugger_exception, "ax" +debug_exception: + dret + +.section text +instr_end: + nop + +.section .data +.align 6; .global tohost; tohost: .dword 0; +.align 6; .global fromhost; fromhost: .dword 0; +.section .region_0,"aw",@progbits; +region_0: +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.section .region_1,"aw",@progbits; +region_1: +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.section .user_stack,"aw",@progbits; +.align 2 +user_stack_start: +.rept 4999 +.4byte 0x0 +.endr +user_stack_end: +.4byte 0x0 +.align 2 +debugger_stack_start: +.rept 4999 +.4byte 0x0 +.endr +debugger_stack_end: +.4byte 0x0 +.align 2 +kernel_instr_start: +.text +mmode_intr_vector_1: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_2: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_3: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_4: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_5: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_6: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_7: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_8: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_9: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_10: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_11: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_12: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_13: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_14: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_15: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_16: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_17: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_18: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_19: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_20: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_21: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_22: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_23: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_24: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_25: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_26: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_27: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_28: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_29: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_30: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_31: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +.align 8 +mtvec_handler: + .option norvc; + j mmode_exception_handler + j mmode_intr_vector_1 + j mmode_intr_vector_2 + j mmode_intr_vector_3 + j mmode_intr_vector_4 + j mmode_intr_vector_5 + j mmode_intr_vector_6 + j mmode_intr_vector_7 + j mmode_intr_vector_8 + j mmode_intr_vector_9 + j mmode_intr_vector_10 + j mmode_intr_vector_11 + j mmode_intr_vector_12 + j mmode_intr_vector_13 + j mmode_intr_vector_14 + j mmode_intr_vector_15 + j mmode_intr_vector_16 + j mmode_intr_vector_17 + j mmode_intr_vector_18 + j mmode_intr_vector_19 + j mmode_intr_vector_20 + j mmode_intr_vector_21 + j mmode_intr_vector_22 + j mmode_intr_vector_23 + j mmode_intr_vector_24 + j mmode_intr_vector_25 + j mmode_intr_vector_26 + j mmode_intr_vector_27 + j mmode_intr_vector_28 + j mmode_intr_vector_29 + j mmode_intr_vector_30 + j mmode_intr_vector_31 + .option rvc; + +mmode_exception_handler: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x341 # MEPC + csrr x22, 0x342 # MCAUSE + li x21, 0x3 # BREAKPOINT + beq x22, x21, ebreak_handler + li x21, 0x8 # ECALL_UMODE + beq x22, x21, ecall_handler + li x21, 0x9 # ECALL_SMODE + beq x22, x21, ecall_handler + li x21, 0xb # ECALL_MMODE + beq x22, x21, ecall_handler + li x21, 0x1 + beq x22, x21, instr_fault_handler + li x21, 0x5 + beq x22, x21, load_fault_handler + li x21, 0x7 + beq x22, x21, store_fault_handler + li x21, 0xc + beq x22, x21, pt_fault_handler + li x21, 0xd + beq x22, x21, pt_fault_handler + li x21, 0xf + beq x22, x21, pt_fault_handler + li x21, 0x2 # ILLEGAL_INSTRUCTION + beq x22, x21, illegal_instr_handler + csrr x21, 0x343 # MTVAL + 1: la x16, test_done + jalr x1, x16, 0 + +ecall_handler: + csrr x22, 0xcc6 + li x21, 1 + bge x22, x21, 1f + 2: csrr x22, 0xcc2 + li x21, 1 + bge x22, x21, 3f + beqz x0, 4f + 1: csrr x22, 0x341 + csrr x21, 0xcc5 + addi x21, x21, -4 + bne x22, x21, 2b + csrr x21, 0xcc6 + addi x21, x21, -1 + cv.count 1, x21 + csrr x21, 0xcc6 + beqz x21, 4f + csrr x22, 0xcc4 + beqz x0, 5f + 3: csrr x22, 0x341 + csrr x21, 0xcc1 + addi x21, x21, -4 + bne x22, x21, 4f + csrr x21, 0xcc2 + addi x21, x21, -1 + cv.count 0, x21 + csrr x21, 0xcc2 + beqz x21, 4f + csrr x22, 0xcc0 + beqz x0, 5f + 4: csrr x22, 0x341 + addi x22, x22, 4 + 5: csrw 0x341, x22 + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +instr_fault_handler: + li x22, 0 + csrw 0x340, x22 + li x3, 0 + 0: csrr x22, 0x340 + mv x16, x22 + li x16, 0 + beq x22, x16, 1f + 1: csrr x21, 0x3b0 + csrr x24, 0x3a0 + j 17f + 17: li x20, 4 + csrr x22, 0x340 + slli x22, x22, 30 + srli x22, x22, 30 + sub x16, x20, x22 + addi x16, x16, -1 + slli x16, x16, 3 + sll x20, x24, x16 + slli x22, x22, 3 + add x16, x16, x22 + srl x20, x20, x16 + slli x16, x20, 27 + srli x16, x16, 30 + beqz x16, 20f + li x22, 1 + beq x16, x22, 21f + li x22, 2 + beq x16, x22, 25f + li x22, 3 + beq x16, x22, 27f + la x22, test_done + jalr x0, x22, 0 + 18: csrr x22, 0x340 + mv x3, x21 + addi x22, x22, 1 + csrw 0x340, x22 + li x21, 1 + ble x21, x22, 19f + j 0b + 19: la x22, test_done + jalr x0, x22, 0 + 20: j 18b + 21: csrr x22, 0x340 + csrr x16, 0x343 + srli x16, x16, 2 + bnez x22, 22f + bltz x16, 18b + j 23f + 22: bgtu x3, x16, 18b + 23: bleu x21, x16, 18b + andi x16, x20, 128 + beqz x16, 24f + la x22, test_done + jalr x0, x22, 0 + 24: j 29f + 25: csrr x22, 0x343 + srli x22, x22, 2 + slli x16, x21, 2 + srli x16, x16, 2 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 26f + la x22, test_done + jalr x0, x22, 0 + 26: j 29f + 27: csrr x22, 0x343 + srli x22, x22, 2 + srli x22, x22, 0 + slli x22, x22, 0 + slli x16, x21, 2 + srli x16, x16, 2 + srli x16, x16, 0 + slli x16, x16, 0 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 29f + la x22, test_done + jalr x0, x22, 0 + 28: j 29f + 29: ori x20, x20, 4 + csrr x22, 0x340 + li x16, 30 + sll x22, x22, x16 + srl x22, x22, x16 + slli x16, x22, 3 + sll x20, x20, x16 + or x24, x24, x20 + csrr x22, 0x340 + srli x22, x22, 2 + beqz x22, 30f + li x16, 1 + beq x22, x16, 31f + li x16, 2 + beq x22, x16, 32f + li x16, 3 + beq x22, x16, 33f + 30: csrw 0x3a0, x24 + j 34f + 31: csrw 0x3a1, x24 + j 34f + 32: csrw 0x3a2, x24 + j 34f + 33: csrw 0x3a3, x24 + 34: nop + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +load_fault_handler: + li x22, 0 + csrw 0x340, x22 + li x3, 0 + 0: csrr x22, 0x340 + mv x16, x22 + li x16, 0 + beq x22, x16, 1f + 1: csrr x21, 0x3b0 + csrr x24, 0x3a0 + j 17f + 17: li x20, 4 + csrr x22, 0x340 + slli x22, x22, 30 + srli x22, x22, 30 + sub x16, x20, x22 + addi x16, x16, -1 + slli x16, x16, 3 + sll x20, x24, x16 + slli x22, x22, 3 + add x16, x16, x22 + srl x20, x20, x16 + slli x16, x20, 27 + srli x16, x16, 30 + beqz x16, 20f + li x22, 1 + beq x16, x22, 21f + li x22, 2 + beq x16, x22, 25f + li x22, 3 + beq x16, x22, 27f + la x22, test_done + jalr x0, x22, 0 + 18: csrr x22, 0x340 + mv x3, x21 + addi x22, x22, 1 + csrw 0x340, x22 + li x21, 1 + ble x21, x22, 19f + j 0b + 19: la x22, test_done + jalr x0, x22, 0 + 20: j 18b + 21: csrr x22, 0x340 + csrr x16, 0x343 + srli x16, x16, 2 + bnez x22, 22f + bltz x16, 18b + j 23f + 22: bgtu x3, x16, 18b + 23: bleu x21, x16, 18b + andi x16, x20, 128 + beqz x16, 24f + la x22, test_done + jalr x0, x22, 0 + 24: j 29f + 25: csrr x22, 0x343 + srli x22, x22, 2 + slli x16, x21, 2 + srli x16, x16, 2 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 26f + la x22, test_done + jalr x0, x22, 0 + 26: j 29f + 27: csrr x22, 0x343 + srli x22, x22, 2 + srli x22, x22, 0 + slli x22, x22, 0 + slli x16, x21, 2 + srli x16, x16, 2 + srli x16, x16, 0 + slli x16, x16, 0 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 29f + la x22, test_done + jalr x0, x22, 0 + 28: j 29f + 29: ori x20, x20, 1 + csrr x22, 0x340 + li x16, 30 + sll x22, x22, x16 + srl x22, x22, x16 + slli x16, x22, 3 + sll x20, x20, x16 + or x24, x24, x20 + csrr x22, 0x340 + srli x22, x22, 2 + beqz x22, 30f + li x16, 1 + beq x22, x16, 31f + li x16, 2 + beq x22, x16, 32f + li x16, 3 + beq x22, x16, 33f + 30: csrw 0x3a0, x24 + j 34f + 31: csrw 0x3a1, x24 + j 34f + 32: csrw 0x3a2, x24 + j 34f + 33: csrw 0x3a3, x24 + 34: nop + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +store_fault_handler: + li x22, 0 + csrw 0x340, x22 + li x3, 0 + 0: csrr x22, 0x340 + mv x16, x22 + li x16, 0 + beq x22, x16, 1f + 1: csrr x21, 0x3b0 + csrr x24, 0x3a0 + j 17f + 17: li x20, 4 + csrr x22, 0x340 + slli x22, x22, 30 + srli x22, x22, 30 + sub x16, x20, x22 + addi x16, x16, -1 + slli x16, x16, 3 + sll x20, x24, x16 + slli x22, x22, 3 + add x16, x16, x22 + srl x20, x20, x16 + slli x16, x20, 27 + srli x16, x16, 30 + beqz x16, 20f + li x22, 1 + beq x16, x22, 21f + li x22, 2 + beq x16, x22, 25f + li x22, 3 + beq x16, x22, 27f + la x22, test_done + jalr x0, x22, 0 + 18: csrr x22, 0x340 + mv x3, x21 + addi x22, x22, 1 + csrw 0x340, x22 + li x21, 1 + ble x21, x22, 19f + j 0b + 19: la x22, test_done + jalr x0, x22, 0 + 20: j 18b + 21: csrr x22, 0x340 + csrr x16, 0x343 + srli x16, x16, 2 + bnez x22, 22f + bltz x16, 18b + j 23f + 22: bgtu x3, x16, 18b + 23: bleu x21, x16, 18b + andi x16, x20, 128 + beqz x16, 24f + la x22, test_done + jalr x0, x22, 0 + 24: j 29f + 25: csrr x22, 0x343 + srli x22, x22, 2 + slli x16, x21, 2 + srli x16, x16, 2 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 26f + la x22, test_done + jalr x0, x22, 0 + 26: j 29f + 27: csrr x22, 0x343 + srli x22, x22, 2 + srli x22, x22, 0 + slli x22, x22, 0 + slli x16, x21, 2 + srli x16, x16, 2 + srli x16, x16, 0 + slli x16, x16, 0 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 29f + la x22, test_done + jalr x0, x22, 0 + 28: j 29f + 29: ori x20, x20, 3 + csrr x22, 0x340 + li x16, 30 + sll x22, x22, x16 + srl x22, x22, x16 + slli x16, x22, 3 + sll x20, x20, x16 + or x24, x24, x20 + csrr x22, 0x340 + srli x22, x22, 2 + beqz x22, 30f + li x16, 1 + beq x22, x16, 31f + li x16, 2 + beq x22, x16, 32f + li x16, 3 + beq x22, x16, 33f + 30: csrw 0x3a0, x24 + j 34f + 31: csrw 0x3a1, x24 + j 34f + 32: csrw 0x3a2, x24 + j 34f + 33: csrw 0x3a3, x24 + 34: nop + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +ebreak_handler: + csrr x22, 0xcc6 + li x21, 1 + bge x22, x21, 1f + 2: csrr x22, 0xcc2 + li x21, 1 + bge x22, x21, 3f + beqz x0, 4f + 1: csrr x22, 0x341 + csrr x21, 0xcc5 + addi x21, x21, -4 + bne x22, x21, 2b + csrr x21, 0xcc6 + addi x21, x21, -1 + cv.count 1, x21 + csrr x21, 0xcc6 + beqz x21, 4f + csrr x22, 0xcc4 + beqz x0, 5f + 3: csrr x22, 0x341 + csrr x21, 0xcc1 + addi x21, x21, -4 + bne x22, x21, 4f + csrr x21, 0xcc2 + addi x21, x21, -1 + cv.count 0, x21 + csrr x21, 0xcc2 + beqz x21, 4f + csrr x22, 0xcc0 + beqz x0, 5f + 4: csrr x22, 0x341 + addi x22, x22, 4 + 5: csrw 0x341, x22 + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +illegal_instr_handler: + csrr x22, 0xcc6 + li x21, 1 + bge x22, x21, 1f + 2: csrr x22, 0xcc2 + li x21, 1 + bge x22, x21, 3f + beqz x0, 4f + 1: csrr x22, 0x341 + csrr x21, 0xcc5 + addi x21, x21, -4 + bne x22, x21, 2b + csrr x21, 0xcc6 + addi x21, x21, -1 + cv.count 1, x21 + csrr x21, 0xcc6 + beqz x21, 4f + csrr x22, 0xcc4 + beqz x0, 5f + 3: csrr x22, 0x341 + csrr x21, 0xcc1 + addi x21, x21, -4 + bne x22, x21, 4f + csrr x21, 0xcc2 + addi x21, x21, -1 + cv.count 0, x21 + csrr x21, 0xcc2 + beqz x21, 4f + csrr x22, 0xcc0 + beqz x0, 5f + 4: csrr x22, 0x341 + addi x22, x22, 4 + 5: csrw 0x341, x22 + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +pt_fault_handler: + nop + +.align 2 +mmode_intr_handler: + csrr x22, 0x300 # MSTATUS; + csrr x22, 0x304 # MIE; + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret; + +kernel_instr_end: nop +.section .kernel_stack,"aw",@progbits; +.align 2 +kernel_stack_start: +.rept 3999 +.4byte 0x0 +.endr +kernel_stack_end: +.4byte 0x0 diff --git a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/test.yaml b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/test.yaml new file mode 100644 index 0000000000..8406783652 --- /dev/null +++ b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/test.yaml @@ -0,0 +1,6 @@ +# Test definition YAML for test + +name: custom_opcode_illegal_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Script-generated test to exercise all illegal instruction types in custom opcode spaces for CV32E40Pv2 diff --git a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c index 9b2687e115..94a994e431 100644 --- a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c +++ b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c @@ -26,9 +26,12 @@ void fp_enable () { unsigned int fs = MSTATUS_FS_INITIAL; - __asm__ volatile("csrs mstatus, %0;" - "csrwi fcsr, 0;" - : : "r"(fs)); + + asm volatile("csrs mstatus, %0;" + "csrwi fcsr, 0;" + "csrs mstatus, %0;" + : : "r"(fs) + ); } const long int INPUT[10] __attribute__ ((aligned (4))) = { diff --git a/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c b/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c index e0754b39e4..f560f4db3a 100644 --- a/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c +++ b/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c @@ -168,9 +168,29 @@ int test_mtvec() { return EXIT_SUCCESS; } +#ifdef FPU +#define MSTATUS_FS_INITIAL 0x00002000 + +void fp_enable () +{ + unsigned int fs = MSTATUS_FS_INITIAL; + + asm volatile("csrs mstatus, %0;" + "csrwi fcsr, 0;" + "csrs mstatus, %0;" + : : "r"(fs) + ); +} +#endif + int main(int argc, char *argv[]) { int retval; +#ifdef FPU + // Floating Point enable + fp_enable(); +#endif + // Trash the "default" 0 table for (int i = 0; i < 32; i++) { volatile uint32_t *ptr = (volatile uint32_t *) (0 + i*4); diff --git a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c index df241ce98e..7192b1ba36 100644 --- a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c +++ b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c @@ -48,7 +48,10 @@ void fp_enable () asm volatile("csrs mstatus, %0;" "csrwi fcsr, 0;" - : : "r"(fs)); + "csrs mstatus, %0;" + : : "r"(fs) + ); + } #endif diff --git a/cv32e40p/tests/programs/custom/matmul_32b_float/test.c b/cv32e40p/tests/programs/custom/matmul_32b_float/test.c index 13ac3b2a46..0bdbd3e3fb 100644 --- a/cv32e40p/tests/programs/custom/matmul_32b_float/test.c +++ b/cv32e40p/tests/programs/custom/matmul_32b_float/test.c @@ -47,9 +47,12 @@ int checkInt (long int *B, long int *A, long int n) void fp_enable () { unsigned int fs = MSTATUS_FS_INITIAL; - __asm__ volatile("csrs mstatus, %0;" - "csrwi fcsr, 0;" - : : "r"(fs)); + + asm volatile("csrs mstatus, %0;" + "csrwi fcsr, 0;" + "csrs mstatus, %0;" + : : "r"(fs) + ); } #endif diff --git a/cv32e40p/tests/programs/custom/pulp_hardware_loop_interrupt_test/pulp_hardware_loop_interrupt_test.c b/cv32e40p/tests/programs/custom/pulp_hardware_loop_interrupt_test/pulp_hardware_loop_interrupt_test.c index 7827fb2ccf..7cd4a5e53b 100644 --- a/cv32e40p/tests/programs/custom/pulp_hardware_loop_interrupt_test/pulp_hardware_loop_interrupt_test.c +++ b/cv32e40p/tests/programs/custom/pulp_hardware_loop_interrupt_test/pulp_hardware_loop_interrupt_test.c @@ -216,9 +216,29 @@ __attribute__((interrupt ("machine"))) void u_sw_direct_irq_handler(void) { "j u_sw_irq_handler\n" ); +#ifdef FPU +#define MSTATUS_FS_INITIAL 0x00002000 + +void fp_enable () +{ + unsigned int fs = MSTATUS_FS_INITIAL; + + asm volatile("csrs mstatus, %0;" + "csrwi fcsr, 0;" + "csrs mstatus, %0;" + : : "r"(fs) + ); +} +#endif + int main(int argc, char *argv[]) { int retval; +#ifdef FPU + // Floating Point enable + fp_enable(); +#endif + // Test 1 retval = test1(); if (retval != EXIT_SUCCESS) diff --git a/cv32e40p/tests/test_cfg/gen_limit_debug_req.yaml b/cv32e40p/tests/test_cfg/gen_limit_debug_req.yaml new file mode 100644 index 0000000000..07bee7902e --- /dev/null +++ b/cv32e40p/tests/test_cfg/gen_limit_debug_req.yaml @@ -0,0 +1,5 @@ +name: gen_limit_debug_req +description: > + Generate few random debug halt requests in range 1 to 5, or use plusarg num_debug_req=val to set number +plusargs: > + +gen_reduced_rand_dbg_req diff --git a/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml b/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml new file mode 100644 index 0000000000..5692669993 --- /dev/null +++ b/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml @@ -0,0 +1,5 @@ +name: gen_rand_debug_req +description: > + Generate Random debug halt request +plusargs: > + +gen_random_debug diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk index d7a6370ddb..f921c52287 100644 --- a/mk/uvmt/vsim.mk +++ b/mk/uvmt/vsim.mk @@ -43,9 +43,11 @@ VSIM_LOCAL_MODELSIMINI ?= YES VOPT_CODE_COV_DUT_ONLY ?= YES VSIM_USER_FLAGS ?= ifeq ($(call IS_YES,$(VOPT_CODE_COV_DUT_ONLY)),YES) -VOPT_COV ?= +cover=bcsetf+$(RTLSRC_VLOG_CORE_TOP). +# note: t/toggle is excluded in cv32e40p_v2 +VOPT_COV ?= +cover=bcsef+$(RTLSRC_VLOG_CORE_TOP). else -VOPT_COV ?= +cover=setf+$(RTLSRC_VLOG_TB_TOP). +# note: t/toggle is excluded in cv32e40p_v2 +VOPT_COV ?= +cover=sef+$(RTLSRC_VLOG_TB_TOP). endif VSIM_COV ?= -coverage +uvm_set_config_int=uvm_test_top,cov_model_enabled,1 VOPT_WAVES_ADV_DEBUG ?= -designfile design.bin @@ -147,9 +149,12 @@ VLOG_FLAGS += +define+USE_ISS VLOG_FLAGS += +define+USE_IMPERASDV VLOG_FILE_LIST_IDV = -f $(DV_UVMT_PATH)/imperas_dv.flist ifeq ($(call IS_YES,$(COV)),YES) -VLOG_FLAGS += +define+IMPERAS_COV +# VLOG_FLAGS += +define+IMPERAS_COV // fixme: add granuality for this enablement endif endif +ifeq ($(call IS_YES,$(COV)),YES) +VLOG_FLAGS += -covermultiuserenv +endif ############################################################################### # VOPT (Optimization) @@ -259,8 +264,8 @@ endif COV_FLAGS = COV_REPORT = cov_report COV_MERGE_TARGET = -COV_MERGE_FIND = find $(SIM_CFG_RESULTS) -type f -name "*.ucdb" -exec echo {} > $(VSIM_COV_MERGE_DIR)/ucdb.list \; -COV_MERGE_FLAGS = merge -testassociated -verbose -64 -out merged.ucdb -inputs ucdb.list +COV_MERGE_FIND = find $(SIM_CFG_RESULTS) -type f -name "*.ucdb" | grep -v corev-dv > $(VSIM_COV_MERGE_DIR)/ucdb.list +COV_MERGE_FLAGS = merge -testassociated -verbose -64 -multiuserenv -out merged.ucdb -inputs ucdb.list ifeq ($(call IS_YES,$(MERGE)),YES) COV_DIR=$(VSIM_COV_MERGE_DIR)