diff --git a/cv32e40p/bsp/Makefile b/cv32e40p/bsp/Makefile
index f2e0ed69c6..fe044b0ea2 100644
--- a/cv32e40p/bsp/Makefile
+++ b/cv32e40p/bsp/Makefile
@@ -3,6 +3,7 @@ RISCV            ?= $(CV_SW_TOOLCHAIN)
 RISCV_EXE_PREFIX ?= $(RISCV)/bin/riscv32-unknown-elf-
 RISCV_GCC = $(RISCV_EXE_PREFIX)gcc
 RISCV_AR = $(RISCV_EXE_PREFIX)ar
+CFG_CFLAGS = $(CFG_CFLAGS)
 SRC = crt0.S handlers.S syscalls.c vectors.S
 OBJ = crt0.o handlers.o syscalls.o vectors.o
 LIBCV-VERIF = libcv-verif.a 
@@ -14,10 +15,10 @@ $(LIBCV-VERIF): $(OBJ)
 	$(RISCV_AR) rcs $@ $(OBJ)
 
 %.o : %.c
-	$(RISCV_GCC) $(CFLAGS) -c $< -o $@
+	$(RISCV_GCC) $(CFLAGS) $(CFG_CFLAGS) -c $< -o $@
 	
 %.o : %.S
-	$(RISCV_GCC) $(CFLAGS) -c $< -o $@
+	$(RISCV_GCC) $(CFLAGS) $(CFG_CFLAGS) -c $< -o $@
 
 clean:
 	rm -f $(OBJ) $(LIBCV-VERIF)
diff --git a/cv32e40p/bsp/handlers.S b/cv32e40p/bsp/handlers.S
index 6068105276..0e27c8aae4 100644
--- a/cv32e40p/bsp/handlers.S
+++ b/cv32e40p/bsp/handlers.S
@@ -66,158 +66,174 @@
 
 /* exception handling */
 __no_irq_handler:
-	la a0, no_exception_handler_msg
-	jal ra, puts
-	j __no_irq_handler
+  la a0, no_exception_handler_msg
+  jal ra, puts
+  j __no_irq_handler
 
 m_software_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_timer_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_external_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast0_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast1_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast2_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast3_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast4_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast5_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast6_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast7_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast8_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast9_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast10_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast11_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast12_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast13_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast14_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 m_fast15_irq_handler:
-	j __no_irq_handler
+  j __no_irq_handler
 
 u_sw_irq_handler:
-	/* While we are still using puts in handlers, save all caller saved
-	   regs.  Eventually, some of these saves could be deferred.  */
-	addi sp,sp,-64
-	sw ra, 0(sp)
-	sw a0, 4(sp)
-	sw a1, 8(sp)
-	sw a2, 12(sp)
-	sw a3, 16(sp)
-	sw a4, 20(sp)
-	sw a5, 24(sp)
-	sw a6, 28(sp)
-	sw a7, 32(sp)
-	sw t0, 36(sp)
-	sw t1, 40(sp)
-	sw t2, 44(sp)
-	sw t3, 48(sp)
-	sw t4, 52(sp)
-	sw t5, 56(sp)
-	sw t6, 60(sp)
-	csrr t0, mcause
-	li t1, EXCEPTION_ILLEGAL_INSN
-	beq t0, t1, handle_illegal_insn
-	li t1, EXCEPTION_ECALL_M
-	beq t0, t1, handle_ecall
-	li t1, EXCEPTION_BREAKPOINT
-	beq t0, t1, handle_ebreak
-	j handle_unknown
+  /* While we are still using puts in handlers, save all caller saved
+     regs.  Eventually, some of these saves could be deferred.  */
+  addi sp,sp,-76
+  sw ra, 0(sp)
+  sw a0, 4(sp)
+  sw a1, 8(sp)
+  sw a2, 12(sp)
+  sw a3, 16(sp)
+  sw a4, 20(sp)
+  sw a5, 24(sp)
+  sw a6, 28(sp)
+  sw a7, 32(sp)
+  sw t0, 36(sp)
+  sw t1, 40(sp)
+  sw t2, 44(sp)
+  sw t3, 48(sp)
+  sw t4, 52(sp)
+  sw t5, 56(sp)
+  sw t6, 60(sp)
+#ifdef PULP
+  csrr t6, 0xCC0
+  sw t6, 64(sp)
+  csrr t6, 0xCC1
+  sw t6, 68(sp)
+  csrr t6, 0xCC2
+  sw t6, 72(sp)
+#endif
+  csrr t0, mcause
+  li t1, EXCEPTION_ILLEGAL_INSN
+  beq t0, t1, handle_illegal_insn
+  li t1, EXCEPTION_ECALL_M
+  beq t0, t1, handle_ecall
+  li t1, EXCEPTION_BREAKPOINT
+  beq t0, t1, handle_ebreak
+  j handle_unknown
 
 handle_ecall:
-	jal ra, handle_syscall
-	j end_handler_incr_mepc
+  jal ra, handle_syscall
+  j end_handler_incr_mepc
 
 handle_ebreak:
-	/* TODO support debug handling requirements.  */
-	la a0, ebreak_msg
-	jal ra, puts
-	j end_handler_incr_mepc
+  /* TODO support debug handling requirements.  */
+  la a0, ebreak_msg
+  jal ra, puts
+  j end_handler_incr_mepc
 
 handle_illegal_insn:
-	la a0, illegal_insn_msg
-	jal ra, puts
-	j end_handler_incr_mepc
+  la a0, illegal_insn_msg
+  jal ra, puts
+  j end_handler_incr_mepc
 
 handle_unknown:
-	la a0, unknown_msg
-	jal ra, puts
-	/* We don't know what interrupt/exception is being handled, so don't
-	   increment mepc.  */
-	j end_handler_ret
+  la a0, unknown_msg
+  jal ra, puts
+  /* We don't know what interrupt/exception is being handled, so don't
+     increment mepc.  */
+  j end_handler_ret
 
 end_handler_incr_mepc:
-	csrr t0, mepc
-	lb t1, 0(t0)
-	li a0, 0x3
-	and t1, t1, a0
-	/* Increment mepc by 2 or 4 depending on whether the instruction at mepc
-	   is compressed or not.  */
-	bne t1, a0, end_handler_incr_mepc2
-	addi t0, t0, 2
+  csrr t0, mepc
+  lb t1, 0(t0)
+  li a0, 0x3
+  and t1, t1, a0
+  /* Increment mepc by 2 or 4 depending on whether the instruction at mepc
+     is compressed or not.  */
+  bne t1, a0, end_handler_incr_mepc2
+  addi t0, t0, 2
 end_handler_incr_mepc2:
-	addi t0, t0, 2
-	csrw mepc, t0
+  addi t0, t0, 2
+  csrw mepc, t0
 end_handler_ret:
-	lw ra, 0(sp)
-	lw a0, 4(sp)
-	lw a1, 8(sp)
-	lw a2, 12(sp)
-	lw a3, 16(sp)
-	lw a4, 20(sp)
-	lw a5, 24(sp)
-	lw a6, 28(sp)
-	lw a7, 32(sp)
-	lw t0, 36(sp)
-	lw t1, 40(sp)
-	lw t2, 44(sp)
-	lw t3, 48(sp)
-	lw t4, 52(sp)
-	lw t5, 56(sp)
-	lw t6, 60(sp)
-	addi sp,sp,64
-	mret
+#ifdef PULP
+  lw t6, 64(sp)
+  cv.start 0, t6
+  lw t6, 68(sp)
+  cv.end 0, t6
+  lw t6, 72(sp)
+  cv.count 0, t6
+#endif
+  lw ra, 0(sp)
+  lw a0, 4(sp)
+  lw a1, 8(sp)
+  lw a2, 12(sp)
+  lw a3, 16(sp)
+  lw a4, 20(sp)
+  lw a5, 24(sp)
+  lw a6, 28(sp)
+  lw a7, 32(sp)
+  lw t0, 36(sp)
+  lw t1, 40(sp)
+  lw t2, 44(sp)
+  lw t3, 48(sp)
+  lw t4, 52(sp)
+  lw t5, 56(sp)
+  lw t6, 60(sp)
+  addi sp,sp,76
+  mret
 
 .section .rodata
 illegal_insn_msg:
-	.string "CV32E40P BSP: illegal instruction exception handler entered\n"
+  .string "CV32E40P BSP: illegal instruction exception handler entered\n"
 ecall_msg:
-	.string "CV32E40P BSP: ecall exception handler entered\n"
+  .string "CV32E40P BSP: ecall exception handler entered\n"
 ebreak_msg:
-	.string "CV32E40P BSP: ebreak exception handler entered\n"
+  .string "CV32E40P BSP: ebreak exception handler entered\n"
 unknown_msg:
-	.string "CV32E40P BSP: unknown exception handler entered\n"
+  .string "CV32E40P BSP: unknown exception handler entered\n"
 no_exception_handler_msg:
-	.string "CV32E40P BSP: no exception handler installed\n"
+  .string "CV32E40P BSP: no exception handler installed\n"
diff --git a/cv32e40p/docs/VerifPlans/Simulation/CV32E40Pv2_test_list.xlsx b/cv32e40p/docs/VerifPlans/Simulation/CV32E40Pv2_test_list.xlsx
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diff --git a/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx b/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx
new file mode 100644
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diff --git a/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CV32E40Pv2 - CSR_Vplan.md b/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CV32E40Pv2 - CSR_Vplan.md
new file mode 100644
index 0000000000..ab0ac39315
--- /dev/null
+++ b/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CV32E40Pv2 - CSR_Vplan.md	
@@ -0,0 +1,161 @@
+## Functional verification of CSRs in a RISC-V core
+The Controll and Status Registers in a RISC-V core are distinct from CSRs in
+non-processor ASIC/FPGA RTL in ways that have a direct impact on RTL
+verification.  Here, we discuss the problem in detail, using select RISC-V
+standard CSRs as examples.
+
+This document serves two purposes.  The first purpose is a general discussion
+and tutorial on the topic of CSR verification in general and RISC-V CSR
+verification in particular.   Its second purpose is form the Verification Plan
+(also known as a Testplan) for the CV32E40P CSRs.   Note that this Vplan does
+not follow the same spreadsheet style template that is used for other CV32E40P
+Vplans.   The reason for this will become apparent as you read the document.
+
+### Power-on-Reset Values
+
+Many (all?) RISC-V CSRs are expected to have a known value once the core comes
+out of hardware reset.  Testing these values is typically straightforward and
+is done in a way that is familiar to anyone who has done this for non-processor
+ASIC/FPGA RTL.  In both cases, care must be taken to read the value of a status
+register before the device-under-test experiences an event that causes an update
+to the register.  For example, accessing a non-existant CSR should raise an
+illegal instruction exception which should, in turn, update the value of MCAUSE.
+Therefore a test that checks the PoR value of MCAUSE must not access a non-existant
+CSR before reading MCAUSE.
+
+### Access Mode Behavior
+
+Here, we are trying to answer the question, "how does the CSR behave when it is
+accessed (written to, or read from)?".  In RISC-V cores, CSRs are accessed using
+the `CSRRC`, `CSRRCI`, `CSRRS`, `CSRRSI`, `CSRRW` and `CSRRWI` instructions.  Note
+that there are also seven pseudoinstructions that will expand into one of these
+instructions.  While in the general case a core may provide alternative means to
+access CSRs, in the CV32E40P, these instructions are the only access method available.
+
+Note that when verifying access mode behavior we are not (yet) concerned about
+what the core will do when a given CSR has a specific value.
+
+In RISC-V cores, access mode behavior has four dimensions: access mode,
+privilege, existance and field specification.  These are discussed in turn,
+with emphasis placed on pre-silicon functional verification (as opposed to
+post-silicon use by software).
+
+#### Access Mode
+
+Access modes in RISC-V cores are simple and familar to those with prior experience
+with non-processor core ASIC/FPGA RTL.  In fact, there are only two access modes
+to worry about: RW and RO:
+
+1. RW: all bits of a RW field must be writable and must return the last written
+value upon a read.
+2. RO: no bit of a RO field may be writable and must return the previous value upon
+read, event after being written to by either 0 or 1.
+
+#### Privilege
+
+Of course, nothing is ever _that_ simple with RISC-V.  A core's privilege mode adds
+a second dimension to access mode.  Is it often the case that a CSR that is
+accessible in a high privilege mode does not exist in lower modes. This must also
+be verified.
+
+For the purposes of CSR verification, it is permissible to consider Debug Mode as
+the highest privilege level.
+
+CV32E40P only supports Machine mode, which greatly simplifies the problem.
+
+#### Existance
+
+CSR "existance" is a concept unique to processor core and is not generally seen in
+non-processor ASIC/FPGA RTL designs.  The RISC-V privileged and debug specifications
+define a set of CSRs, including both "required" and "optional" CSRs.  Accessing an
+optional CSR may result in an illegal instruction (which must be veified).  A
+complicating factor is that CSR existance may also be dependent on privlege level.
+For example reading a Debug CSR when the core is not in debug mode results in an
+illegal instruction exception while reading the same register in debug mode
+returns a value.
+
+#### Field Specification
+
+Although the "field specification" may sound familiar to those with a
+non-processor RTL background, the term is used differently in RISC-V where
+"field specification" refers to how software is expected to interact with
+specific fields of specific CSRs.  This has a material impact on the strategy
+used for RTL verification of CSRs.  There are three field specification types:
+
+1. **WPRI**: this field specification defines how software should interact
+with specific "protected" fields.  This software action is wholly independent of RTL
+logic behavior, so WPRI fields may be treated as RO for the purposes of RTL
+functional verification of their access behavior.
+2. **WLRL**: once again, this field specification refers to how software should
+interact with specific RW fields.  The difference is that reads will only return
+_legal_ values on reads, acting as a mask on return values of a RW test.  In all
+other respects, WLRL fields may be treated as RW for the purposes of RTL
+functional verification of their access behavior.
+3. **WARL**: fields may be treated as RW (with read masking) for the purposes of RTL functional
+verification of their access behavior.
+
+
+### Control Actions
+
+CSRs are called Control and Status Registers for a reason.  Control registers will
+change (control) the operation of the device under test in measureable ways and functional
+verification must coverage all legal values (or in some cases, important ranges of
+values) and then check that these values have the desired affect.  A good example
+is ensuring that interrupts are asserted when MSTATUS[MIE] is both 0/1 and ensuring
+that interrupts are ignored or responded to, as appropriate.
+
+Control register verification of RISC-V cores is not conceptually different than
+control register verification of non-processor ASIC/FPGA RTL.  One difference is
+that in non-processor RTL, the control path (reading the writing the CSRs) is
+typically independent of the data path (events that are affected by control
+register values).  In processor cores a program executing on the core acts as both
+the control path (by executing CSR access instructions) and the data path (by
+executing code that is affected by the CSRs).
+
+## CV32E40Pv2 CSR Verification Plan
+Some tests for v1 were missing, and new tests were needed to improve v2 RTL code coverage. For backward-compatibily reasons, tests originated from v1 will be updated to match v2 specifications changes when possible (default/reset values, new mapping for HWLoop registers, etc.).
+
+| Testcase | Targeted Aspect | Type | Origin | Reference | Status |
+|----------|-----------------|------|--------|-----------|--------|
+| ~~por\_csr.c~~ | ~~Power-on-Reset values~~ | ~~Manually written, directed~~ | v1 test not found in verification environment, so note in [1](#1) from v1 has not been completed | N/A | not-available in v2 environment |
+| requested\_por\_csr | Power-on-Reset values | Manually written, directed, self-checking | v1 test adapted to v2 environment | [1](#1) | Complete |
+| modeled\_por\_csr | Power-on-Reset values | Manually written, directed, non-self-checking | v1 test untouched in v2 environment | [1](#1) | Complete |
+| all\_por\_csr | Power-on-Reset values | Scripted, directed, non-sels-checking | v1 test untouched in v2 environment | [1](#1) | Complete |
+| ~~por\_debug\_csr.c~~ | ~~Power-on-Reset values for Debug CSRs~~ | ~~Manually written, directed~~ |  v1 test planned but not found in verification environment | N/A | not-available in v2 environment |
+| csr_instr_asm | Brute force all all legal CSR instructions on MSCRATCH CSR | Scripted, directed, non-self-checking | v1 test adapted to v2 environment | [2](#2) | Complete |
+| csr_instructions | Test once all csr instructions | Manually written, directed, non-self-checking | v1 test adapted to v2 environment | [2](#2) | Complete |
+| ~~csr\_existance.c~~ | ~~Illegal instruction exception for non-existant CSRs~~ | ~~Manually written, directed~~ | v1 test planned but not found in verification environment | N/A | not-available in v2 environment |
+| cv32e40p\_csr\_access_test | Combined access mode behavior and field specification tests for all CSRs | Generated, self-checking | v1 test adapted to v2 environment | [3](#3) | Complete |
+| cv32e40p\_readonly\_csr\_access_test | Combined access mode behavior and field specification tests for all CSRs | Generated | v1 test adapted to v2 environment | [4](#4) | Complete |
+| cv32e40pv2\_illegal\_ro\_csr\_access_test | Combined access mode behavior and field specification tests for all CSRs | Manually written with parts scripted, direct, self-checking | new test for v2 | [5](#5) | Complete |
+| ~~csr\_privlege.c~~ | ~~Debug mode can access all CSRs~~ | ~~Manually written, directed~~ | v1 test planned but not found in verification environment | N/A | not-available in v2 environment |
+
+
+### 1
+At the time of this writting (2020-10-07), this is implemented as two tests, `modeled_csr_por` and `requested_csr_por`.  In the near (?) future these will be combined into a single test.  For each machine-mode CSR in CV32E40P:
+- read current value
+- compare to documented PoR value in User Manual
+
+Failure conditions:
+- any read value does not match documented PoR
+- any illegal instruction exceptions
+
+**Updated note for CV32E40Pv2 (2024-04-03):** These two tests still exist as splitted, and have been updated to match v2 configurations and updates. <br>
+all\_por\_csr was not mentionned in v1 plan but it seems to fill the same purpose.
+
+### 2
+
+**Updated note for CV32E40Pv2 (2024-04-03):** These tests were not mentionned in v1 plan, but existed at the beginning of v2 verification effort. Their behavior is as described in the table : brute-force for all Zicsr instructions, and a shorter version.
+
+### 3
+Access mode test of all CSRs.  This is a generated test based on [cv32e40p_csr_template.yaml](https://github.com/openhwgroup/core-v-verif/blob/master/vendor_lib/google/corev-dv/cv32e40p_csr_template.yaml).
+
+**Updated note for CV32E40Pv2 (2024-04-03):** Due to the high number of CSR R/W accesses to mstatus, only the first few accesses are self-checking in F configurations.
+
+### 4
+Access mode test of all CSRs.  This is a generated test based on [cv32e40p_csr_template.yaml](https://github.com/openhwgroup/core-v-verif/blob/master/vendor_lib/google/corev-dv/cv32e40p_csr_template.yaml).
+
+**Updated note for CV32E40Pv2 (2024-04-03):** Test was missing some registers for v2 verification, it has been left as-is, updated just to run correctly without error with v2 configurations and
+
+### 5
+As explained in [4](#4), this test has been added to fill coverage holes in v2 verification, mainly with missing counters, missing FPU CSR register, and with updated PULP CSRs addresses.
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diff --git a/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx b/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx
new file mode 100644
index 0000000000..62d92ab9aa
Binary files /dev/null and b/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx differ
diff --git a/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx b/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx
new file mode 100644
index 0000000000..5d50813473
Binary files /dev/null and b/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx differ
diff --git a/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx b/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx
new file mode 100644
index 0000000000..d7fa4b4fa3
Binary files /dev/null and b/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx differ
diff --git a/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx b/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx
new file mode 100644
index 0000000000..98ef3c8f31
Binary files /dev/null and b/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx differ
diff --git a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml
index 3400f236b5..d07f83cc23 100644
--- a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml
+++ b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml
@@ -71,9 +71,9 @@ tests:
     num: 1
     skip_sim:
       - pulp
-      - pulp_zfinx
-      - pulp_zfinx_1cyclat
-      - pulp_zfinx_2cyclat
+      - pulp_fpu_zfinx
+      - pulp_fpu_zfinx_1cyclat
+      - pulp_fpu_zfinx_2cyclat
       - pulp_cluster
       - pulp_cluster_fpu
       - pulp_cluster_fpu_1cyclat
diff --git a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml
index 9c8773ebd7..5662ae3e94 100644
--- a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml
+++ b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml
@@ -72,9 +72,9 @@ tests:
     num: 1
     skip_sim:
       - pulp
-      - pulp_zfinx
-      - pulp_zfinx_1cyclat
-      - pulp_zfinx_2cyclat
+      - pulp_fpu_zfinx
+      - pulp_fpu_zfinx_1cyclat
+      - pulp_fpu_zfinx_2cyclat
       - pulp_cluster
       - pulp_cluster_fpu
       - pulp_cluster_fpu_1cyclat
diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv
index a7492f796e..8b32d16195 100644
--- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv
+++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv
@@ -581,6 +581,63 @@ module uvmt_cv32e40p_imperas_dv_wrap
     void'(rvviRefCsrSetVolatile(hart_id, `CSR_INSTRET_ADDR      ));
     void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER3_ADDR      ));
     void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER3H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER4_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER4H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER5_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER5H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER6_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER6H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER7_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER7H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER8_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER8H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER9_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER9H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER10_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER10H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER11_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER11H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER12_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER12H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER13_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER13H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER14_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER14H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER15_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER15H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER16_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER16H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER17_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER17H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER18_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER18H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER19_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER19H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER20_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER20H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER21_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER21H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER22_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER22H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER23_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER23H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER24_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER24H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER25_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER25H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER26_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER26H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER27_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER27H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER28_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER28H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER29_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER29H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER30_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER30H_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER31_ADDR      ));
+    void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER31H_ADDR      ));
+
 
     void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT3_ADDR      ));
     void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT4_ADDR      ));
diff --git a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S
index 3cb4f75898..013ae4ae80 100644
--- a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S
+++ b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S
@@ -810,6 +810,19 @@ main:             fence.i
                   .4byte 0x16794e2b # custom-1 plane B
                   .4byte 0xdd363aab # custom-1 Plane A illegal func7
                   .4byte 0x6667f4fb # custom-3 cv.subrotmj block
+                  .4byte 0xba45807b # custom-3 cv.extract.h illegal imm6
+                  .4byte 0xba5a91fb # custom-3 cv.extract.b illegal imm6
+                  .4byte 0xbad6a0fb # custom-3 cv.extractu.h illegal imm6
+                  .4byte 0xba96b0fb # custom-3 cv.extractu.b illegal imm6
+                  .4byte 0xba1e44fb # custom-3 cv.insert.h illegal imm6
+                  .4byte 0xba2e54fb # custom-3 cv.insert.b illegal imm6
+                  .4byte 0xc288e8fb # custom-3 cv.shuffle.sci.h illegal imm6
+                  .4byte 0x509f6f7b # custom-3 cv.sll.sci.h illegal imm6
+                  .4byte 0x5102727b # custom-3 cv.sll.sci.b illegal imm6
+                  .4byte 0x40c1e8fb # custom-3 cv.srl.sci.h illegal imm6
+                  .4byte 0x404ef6fb # custom-3 cv.srl.sci.b illegal imm6
+                  .4byte 0x4953637b # custom-3 cv.sra.sci.h illegal imm6
+                  .4byte 0x4b1f767b # custom-3 cv.sra.sci.b illegal imm6
                   la x16, test_done
                   jalr x0, x16, 0
 
diff --git a/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S
index 3b4c4c0f47..2c9f86edc1 100644
--- a/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S
+++ b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S
@@ -1,3 +1,5 @@
+# Copyright (c) 2024 Dolphin Design
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 .globl _start
 .globl main
diff --git a/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/test.yaml b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/test.yaml
index ef5b8cece8..40ce6ab7bc 100644
--- a/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/test.yaml
+++ b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/test.yaml
@@ -1,5 +1,7 @@
-# Test definition YAML for test
+# Copyright (c) 2024 Dolphin Design
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
+# Test definition YAML for test
 name: fpu_func_cov_improve_test
 uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c
 description: >
diff --git a/cv32e40p/tests/programs/custom/pulp_vectorial_shuffle_pack/pulp_vectorial_shuffle_pack.S b/cv32e40p/tests/programs/custom/pulp_vectorial_shuffle_pack/pulp_vectorial_shuffle_pack.S
index ad6777b176..e0a5cedc03 100644
--- a/cv32e40p/tests/programs/custom/pulp_vectorial_shuffle_pack/pulp_vectorial_shuffle_pack.S
+++ b/cv32e40p/tests/programs/custom/pulp_vectorial_shuffle_pack/pulp_vectorial_shuffle_pack.S
@@ -108,31 +108,31 @@ test6:
 #cv.shuffle.sci.h is of the form "cv.shuffle.sci.h rD, rs1, Imm6".
 test7:
     li x17, 0x65611a7f
-    cv.shuffle.sci.h x19, x17, 0xb
+    cv.shuffle.sci.h x19, x17, 0x3
     li x20, 0x65616561
     beq x20, x19, test8
     c.addi x15, 0x1
 test8:
     li x17, 0xb03ec1e9
-    cv.shuffle.sci.h x19, x17, 0x5
+    cv.shuffle.sci.h x19, x17, 0x1
     li x20, 0xc1e9b03e
     beq x20, x19, test9
     c.addi x15, 0x1
 test9:
     li x17, 0x656b1acf
-    cv.shuffle.sci.h x19, x17, 0x7
+    cv.shuffle.sci.h x19, x17, 0x3
     li x20, 0x656b656b
     beq x20, x19, test10
     c.addi x15, 0x1
 test10:
     li x17, 0xc8440911
-    cv.shuffle.sci.h x19, x17, 0xc
+    cv.shuffle.sci.h x19, x17, 0x0
     li x20, 0x09110911
     beq x20, x19, test11
     c.addi x15, 0x1
 test11:
     li x17, 0xaf077cef
-    cv.shuffle.sci.h x19, x17, 0xe
+    cv.shuffle.sci.h x19, x17, 0x2
     li x20, 0xaf077cef
     beq x20, x19, test12
     c.addi x15, 0x1
diff --git a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/test.yaml b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/test.yaml
index e41dff3377..cbe67dfeab 100644
--- a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/test.yaml
+++ b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/test.yaml
@@ -1,5 +1,7 @@
-# Test definition YAML for test
+# Copyright (c) 2024 Dolphin Design
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
+# Test definition YAML for test
 name: zfinx_func_cov_improve_test
 uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c
 description: >
diff --git a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S
index 6ce5adab44..fb1df55b06 100644
--- a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S
+++ b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S
@@ -1,3 +1,5 @@
+# Copyright (c) 2024 Dolphin Design
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 .globl _start
 .globl main
diff --git a/mk/Common.mk b/mk/Common.mk
index 1bfaaa2072..8a152be126 100644
--- a/mk/Common.mk
+++ b/mk/Common.mk
@@ -556,6 +556,7 @@ bsp:
 		RISCV_MARCH=$(RISCV_MARCH) \
 		RISCV_CC=$(RISCV_CC) \
 		RISCV_CFLAGS="$(RISCV_CFLAGS)" \
+		CFG_CFLAGS="$(CFG_CFLAGS)" \
 		all
 
 vars_bsp:
diff --git a/mk/uvmt/uvmt.mk b/mk/uvmt/uvmt.mk
index e32b6f71b5..e4664a7feb 100644
--- a/mk/uvmt/uvmt.mk
+++ b/mk/uvmt/uvmt.mk
@@ -62,7 +62,7 @@ MKDIR_P = mkdir -p
 
 # Compile compile flags for all simulators (careful!)
 WAVES        ?= 0
-SV_CMP_FLAGS ?= "+define+$(CV_CORE_UC)_ASSERT_ON"
+SV_CMP_FLAGS ?= +define+$(CV_CORE_UC)_ASSERT_ON
 TIMESCALE    ?= -timescale 1ns/1ps
 UVM_PLUSARGS ?=
 
diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk
index b2636f4f8d..bbbe50d829 100644
--- a/mk/uvmt/vsim.mk
+++ b/mk/uvmt/vsim.mk
@@ -135,15 +135,15 @@ VLOG_FILE_LIST = -f $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC).flist
 VLOG_FLAGS += $(DPILIB_VLOG_OPT)
 
 # Add the ISS to compilation
-VLOG_FLAGS += "+define+$(CV_CORE_UC)_RVFI"
+VLOG_FLAGS += +define+$(CV_CORE_UC)_RVFI
 
 ifeq ($(call IS_YES,$(ENABLE_TRACE_LOG)),YES)
-    VLOG_FLAGS += "+define+$(CV_CORE_UC)_TRACE_EXECUTION"
-    VLOG_FLAGS += "+define+$(CV_CORE_UC)_RVFI_TRACE_EXECUTION"
+    VLOG_FLAGS += +define+$(CV_CORE_UC)_TRACE_EXECUTION
+    VLOG_FLAGS += +define+$(CV_CORE_UC)_RVFI_TRACE_EXECUTION
 endif
 
-VLOG_FLAGS += "+define+$(CV_CORE_UC)_CORE_LOG"
-VLOG_FLAGS += "+define+UVM"
+VLOG_FLAGS += +define+$(CV_CORE_UC)_CORE_LOG
+VLOG_FLAGS += +define+UVM
 ifeq ($(call IS_YES,$(USE_ISS)),YES)
 VLOG_FLAGS += +define+USE_ISS
 VLOG_FLAGS += +define+USE_IMPERASDV