From e1435ec5e0025d21665e9d0fb29fc1100bb6aff2 Mon Sep 17 00:00:00 2001 From: Marton Teilgard Date: Mon, 20 Nov 2023 13:40:32 +0100 Subject: [PATCH 1/4] pushpop_debug_triggers test updated Signed-off-by: Marton Teilgard --- .../pushpop_debug_triggers.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c index aca7c7a4d3..f186c2ff60 100644 --- a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c +++ b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c @@ -33,6 +33,7 @@ volatile uint32_t g_debug_function_setup_triggers = 0; volatile uint32_t g_exception_expected = 0; volatile uint32_t g_pushpop_area [32]; +volatile uint32_t g_pushpop_area_index = 0; void disable_debug_req(void) { CV_VP_DEBUG_CONTROL = ( @@ -111,7 +112,7 @@ void debug_start(void) { )"); } -static void setup_triggers(void){ +static void setup_triggers(int index){ mcontrol6_t mcontrol6; uint32_t trigger_addr; @@ -122,7 +123,7 @@ static void setup_triggers(void){ mcontrol6.fields.match = 0; // (match exact address) mcontrol6.fields.type = 6; - trigger_addr = (uint32_t) &(g_pushpop_area[2]); // (arbitrary index) + trigger_addr = (uint32_t) &(g_pushpop_area[index]); // (arbitrary index) __asm__ volatile( R"( @@ -180,7 +181,7 @@ void debug_handler(void){ if (g_debug_function_setup_triggers) { g_debug_function_setup_triggers = 0; - setup_triggers(); + setup_triggers(g_pushpop_area_index); return; } if (g_debug_function_incr_dpc) { @@ -238,12 +239,13 @@ static void pop_debug_trigger(void){ ); } -static void let_dmode_setup_triggers(void){ +static void let_dmode_setup_triggers(int index){ printf("setup trigs\n"); g_debug_expected = 1; g_debug_entered = 0; g_debug_function_setup_triggers = 1; + g_pushpop_area_index = index; // arbitrary index // Prolonged pulse duration so debug req has a chance to be acked and taken CV_VP_DEBUG_CONTROL = ( @@ -293,7 +295,13 @@ static void test_pop_debug_trigger(void){ } int main(int argc, char **argv){ - let_dmode_setup_triggers(); + let_dmode_setup_triggers(2); + test_push_debug_trigger(); + test_pop_debug_trigger(); + let_dmode_setup_triggers(1); // trigger at first address + test_push_debug_trigger(); + test_pop_debug_trigger(); + let_dmode_setup_triggers(3); // trigger at last address //TODO find address test_push_debug_trigger(); test_pop_debug_trigger(); From 0e8e41239a8c0beca2f8c246b71f7c374f15c443 Mon Sep 17 00:00:00 2001 From: Marton Teilgard Date: Thu, 23 Nov 2023 13:22:42 +0100 Subject: [PATCH 2/4] updated tests for push/pop vs PMA exceptions and haltreq during instruction excecution Signed-off-by: Marton Teilgard --- .../Zc/RV32Zc_Extension_Instructions.csv | 10 +- .../Zc/RV32Zc_Extension_Instructions.json | 10 +- .../Zc/RV32Zc_Extension_Instructions.xlsx | Bin 307761 -> 308036 bytes .../debug-trace/CV32E40XS_debug.csv | 5 +- .../debug-trace/CV32E40XS_debug.json | 4 +- .../debug-trace/CV32E40XS_debug.xlsx | Bin 50376 -> 50531 bytes .../programs/custom/debug_test2/debug_test2.c | 117 ++++++++++++++- cv32e40s/tests/programs/custom/pma/pma.c | 139 ++++++++++++++++-- 8 files changed, 257 insertions(+), 28 deletions(-) diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv index 5bb219791d..4ebef3b9c9 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv +++ b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv @@ -82,7 +82,7 @@ Note: this functionality is closely matched with items mentioned in other featur Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. (the order might change) -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,DTC: pma,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,cm.pop,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, @@ -95,7 +95,7 @@ Note: this functionality is closely matched with items mentioned in other featur Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,DTC: pma,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,cm.popret,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, @@ -107,7 +107,7 @@ Note: this functionality is closely matched with items mentioned in other featur Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"""push"" and ""pop"" instructions tested, testing every type of instruction is deprioritized",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,cm.popretz,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, @@ -119,7 +119,7 @@ Note: this functionality is closely matched with items mentioned in other featur Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,"""push"" and ""pop"" instructions tested, testing every type of instruction is deprioritized",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,cm.mva01s,Move a0-a1 into two registers of s0-s7,"Verify all possible variatons of sreg1, sreg2. Note that sreg1 = sreg2 is illegal",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, @@ -141,7 +141,7 @@ Note: this functionality is closely matched with items mentioned in other featur Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"""push"" and ""pop"" instructions tested, testing every type of instruction is deprioritized",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,"Zcmt diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json index cb0c943680..40230e39d9 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json +++ b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json @@ -332,7 +332,7 @@ "Pass/Fail Criteria": "Check against ISS", "Test Type": "Directed Non-Self-Checking", "Coverage Method": "Testcase", - "Link to Coverage": "Coverage hole, evaluate priority", + "Link to Coverage": "DTC: pma", "": "" }, { @@ -404,7 +404,7 @@ "Pass/Fail Criteria": "Check against ISS", "Test Type": "Directed Non-Self-Checking", "Coverage Method": "Testcase", - "Link to Coverage": "Coverage hole, evaluate priority", + "Link to Coverage": "DTC: pma", "": "" }, { @@ -464,7 +464,7 @@ "Pass/Fail Criteria": "Check against ISS", "Test Type": "Directed Non-Self-Checking", "Coverage Method": "Testcase", - "Link to Coverage": "Coverage hole, evaluate priority", + "Link to Coverage": "\"push\" and \"pop\" instructions tested, testing every type of instruction is deprioritized", "": "" }, { @@ -524,7 +524,7 @@ "Pass/Fail Criteria": "Check against ISS", "Test Type": "Constrained-Random", "Coverage Method": "Functional Coverage", - "Link to Coverage": "Coverage hole, evaluate priority", + "Link to Coverage": "\"push\" and \"pop\" instructions tested, testing every type of instruction is deprioritized", "": "" }, { @@ -620,7 +620,7 @@ "Pass/Fail Criteria": "Check against ISS", "Test Type": "Directed Non-Self-Checking", "Coverage Method": "Testcase", - "Link to Coverage": "Coverage hole, evaluate priority", + "Link to Coverage": "\"push\" and \"pop\" instructions tested, testing every type of instruction is deprioritized", "": "" }, { diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx index 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z$IlA+AV$Qr$+vsZpuX+-MugP6ss(L25mbZULxwX3c+tc8`SPkjraZq{EE}bPs=qVhws)*mtnC476Ad5c(DW^9F(4V zB`*sA0Cgk)02BZK00000000000000@l9#lx1V96>odlQOo&+S98?po{1F)V1m*AfS zD3@@u1P~mSwHD=-0RRB?0ssIJ0000000000000000Pv-koU#Nx0=%e~+p+{a1fZ(~ V0GH9M1QVAovjh+ZD6Rwm006tXc0K?A diff --git a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv index 612e81ec78..a5e792d808 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv +++ b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv @@ -397,9 +397,8 @@ Machine Status Registers",MPRV,,"""dcsr.mprven"" is WARL 1. Since ""mprven"" is 1, then ""mstatus.MPRV"" always takes effect in D-mode.","Read ""dcsr.mprven"", check that it is always 1. 40S, be in debug mode, have ""mstatus.MPRV"" disabled, check that all instructions are treated as M-mode. Be in debug mode, have ""mstatus.MPRV"" enabled, have ""mstatus.MPP"" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.",Assertion Check,Other,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mprven_tied,?,?,? -Silabs Internal,,Instruction boundaries,Haltreq and stepping,"External debug requests and single stepping can only cause debug entry on ""instruction boundaries"", so a multi-step instruction cannot be interrupted by this.","While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.",Self Checking Test,Directed Self-Checking,Testcase,TODO: not covered,?,?,? -Debug 1.0.0,,Instruction boundaries,Synchronous entry,"Trigger matching can cause synchronous debug entry, and can interrupt ""within"" and instruction.","Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted ""midway"" and that debug mode is entered correctly.",Self Checking Test,Directed Self-Checking,Testcase,"DTC: pushpop_debug_triggers -TODO: Increase coverage by checking triggers at first/last operation",?,?,? +Silabs Internal,,Instruction boundaries,Haltreq and stepping,"External debug requests and single stepping can only cause debug entry on ""instruction boundaries"", so a multi-step instruction cannot be interrupted by this.","While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2""",?,?,? +Debug 1.0.0,,Instruction boundaries,Synchronous entry,"Trigger matching can cause synchronous debug entry, and can interrupt ""within"" and instruction.","Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted ""midway"" and that debug mode is entered correctly.",Self Checking Test,Directed Self-Checking,Testcase,DTC: pushpop_debug_triggers,?,?,? "RISC-V External Debug Support Version 0.13.2 CV32E40P doc rev 46711ac","4.8.1 DCSR diff --git a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json index cb69096e03..fc4be8661c 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json +++ b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json @@ -1644,7 +1644,7 @@ "Pass/Fail Criteria": "Self Checking Test", "Test Type": "Directed Self-Checking", "Coverage Method": "Testcase", - "Link to Coverage": "TODO: not covered", + "Link to Coverage": "Covered in DTC \"debug_test2\"", "Review (Marton)": "?", "Review (Robin)": "?", "Review (Henrik)": "?" @@ -1659,7 +1659,7 @@ "Pass/Fail Criteria": "Self Checking Test", "Test Type": "Directed Self-Checking", "Coverage Method": "Testcase", - "Link to Coverage": "DTC: pushpop_debug_triggers\nTODO: Increase coverage by checking triggers at first/last operation", + "Link to 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6795dad584..3a6696acba 100644 --- a/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c +++ b/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c @@ -33,7 +33,7 @@ // MUST be 31 or less (bit position-1 in result array determines test pass/fail // status, thus we are limited to 31 tests with this construct. -#define NUM_TESTS 19 +#define NUM_TESTS 21 // Start at 1 (ignore dummy test that is only used for env sanity checking during dev.) #define START_TEST_NUM 1 // Abort test at first self-check fail, useful for debugging. @@ -379,6 +379,8 @@ volatile uint32_t * volatile g_trigger_matched; volatile uint32_t * volatile g_has_clic; volatile uint32_t * volatile g_single_step_unspec_err; +volatile uint32_t g_pushpop_area [64]; + extern volatile uint32_t *trigger_loc; extern volatile uint32_t *trigger_loc_dbg; extern volatile uint32_t *trigger_exit; @@ -465,6 +467,8 @@ uint32_t check_stopcnt_bits(uint32_t index, uint8_t report_name); uint32_t single_step(uint32_t index, uint8_t report_name); uint32_t mprv_dret_to_umode(uint32_t index, uint8_t report_name); uint32_t cover_known_iss_mismatches(uint32_t index, uint8_t report_name); +uint32_t push_haltreq(uint32_t index, uint8_t report_name); +uint32_t pop_haltreq(uint32_t index, uint8_t report_name); // --------------------------------------------------------------- // Prototypes for functions that are test specific and @@ -621,7 +625,7 @@ int main(int argc, char **argv){ setup_clic(); // Add function pointers to new tests here - tests[0] = dummy; // unused, can be used for env sanity checking + tests[0] = dummy; // unused, can be used for env sanity checking tests[1] = debug_csr_rw; tests[2] = trigger_default_val; tests[3] = ebreak_behavior_m_mode; @@ -640,6 +644,8 @@ int main(int argc, char **argv){ tests[16] = single_step; tests[17] = mprv_dret_to_umode; tests[18] = cover_known_iss_mismatches; + tests[19] = push_haltreq; + tests[20] = pop_haltreq; // Run all tests in list above cvprintf(V_LOW, "\nDebug test start\n\n"); @@ -1134,6 +1140,113 @@ uint32_t request_ebreak_3x(uint32_t index, uint8_t report_name) { // ----------------------------------------------------------------------------- +uint32_t push_haltreq(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 15 + }; + + *g_debug_test_num = 1; + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + __asm__ volatile( + R"( + # Save old "sp" + mv t0, sp + + # Setup temporary "sp" + la sp, g_pushpop_area + addi sp, sp, 64 + + # Push to temporary "sp" + cm.push {x1, x8-x9, x18-x27}, -64 + + # Restore old "sp" + mv sp, t0 + )"::: "t0" + ); + + test_fail += *g_debug_status > 1 ? 1 : 0; + *g_debug_status = 0; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + + +// ----------------------------------------------------------------------------- + +uint32_t pop_haltreq(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 25 + }; + + *g_debug_test_num = 1; + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + __asm__ volatile( + R"( + # Save old "sp" and GPRs + cm.push {x1, x8-x9}, -16 + mv t0, sp + + # Setup temporary "sp" + la sp, g_pushpop_area + + # Pop from temporary "sp" + cm.pop {x1, x8-x9, x18-x27}, 64 + + # Restore old "sp" and GPRs + mv sp, t0 + cm.pop {x1, x8-x9}, 16 + )"::: "t0" + ); + + test_fail += *g_debug_status > 1 ? 1 : 0; + *g_debug_status = 0; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} +// ----------------------------------------------------------------------------- + __attribute__((naked)) void m_fast14_irq_handler(void) { __asm__ volatile ( R"( diff --git a/cv32e40s/tests/programs/custom/pma/pma.c b/cv32e40s/tests/programs/custom/pma/pma.c index 36f0e99274..24a6b2f829 100644 --- a/cv32e40s/tests/programs/custom/pma/pma.c +++ b/cv32e40s/tests/programs/custom/pma/pma.c @@ -31,7 +31,7 @@ // MUST be 31 or less (bit position-1 in result array determines test pass/fail // status, thus we are limited to 31 tests with this construct. -#define NUM_TESTS 9 +#define NUM_TESTS 11 // Start at 1 (ignore dummy test that is only used for env sanity checking during dev.) #define START_TEST_NUM 1 // Abort test at first self-check fail, useful for debugging. @@ -160,6 +160,8 @@ uint32_t misaligned_border_io_to_mem(uint32_t index, uint8_t report_name); uint32_t misaligned_border_mem_to_io(uint32_t index, uint8_t report_name); uint32_t misalign_store_fault_no_bus_access_second(uint32_t index, uint8_t report_name); uint32_t misalign_store_fault_io_no_bus_access_first(uint32_t index, uint8_t report_name); +uint32_t push_border(uint32_t index, uint8_t report_name); +uint32_t pop_border(uint32_t index, uint8_t report_name); // --------------------------------------------------------------- // Prototypes for functions that are test specific and @@ -218,6 +220,11 @@ int cvprintf(verbosity_t verbosity, const char *format, ...) __attribute((__noin // Test entry point // --------------------------------------------------------------- int main(int argc, char **argv){ + // need to use a different stack for the exception handlers, due to testing push/pop + __asm__ volatile (R"( + la t0, __debugger_stack_start + csrw mscratch, t0 + )"); volatile uint32_t (* volatile tests[NUM_TESTS])(volatile uint32_t, volatile uint8_t); volatile uint32_t test_res = 0x1; @@ -237,15 +244,17 @@ int main(int argc, char **argv){ setup_clic(); // Add function pointers to new tests here - tests[0] = dummy; // unused, can be used for env sanity checking - tests[1] = exec_only_for_main_regions; - tests[2] = non_natural_aligned_store_to_io; - tests[3] = non_natural_aligned_loads_from_io; - tests[4] = misaligned_fault_nochange_regfile; - tests[5] = misaligned_border_io_to_mem; - tests[6] = misaligned_border_mem_to_io; - tests[7] = misalign_store_fault_no_bus_access_second; - tests[8] = misalign_store_fault_io_no_bus_access_first; + tests[0] = dummy; // unused, can be used for env sanity checking + tests[1] = exec_only_for_main_regions; + tests[2] = non_natural_aligned_store_to_io; + tests[3] = non_natural_aligned_loads_from_io; + tests[4] = misaligned_fault_nochange_regfile; + tests[5] = misaligned_border_io_to_mem; + tests[6] = misaligned_border_mem_to_io; + tests[7] = misalign_store_fault_no_bus_access_second; + tests[8] = misalign_store_fault_io_no_bus_access_first; + tests[9] = push_border; + tests[10] = pop_border; // Run all tests in list above cvprintf(V_LOW, "\nPMA test start\n\n"); for (volatile uint32_t i = START_TEST_NUM; i < NUM_TESTS; i++) { @@ -750,6 +759,108 @@ uint32_t misaligned_border_mem_to_io(uint32_t index, uint8_t report_name) { // ----------------------------------------------------------------------------- +uint32_t push_border(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile uint32_t io_addr = 0x1a111000; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_test_num = index; + + *g_exp_fault = 1; + + __asm__ volatile(R"( + # Save old "sp" + mv t0, sp + + # Setup temporary "sp" push should pass IO border + mv sp, %[addr] + addi sp, sp, 8 + + # Push to temporary "sp" + cm.push {x1, x8-x9}, -16 + + # Restore old "sp" + mv sp, t0 + )" + :: [addr] "r"(io_addr) + : "t0", "memory" + ); + + + test_fail += *g_exp_fault; + //test_fail += g_mcause->raw != 0; + //test_fail += *g_mepc != 0; + //test_fail += *g_mtval != 0; + clear_status_csrs(); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + + +// ----------------------------------------------------------------------------- + +uint32_t pop_border(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile uint32_t io_addr = 0x1a110810; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_test_num = index; + + *g_exp_fault = 1; + + __asm__ volatile( + R"( + # Save old "sp" and GPRs + cm.push {x1, x8-x9}, -16 + mv t0, sp + + # Setup temporary "sp" pop should pass IO border + mv sp, %[addr] + addi sp, sp, -8 + + # Pop from temporary "sp" + cm.pop {x1, x8-x9}, 16 + + # Restore old "sp" and GPRs + mv sp, t0 + cm.pop {x1, x8-x9}, 16 + )" + :: [addr] "r"(io_addr) + : "t0", "memory" + ); + + test_fail += *g_exp_fault; + //test_fail += g_mcause->raw != 0; + //test_fail += *g_mepc != 0; + //test_fail += *g_mtval != 0; + clear_status_csrs(); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} +// ----------------------------------------------------------------------------- + uint32_t misalign_store_fault_no_bus_access_second(uint32_t index, uint8_t report_name) { volatile uint32_t test_fail = 0; volatile uint32_t io_addr = 0x1a110810; @@ -1055,6 +1166,9 @@ uint32_t detect_irq_mode(void) { void __attribute__((naked)) u_sw_irq_handler(void) { __asm__ volatile (R"( .extern u_sw_irq_handler_normal + + csrrw sp, mscratch, sp + cm.push {ra, s0-s11}, -112 addi sp, sp, -12 @@ -1116,6 +1230,9 @@ void __attribute__((naked)) u_sw_irq_handler(void) { # Restore stack ptr addi sp, sp, 12 cm.pop {ra, s0-s11}, 112 + + csrrw sp, mscratch, sp + mret )"); @@ -1146,7 +1263,7 @@ void u_sw_irq_handler_normal(void) { csrrw zero, mepc, t0 )" ::: "t0", "memory"); } - else if (*g_test_num >= 2 && *g_test_num <= 9) { + else if (*g_test_num >= 2 && *g_test_num <= 11) { increment_mepc(0); if (*g_exp_fault) { *g_exp_fault = 0; From 61e704fa244978c0076a0238ce217eb2fcc8189c Mon Sep 17 00:00:00 2001 From: Marton Teilgard Date: Tue, 28 Nov 2023 12:37:24 +0100 Subject: [PATCH 3/4] fixed PR feedback Signed-off-by: Marton Teilgard --- cv32e40s/tests/programs/custom/pma/pma.c | 6 ------ .../custom/pushpop_debug_triggers/pushpop_debug_triggers.c | 2 +- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/cv32e40s/tests/programs/custom/pma/pma.c b/cv32e40s/tests/programs/custom/pma/pma.c index 24a6b2f829..52dabc85fc 100644 --- a/cv32e40s/tests/programs/custom/pma/pma.c +++ b/cv32e40s/tests/programs/custom/pma/pma.c @@ -794,9 +794,6 @@ uint32_t push_border(uint32_t index, uint8_t report_name) { test_fail += *g_exp_fault; - //test_fail += g_mcause->raw != 0; - //test_fail += *g_mepc != 0; - //test_fail += *g_mtval != 0; clear_status_csrs(); if (test_fail) { @@ -847,9 +844,6 @@ uint32_t pop_border(uint32_t index, uint8_t report_name) { ); test_fail += *g_exp_fault; - //test_fail += g_mcause->raw != 0; - //test_fail += *g_mepc != 0; - //test_fail += *g_mtval != 0; clear_status_csrs(); if (test_fail) { diff --git a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c index f186c2ff60..1ecfc64691 100644 --- a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c +++ b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c @@ -301,7 +301,7 @@ int main(int argc, char **argv){ let_dmode_setup_triggers(1); // trigger at first address test_push_debug_trigger(); test_pop_debug_trigger(); - let_dmode_setup_triggers(3); // trigger at last address //TODO find address + let_dmode_setup_triggers(3); // trigger at last address test_push_debug_trigger(); test_pop_debug_trigger(); From 50b499ef7de3d399d17661215e7a0eece271b331 Mon Sep 17 00:00:00 2001 From: Marton Teilgard Date: Wed, 29 Nov 2023 14:12:37 +0100 Subject: [PATCH 4/4] Fixed debug test selfchecking Signed-off-by: Marton Teilgard --- .../programs/custom/debug_test2/debug_test2.c | 20 +++++++++++++++---- .../pushpop_debug_triggers.c | 8 ++++---- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c b/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c index 3a6696acba..27a9cc7110 100644 --- a/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c +++ b/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c @@ -1160,7 +1160,8 @@ uint32_t push_haltreq(uint32_t index, uint8_t report_name) { .fields.start_delay = 15 }; - *g_debug_test_num = 1; + *g_debug_test_num = 19; + *g_debug_status = 0; DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; __asm__ volatile( @@ -1180,7 +1181,7 @@ uint32_t push_haltreq(uint32_t index, uint8_t report_name) { )"::: "t0" ); - test_fail += *g_debug_status > 1 ? 1 : 0; + test_fail += *g_debug_status == 1 ? 0 : 1; *g_debug_status = 0; if (test_fail) { @@ -1214,7 +1215,8 @@ uint32_t pop_haltreq(uint32_t index, uint8_t report_name) { .fields.start_delay = 25 }; - *g_debug_test_num = 1; + *g_debug_test_num = 20; + *g_debug_status = 0; DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; __asm__ volatile( @@ -1235,7 +1237,7 @@ uint32_t pop_haltreq(uint32_t index, uint8_t report_name) { )"::: "t0" ); - test_fail += *g_debug_status > 1 ? 1 : 0; + test_fail += *g_debug_status == 1 ? 0 : 1; *g_debug_status = 0; if (test_fail) { @@ -1568,6 +1570,10 @@ void __attribute__((naked)) _debugger_start(void) { beq s0, s1, 14f addi s0, zero, 18 beq s0, s1, 18f + addi s0, zero, 19 + beq s0, s1, 19f + addi s0, zero, 20 + beq s0, s1, 20f # no match, exit beq zero, zero, 99f @@ -1611,6 +1617,12 @@ void __attribute__((naked)) _debugger_start(void) { 18: call cover_known_iss_mismatches_dbg beq zero, zero, 99f + 19: call request_hw_debugger_dbg + beq zero, zero, 99f + + 20: call request_hw_debugger_dbg + beq zero, zero, 99f + 99: call _debugger_end dret diff --git a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c index 1ecfc64691..e0881c7e25 100644 --- a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c +++ b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c @@ -123,7 +123,7 @@ static void setup_triggers(int index){ mcontrol6.fields.match = 0; // (match exact address) mcontrol6.fields.type = 6; - trigger_addr = (uint32_t) &(g_pushpop_area[index]); // (arbitrary index) + trigger_addr = (uint32_t) &(g_pushpop_area[index]); __asm__ volatile( R"( @@ -245,7 +245,7 @@ static void let_dmode_setup_triggers(int index){ g_debug_expected = 1; g_debug_entered = 0; g_debug_function_setup_triggers = 1; - g_pushpop_area_index = index; // arbitrary index + g_pushpop_area_index = index; // Prolonged pulse duration so debug req has a chance to be acked and taken CV_VP_DEBUG_CONTROL = ( @@ -298,10 +298,10 @@ int main(int argc, char **argv){ let_dmode_setup_triggers(2); test_push_debug_trigger(); test_pop_debug_trigger(); - let_dmode_setup_triggers(1); // trigger at first address + let_dmode_setup_triggers(1); // trigger at last address in actual sequence test_push_debug_trigger(); test_pop_debug_trigger(); - let_dmode_setup_triggers(3); // trigger at last address + let_dmode_setup_triggers(3); // trigger at first address in actual sequence test_push_debug_trigger(); test_pop_debug_trigger();