diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv
index 63683ff06a..ff2ed0e205 100644
--- a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv
+++ b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv
@@ -14,7 +14,7 @@ UM v0.3.0 Common,Constraints,Privilege Modes,CLIC interrupts only support machin
 Assume on input for formal",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_clic_mode_only
 UM v0.3.0 Common,Constraints,NMI,"NMI address is located at the 15th entry in the machine trap vector table, located at mtvec. In other words, nmi_addr = { mtvec[31:7], 5'b0_1111, 2'b00 }","Assert that nmi addr = { mtvec[31:7], 5'b0_1111, 2'b00 }",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_nmi_to_mtvec_offset
 UM v0.3.0 Common,Constraints,Interrupts,Support up to a maximum of 1024 CLIC interrupts,Assert that SMCLIC_ID_WIDTH is inside { 1 .. 10 },Assertion Check,"ENV capability, not specific test",Functional Coverage,a_clic_valid_setting
-UM v0.3.0 Common,Constraints,Interrupts,Interrupt levels inside { 0 .. 255 },Correct functionality of interrupts of all valid levels,Check against RM,Constrained-Random,Functional Coverage,"Missing covergroup, vc should use all interrupt levels"
+UM v0.3.0 Common,Constraints,Interrupts,Interrupt levels inside { 0 .. 255 },Correct functionality of interrupts of all valid levels,Check against RM,Constrained-Random,Functional Coverage,clic_cg.cp_lvl
 UM v0.3.0 Common,Constraints,Input ports,irq_i[31:0] tied to zero,Assert that non-clic irq[31:0] signals are tied to 0,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_tieoff_zero_irq_i
 Silabs Internal,Eventually taken,Interrupt taken,"An interrupt that is both pending and enabled shall be taken, unless if the core is in debug mode or is blocked by external interfaces (rvalid, fence_flush_ack, etc), and the taking happens within a fixed number of cycles","Check that when conditions are right, then the interrupt gets taken within expected time",Assertion Check,"ENV capability, not specific test",Functional Coverage,"Waived on top level verification due to lack of visibility and precise specification of what prevents interrupts from being taken, and there exist no definite bound. 
 
diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json
index 31fe7aaf06..8eda35f479 100644
--- a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json
+++ b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json
@@ -85,7 +85,7 @@
         "Pass/Fail Criteria": "Check against RM",
         "Test Type": "Constrained-Random",
         "Coverage Method": "Functional Coverage",
-        "Link to Coverage": "Missing covergroup, vc should use all interrupt levels"
+        "Link to Coverage": "clic_cg.cp_lvl"
     },
     {
         "Requirement Location": "UM v0.3.0 Common",
diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx
index 73ee087bab..49e6523ea6 100644
Binary files a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx and b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx differ
diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv
index e07db9b452..348fe5807a 100644
--- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv
+++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv
@@ -780,6 +780,13 @@ module uvmt_cv32e40s_clic_interrupt_assert
     end
   end
 
+  covergroup cg_clic @(posedge clk_i);
+    option.per_instance = 1;
+    cp_lvl: coverpoint irq_level{ bins values[] = {[0:255]};}
+  endgroup
+
+  cg_clic clic_cg = new;
+
 
   assign core_not_in_debug            = debug_running;
   assign core_in_debug                = !core_not_in_debug;