From b02c745153ae3aa0289110b5c6f1c8548a055922 Mon Sep 17 00:00:00 2001 From: bsm Date: Mon, 30 Oct 2023 11:17:55 +0800 Subject: [PATCH 01/97] Add fp testcases information into verif plan Signed-off-by: bsm --- .../CV32E40P_F-Zfinx-instructions.xlsx | Bin 27887 -> 46488 bytes .../CV32E40P_FPU_register_file.xlsx | Bin 21281 -> 13978 bytes 2 files changed, 0 insertions(+), 0 deletions(-) diff --git a/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40P_F-Zfinx-instructions.xlsx b/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40P_F-Zfinx-instructions.xlsx index b5cf28e4bfeaf458176106f2cb752c6acb2a9ffa..dc6b1124d672a9729bd62c69fdaf990ab606409c 100644 GIT binary patch literal 46488 zcmbSyQ;=xAx^3IGd$n!b-K%Zewr$(CZQJf%ZQHhW*T46!I=61s*$;O>h(fB-EoiwQ`Sl&30I-Pjt%uST#zs1u2?YH7R3rTG8Bki zbL4&=gg-Jc&OAKkCDWdz#TN!?Zy=n|7OH5g#|<+wB`s5QGt~QIed5lM>jQV1$nzbHdAIE!>fu1zCK>+fX490&j$^k^H4miBa$1+!46VK@-`gMZEHchf zU7TUcYo8zvP4VYx0*yNu-t}#8UV#P5ZDN-#`;10ge47lTC3e^-G`;Pf6@>eiRX6plPMs z1)FI8U3zkaKUGko`cUx(@(*-T5x{E?e}Osvuh60V8#+fbeFtMBMJESy8&k)Bkh}8U zaM%!SIsJHxpzXAXh;Z)@R^^C@H4qOs(QFWH$TCu*MS)=cJw)8ME2!|$^kcB{?f*dZ zA^V(~)vN;ii(G!b0B6l^q(&G?AaAbwx>e`vtMbT+@R%{;i+gvyV*& zL;4DYSF})tJF@6%#E>HKtjO3*qm`xkYd76)fcf`x4(xiMDIx49pTe7lwz+GRDW4bq z2cMU0?OL>H3$Sgdy#eO*Q6v7$5q>%TcsUHx9jVhL$nlRi)!W_&8n4rApxC_3{O^YA z?%$yXnIG_};V=f*QroL`t&Y=K<5p;*;caQ+qpf87Q!+@Hpm(g2XyA-4guWwSOP-i- zIkkFJK2TSX7v-)JQ=Sf5-m^aOiF>e#-#y@gfG9ve{yITZ~6 z!fMq9v?8ZXK#+6C84^$848tUa?RpD##fPW;sM_cfcO>9$rTsi>LK}XE103v(*n~Hb z&C;T&-Q5Sj6C83#Ulg2;G;VmzAwPrOqi z?P=uAg!twP#1~>{CG(sGkh@oh?s-pruex|0ha}S{E|{~sS(}R&{ke5;LJ1Jg|Ipb$ z_QiN}TWT!*KGe`=Jw2<(?Kf%!ypxF3aVJYA>ft{mxvR-bF2@v$O|QzhUXXs?QiJLh z)-@mo)=LliMGLxl`df9Nbg#K?m^m8&s3tocMeJxa0+d&n81B!*W`ti0jjhQX#IjR@ z8hr`qW~vo|6XS9X6#{-S;55k4kxIfqql)GJEdLJTI7WCgKTASQrbLob5sdh34TuE- zsR2x7PMi{uJ7(mt8jv4T8Y_yNHjxJxjKV7?9lzt~a?oM9sRIvb= z(}j(a&?9{9UWVOkzTghZraW)h@N+E}tcHmG?BIuc@P^V^p6&Fbd@v-vvqnKhbOxY{ z>VQgg;O9|(P(mLNgQS+Ex>2)fQI2m!$b&jraG1ZWxxtF)nFmJq0-qpGL%8hya18f< z9&}^VIrNQL$8Se7KiYBL816aT@XI9jwLM6_R&%9>s6j4lA8N z@%^>zBj0L!*jRn=gU$Wy;TT}Wmk((ADCdncYv7T5Y|?Nkx|yZKIzbr{4CaTv&j7!a zr$%7W0Ymk9D}f(arQ_mvnIKL+R!<#&;S*nHFTyf=X98?$zSh!z=;HYcHi_vq0+hlQ z!+`L9o-7>lDL~Gg8hFwCF81ptUW^2+aDYr5BL?3SFY_(V!|EdvI$M2>U|7B2p95lM z*D!KM%u|F=!63)S9DQ>}MH$R~Bc5-Morx4}af zP2$FOUE1@MNJ#&ZnNpLzn$l{=7uozity2}${W?u+#I&frJYR}QJ9Rq9H?vbe2=6OA zEz!^7cg5(Q_Y-p7V3AAXLm6{^)siH}__8IbNu(rUHoOjtrsudokc_|1MfPdYiP zQh{2PFawrJU+l$MGQ#!iT-Q&i;wJlUskq${ddTE!(; z4R|UrUC_@oEbso$XR5|D^rtcJAw@yN81VW^C37hIGsqNTIa?M<-yQ&8xH7v!xVBUv zs+Y(GTW=nvHG*Km@;RWY+$r6KGtUfV$ABN$uFO+{J5*_^r)}X z2NB)XC+Kdzavy@R37+su**@D+bZg!5+xM@|V>;DT{5GVSbh7DT<##}l&5YUdk|e#3 zuMn#8bN)X_ZFeI6fJUx$Fjn%Cf!S3aL(Eut4!0C-$_3H&9ogmrUbHv$4&gbq+x|cw zYq=$gUAw>!`wr)VYs7j9+n*Kb!@Ux~LFV%i-C$L|#3H}M_+1>+;hUaGc9-dV(>*Qd zc-IU+s>prE;txC?lYjp{W;Ks$=D#>qSh)a|xc~)1^$*Lqf%FtjChM!`+Ls5rL_Z8% zctJIpmt`uEU(t$d*}KR{YntBb2q|Z90B!8HaOlly|CElR^P)ch$`1lypo0W_4ZI}* zU~Uftc_HUCEB1dk6sqwfLhprAf6@cmD_!W-&2I5A-f+GnfBm8~qe<3xQ7i3SRQvhJ{lTrp1K2FI zO!e)#(~|SKwPodhI(lz>wPq(Wo8*>M^6KSXzR$0>y1UqLL~tDkBH3R5JyEzE2|abY z`Eg7)t@}3S^%Q|QsmY8!Z5-0ArBuObGj%}`v>8T4E>k#dfV3uugO7(7p;Nj=&s?2r zjRj0O)tX2lrLaq<<>$s69iVc9)ZzB9HJ^+<@3r&U{5B~KIp#Ok(C!8!jAy4pC~gax zAk9yumrRobNI{CRs$=paTba;`-zIA_H+4W%kAZLpBfRAny`dD30uo?I$5j+FJgNqXkr4Z>Nfk zCf`p!>OXH}E3c{OB`_`kHQ!AI0t1C2?YEkmx2BRqp%WsXK6M+Cjh#cR$?qEQq_gAa zIR;jDjxP7T>C#3$GzzC&!%B2;6iDSgzlp@LxK}}DE zR=B$32bKq-O$2UiF^ZpjbO=ss6F0Uk^e|o+kBy5OEFm1co|e5MMYIowwT{iLBmvp` z`%g^~Y-IuKAl7_Nym~r2#2-X{L$r!Zn`5qiDRka-hlDOJKKK~Ij6_Sun!d@rCr*AZ zKi{H&VEjqtt|(dx=TcE&8bMddRth`58jW79br~QhOfZLs3-`rGG+lH>1&>ZnWp8k; zBodoS(l%K;Pa7#s$CVbDW9suMX#)Y%>uH61X^mGREe>-(|8y9w=NLOLqKlES>V7WQ zp=~_=vJm7oeV!Mw2*eu%Dxc9k!Pg28469J+y%1xDpqWYB3svR8&}n&lMeRNEN|6#Q z1LHSS&{0HX1bE|TpfjYppvdpU$wm`-(((*J9wM^5G=6Es5gF5(Y~wtlBXp9t5YVKwFHk2ZEyh2-DYO^pytwmnH(S zjLkI(kp)fDQ9n&r9RT2NVa_i=`c8&iq+q_mBO4g3*-L;!ke^{ZInNrkqHFuw?r)q` zaFO3_M|7OCKsDCir}mJl*YL9bU<`<%@y%4NzPmh^Y1oAQ@Z5a2 zi5KStK&cfM9mNZ=&B4lWEV*G}3tx)ziZL+fSVv-)R?!KiI!s_seI;2lqz!P-tZ7NG z%u)}QWf4}WRqg6mS)=VXsP#)qD*B<^B_e4uT6NSe!>noFtqBl)(1NA-%0ThjBnULA z2JKx3Vk&frqjeN@T9Z@c^vNJza70Ht#^Jz>bFOil+K}hgM=hi)Oa*QddPFO<;vWU7 zxx%cgNh?NDj-s|I5!6a?E08$^6yc$z8 z$;zc%6R3m_h{SOyujMF*3u+ttHUO@==w`tIH?MeRqOqiufdmdliTyH-n9r`^`NlQTbH@TwPEH12pao@%;f0g>fHja5*BO|#|4_q@}EX!?PU9tz&ITHHgl z9Zcv#7}bqNlExS@5Vk)NMv6Fn(t{Cm5)i=R?uA?gJ7S1SNofCtF}SOD{!916z6(95 z3-h*s2(G|cp~bMtvty1)NpRTAQlr!`4H$2X zD1mY>ouMsaWbWWV!fC_Z~NQQMw&a14|S$ce-m z2iji+ILE}S@!CURRjeE5twu{6Y1q}1`_ILYfS-Ezl4>Q8#>}#?B&A)Ub8`)9P*?k% zM(Vw8O_)z5#jVHd*ND~nJ3t)+9MJPLj4& zWp5*;@~BTO%jZlDAHTqgYHwBiSP89X3ObtcUkoRUJ> zU;}lZc{PC8yBhjt|0^>%S-vwVmXQS^P@=SrIsn;^O}&Qd?Y_jl6Gk{PN0@pU(!Btv z_OBzQk!mco^0DCCBB#(i&i%g<(RjyM1VHyUHym)}pt3s_YHL1dP_p8@bsV6o)nZ+6 z!+?Zg-VfD*8ma;yQZQ!^Vdnv3<$-`nTT7{)UqE*==rA_-Q$n|BvwW_!mCon*E(Ka3 z*$He;U$;pIPp;}?vYXxNO(rg>?NaMK+h@gXu%G=wUQ^YvPr*P391d+#rxL z4F}47((;a;Vp3NCmcEJl-=ONp@ZEJNTFP`R%q7y6w@&2J8tza{R64_=5Jm+lOKUtU z?iQYnks-@W(Wd#11DV`<+S1gcTq@Sl?ia`A0)b)!)VCO1Uh&5FkI`=wb`y|XDagw4 z9Crs+oeEfC6v}R-?#ZoCcqllF-@$JM>a)mC@vqEn^J<;?r<1U9

L^8p%XfJk= zdv|1qnv?fKCd$9jcW(u_QfSaw28QUc-@T+gK( zU}5KxeKsOrw0Ie}s6i$R*MqA2ppVVHofDa(yfH4WV8`j2y9Co47cc=7jsNcw$on+dsUwQ0hJMC3f<;Vf4QS^NZd&$=y>+<w zZ-LSbx!8^JT*I{cn9WMQG^VD@Ud1*A&lE5=g>a$Yz|n1AmAl(i@bvNwm)7uz+3goy z?+`w{36SaFe<^YBmopws_@D2;9^OxXceb8*I^J#|IxMecPDXw`Bs9i=l@itf6ooXs_z!q9cqOu0cYA{7z!!03-t#+KBU&W4+ zg_3=spWN{3sb>E{URNkQu(^A6xwHk{j4KTzd~G=47^A$hIv6f2$%Dnq85oFpFem;d zpJwui^(@@J*?bW7Lbc9zUVx}9z4Swq#C=%ZGF5sfr4kjm!GLGBc5lUQQPS(RGr#FW z&DQa~*~XNos)n_h**(36NT!QZ#Go}St8|ds4Q%t>Rj?`GCIU7sim64H z8<+J=^dRLdeBmDWR(8MC_fk+GNp7YFiuK1sZRt92xNNUxjgu|TvxggfU)mU8I+W&v zz!$C~9WQloN`O`Bdwos}u1P;C6tE`a4Q2~~;@#l66&IIa-aqR+orV#YD7t-_DlhMT zEj1p52U|i>Q^vMl-u7g0B3Gtd5;0ra)wDA@Hv#Ow;tjD3o@T6u=8-^}dGhU9q|sR> zkc~-VFW4eTTc{>SmmXu-y?ZMo1AVV8_OB2>o!vovv%fnkZGG4iw$Jswzx1z01~>FR z9q+x-+mK%eLJ_S8>J7SCp5--uBtGmuWF7`-L>HP-OEGyGty@?cb=e-D^SCe`<2!8} zQlL_O)NtG28u)ICTPy-q&iO(%Rd_4FNZ438rA&X<^x61pkq#tR9N2FUQFG~+WN5uY za<5)d;W2M`@Ak{!C+#7)({nK|GQk-2CGSqj#IN;%rz@;n zYksfboeJ8UxB7Zg4)bLt`iUpw2U~i+f!ua#FD!U;RNl!tcB?D>D4^=B_7C;MG}=&A zFyR%0DRK2^z35ATbn*~Im3KAL)-4FDh-z<2YLr(&NS1^8)vd3fCTEnft{#<4n3+9A z`P{KS98b+$uJ+epH6qY3?&O4ZA@~k^WM0$l=$LZ}cS7#4#3KiZItKbt#$m*kdoJ|z zCHstUAP6?4km_{5Lo;-r8AY@fzKGwg+jMFxbWQqrL$V@&<4c#4^x!|PXTB~kf=Afu z?`{-UfA_Zmfe+(XT2l1{Pj+fN+g=TB36d@3+T`;+Nl(1+E`9iI*HoOdTzqx-L~iSL z2SDpF;N$e#RxlOJHkw3EBg>ger$r^olvT94C&ULwWloBBeL~N>z-@iGW&$Lz%E?c5MJxdDhGj!yM%~ zvhkd>?nt++;bu!HmaYr`RjsYe+cZRS8&F^I3Z_pZ8T^tS$ifyr@4+>Z?r3^nj6@%G$}S~*vk6?Ri8BP@I$K{9c5$!@MV~@ z!`OUrodcJT7bfW6H&6ZJ+Ud<)%JTsG!D^9VOFrD20oyLSca(d_-}EX=O*a|NTHsqH zL8K8<54B=XnlvZn0zZPMmJVp+J&->xtmDRCbYW5GS-es&q))wmPmYbYL)oit6($9N zUCpuUwJ+r4-lXLQ$*{?_iEiCR3j*&1Y{ zy?A(PqowFKGu6n{J;EysgewaHmZ2YH$*j9QHdvn$R_rmXLPjv(9%-+X%4^=Z-W38$ zbir?Aohc!MI?~+O-!~9bv7k>+4rJcO73&ipm_#3aqea8~3))4V4yCXBA>+ z-SZV?yk%^h-8$B5JBZQLv+bRNP*)Id zzi!D)%x;-EsH<)ne*X@|M(09akzua{D-fo!oagsEbFDbP)){6qG)US%I>i}-F#L8$} z;wl3wiVxhbYHhp~OkQ=ON}n@-fo*(nO3Y6vxpNg+ce{ABYc&kZkhoCj)$tXlbdoyZ zqHZyrq$AuZhCV(p%BnztPKYXjw~*W-u1{x!h8PfVd~!1ejj2(Do&G{9ZE&08YDH`u zbI>)rJT>WUVV=saI=!~}tTV32UmBhkHAe*+`_5#$Kmh!7UvOu#p`|kR=GN0~%U4Qn zY$ONKpiW&YH=qz7ZBPieaG5Vpdt-v6SIb^A>#T9A6mGT@4eO5$*u1=aRai}AM`<}J z-&Wr_nnRQlw~Iw+k2Oe2@?~VuRljCPjt#1}t{bErrgL3lQ4Q~zJglxAR;_7~U4Lx) z3Us+SBZZE`_JV$5ISZU<+l@?RwNU7SYlnGu)XCYA5ORY)J`!sh`LBEO*5$1to8yYUHW-4h8n{&NYrzt)=6^O-i6_72D3sHjF@ZGE4;L1c?{OA z;?H4&b{9>FIN@FX2DXeB&Mxj>-AL-UYE(fCXcP2@5ol7y|qoU%rc+IC@Y(1t(6iei0JTup8Z7wJLAEzkOI$R2k;`(*MPE;V$f%elXTpR!2s%+_hX_-Z*a zsT8%?f38tZry@_nG%}-=8?}mC>F(`-ujWw48NN~A)&Sg5_+ z-Zgkt+;)X4uwvMwH~3R!BCz6qe{9CE>B+dXXHzDXyZNdM^GklzWvOLp6 zn@zg9h54~MLOd6z#nn98LP!<&XQSrj_76_bBk>bz9v3RI*U@L$tuoZAB$*q)u<$yd z%aI(-fi~(}rAyV?uP@wj^B#fJp;Ubo(y*9%@ud@eD$ILZ<5}-yoRz|g47#FGNi?IE z!7WC~MN$1S4_~2~!-aJA7SC=+$EGWZ107e+583u32zTfUWLyl-OR_cpUmYcL z90m{ymz~iU4_ zyvZeHl5Np?IJAq{DYdVpya5TM;TQ@n4XL6|NO{!?-mA$}!$o?=u%?B**-M{?q8PaJ z3kcw;H$!wMAEu_ECkEGIkU3`TiSc~Erv<(Hu|U}H3zQ_!SgTO< z_4JL#?mo=g01OKLG&Ub*&D-5PZk?JMAitx=gTnB%XxsK5xZn|=4%`+aEWnI-yU@tK z#ln?du_0(Lfrs1+%}{*sOOCCph8#xNp^h<+nW!Qgr@Ui{CtY`{?alWL50ELRqs4}6 z8@5+dD&Y*yHM%^M)qBRaTxS0sDS^6t^kGTJz$UXvJ^)pG(+F%=s_0Z|(9RCI8X-s) za}6?6fD2>7$XO&8&jj%+DW&vrj-)t4|EMhQlQrOGnsBb}x9F-9GE}HY$ORd|I)smH zQ^OIdz#*bWP}-7D#2OXVxYm^nAXSJuK`r09Vn1n+pEA2Q%&iEws5hq(=ERgE{Mpm{ zCF5|_qcD3ODviiw`G8%HZWWW&O>47G^qafB?WV*o^`19uXLi*i<0cHIdU z0ftGFSeG$JIOwin-$*U(+#xyTo8gn>mjyM@1E8DRFrR&zVfV2UAa-{If@dxD8~aH) zf3H~?m`VUXVOpjcK6}j6=@#VPlD`kYZR)peYJl-IS9|)G&JgsXfX^w@I;I2=J;qKB zM!J5yaSXYYG|yR88b%D3&@ygqD@o(9@#(R`O3vb+DKtgMG#Wrd)LYGkHhW!IuLayFjJst?hvrOPy>+0^b}IyrZ1W+^(szQ2}E9&~GZF5dun zjE{Kj&JfK*v20o8h3xonZ7M>yBRg4#B>s8(U2RWJ2&Wn|!}tIg96-f`y%A&@QHvHd z+#~5s5k2-?ww-f*)1$aPGpc7G3}obt6hjXNyP!AOHrwF-6u&Qcf!UQ)O7Z|h9bSSh zV`9i><{?j&Bd#Z>7D9A@VV2L5t=6L3Be!byh97Om4HO7Fcv&rqr@F_|K24o);-SsW zCILrY>@%!7PI68+U>Bn%K{R|c^8uw{5oGd28Q`xQR<$y(^odjeIV8H{gM^ZT$IqsG-P0C9s5b%WWpZa1p@`L<*&tt?*KTF#ygmoM7t`;&V zwC++^PfzbT(q{$F8Owym`dFZ^0kJXTGEMoXL$q|m-1XhK(hqdJm1&#_Oa~-i1a!yq zebPZKCZeleO)pf&g3vro#1GH7$!4SV%t!n~m<)!H&=*P|uL&rlEwPRTp6pEN zoCblTH}G01-XE=vMt-v+N2Hp|%%?c(H_X97;aJW{bykh$3u5?s@N4TyVCpWdUb){G zzNOB_Lb%}kI*DaILVLkDnOX$Qapha3Iq<8kELxGe#XVVYKqkMY$5DA^9m?j5d+k*lc&viU?PF_W7t2EAzX@YmV7Qx7vG_SVmrk z?gY|#hy5{)-xASAaE)ZU>lvm=d1?K2zpja)g7RYoiTA=z$VT3_oox$17>){4i=5F0 zBS5&_wwKM*#LCU!zieRu-4UWI4*2+X$m2zxIxDhoNU#NbLk>u))EVK6cE zJ6^Zs2+CAfWr_G@Ue?vB zd&j+UuLAsfnlQg7ayFs1K-sWYU|ca$m#a9)6qrtecZTE1kAYFq`9920I^q~^S+XB| zcL|;5ZhjY22JnfVC>U0rKch3(`Q>=z0QPyKTD7))B%kaja{lrvN4`D?ZmAYlD>1&S z_`D>uJ*7vZfCbI8fy}bZysK3)T&oPZT65#yDA8}zB!0hez%bT{=lGQxeweF>(6z;X19Gf!_KQi$7(40S-Dg=JQh$nxh4;ABzF1ozTF(dge)@ zx3jfX)wM&3s>iN_dO&(e5nq9j1d(eCA#D3W#AXP9mZp_~k8 z-JHZ*tl+QwCwQ80stI2HL&;{Y3BP#;nHCkoZkU=*@-b|w^!!hX^w#dRAcrhergpcr z^A^EuuI9Z_&84fSiY>V{EjCPx0dRNX9Y79`kB|F^5nxVcrDcX8W_HYja@_!%?NMf{ z0;1lRrYBV(rG9{IZCb;LI^O3&xLi(i!Py2(hraHqwueFA0&kA_uDs7jjfA-oeq^t9 zF1k%?;6(zU3~ULW2S{VtD{~c(Oeo;BcY4zz z9m9}S6z-M^9c=voKhKXR8}f~tL{vfv!0)J7DzpMU=3i|Z+_CqTP>PD|WMO>^$p%kI zL;iKGT(CEdSWV9Hp2~ytm^+90&f!ZD2Zy0Q@c%ed6NJ7E)F=S}cCi5ei>Vjm-_BGc z2YuInOsRDLsWANGPR)*+h6|ua2)f|~UF$^Q!4P_FN66*J*AqfF6Ks`kh3e^+j_bT* zPoGLnFJE7pS&Iz77-h-22V&gcHXk&Ejs3WC3zi~m7+GUjx+V2*;ZUlCJ0jE`Q^+Zn zY6zha)ukl)5=J9&&0%j3ghn$=&{yKzO&D`gIVor(zw?)y6h`Ts_NRmY$x~HGe1?-PTmFym9CJQXcKC&}KqVUDj3a*r7aDvY(E! z-h$fCdRMhU30f^;p&cBqnt#MN64((d-2~gT42;&EB2k=|C(-3<*#+|STUBVeW|QXi zx=3G7i=wPplv8=XT3b}p0#Z~1GUF~8u(@%+VRuRNoIkwT82!PGxs&_~ut}}~lXsc1 zk)v=A=Spi#+6FVaaBe^Z3*tN?RiG1aA#eDIx2~WbaK#)BmC7iE0;D*es=UbCfP+vF zAC4w4!|(dHM!J*gllK!(EsAU_ZhH)*6%8`l8kL@@aD`C^Zk->`c$I8)9EunusfYUFn$fO)bwn|!Bj!1<4xj#7Ab+)%$x!#?z~)W!Z8JDPoA zR1XekIosCb`iB#DKIrFMh!lf+^3QIAvx0}`g6M&9GZ(b0%rG=(&f>>B4YE!5$~DL@ zd}b~_%jafhY}o;spxKD*5C&Y4K=dmEX3R3yoES88)3u&-E5qC#&~Eim~gR|&G$ z$MgAYsc)4|!%xNTPso2ruS?e>UIhdIaQ63x!~aft__J`PF*tSUBBKr6JJcP*K4OYRB?iQKJm~YCQN&pciMHbk3^Ek{U6y#PJiK-z3w&hiIY-NG*GaJ%s~Aw6r_n%@8>m;(RtC(_6T~}eX`9N>h;e%U z)+kFuZG=!khD2Pwu8D!5PZiM`lj)VjYXMa`2SgPm`Zm@m7DA+73 z7)ZMO8NBcfACIYoX-?)oW=w0yrAaW1w16s`zUJ>66gZ`Gn6-&m2$3p~G?C#ibePof zgQz_$t-zo?#N{cQ?zc$D?@`psWqBAYp?~U`ZiEwOq{%Ygt8W|8(G&*FD4wyz)TS)+ zCBhw`slLp|Y*2(YInH<8dj!XZ2iM&M>At% zCr7$}y_o-5wz@Sn6AM|Js=ORV$~U5k;qkK86Zft~5UAWlF0y6WVf#XbtFOon)pDI3h}BoWmsZ{$sS_J0hW}o8J(DAupL+QC zCXw`jjb9B3Evm?ldu}MOlGpvgGCqxmnBi7lFgngiH5e?lM|i=_p^eVB?987;in%de+*acUMha zv=eIy%B19#*m^?n9Iv3;Q+a+()o?>-%~|SSa^2j8s8YcRTM8lDs~Jjq^poL} z@`Au3lqn=lH8QHa#P*R?A%w5vI^JlLpkY#YPO&EGJ0#znSU01!qaVcSO*c{WroKo) zpnufZVQSRiL_>+%zzWM7QTV&a>tMD{`rP)emH9yyzF~6m*mmnpJS{cwa~($lv**52 zI!_x%givIfmGxz>wS?})e*KfK@`cl1D;=g9%XCBycGj7O(Kwy}?JHfXxKi_Qg7AiB zf^jaL_>fedbD|_rSR5lg{vy*USsWcWW%^j!ylI`-f-I~KDi<%}(prHT@(-5HLv^dO zgz>I0l{aZC_H5Lx(PDFZ?s-t6&$vBpF0JvyUAWv$Kj$(pWj+A1fiSuTB>^Xb0qa7r zN*Jk$qqbRehNB08q~OxQ@XYS;T2#)hMdz*Uz%bTI8JANuFmZs&m}#`!I)wdb4ls2} zHO2!oH4cCpm9Uod7^okC4#UPE;DISXVRLrn{xCzAmmhjB3?1)KB`Pp~RT60pAOpCW zJ&Xdr*d#}2inPhf$fUrn0|0`5-~ni#8Yiiao?a~u2%Q0NS5jOdBq9#o%l^GHYMT}e z?Vlb0$blo^`eMrgk-jkC4mEiKYbI| z1cecO6EUl%Mnw&?v-}5cs`&1XFj(yO$6(BkAXo@b70LF^>G6G7HA)wMq89CbdJ3mT z^Zar8+4AlX&2}F{%1l7etdz`(^pHP#h$>o41AtB0Nmzu%Sk7+y-lQPU%7yg(ubV6Z z=Hj8G$A+WMIAI!D&3+x)hsjYLd1@q+#=+AhXTfdY42Z_LM-OmT7d)8!ZR5-;C{vz#>LH=QMBetSp;od;7_fQ?%BLT~rf2{t{FHzosT#Qj@6rRyZTLCT#!KrfCP<)nfj%LKLD2GL!G9i!z>*}I7 z=7JNmS7|g4L@b%TcPoB-EI3_`lq9`h{VS<5nK=Y;$`ll`ntBFAkA67^d+#4x$#z0+ z?7@=DfGqCpB5v$eOjHqfc3_YwxJP@B+uT`%C}{(rXMP#nS&SfXhDr=DaAQ$2ycl+y znU0D{>jNuD6VmJm9$ui_@&4pV)nIF3EzLqT??P#pGoMZ}_|Ndjh!p_2G0h2uE$*d)cNTD%R90<#P! znZJVQO`$OV{uEUX5+PQfKRjurepQJ~z)#-~fvbcs?~5-k z`ugc3VA5^!iu9UUdw!UL*qC0cU5DwnVL}hy57PnXyWN=v-I%f}fJi`hdVlR`GXDJo zoVJp|>I*AotT|zRteHt+aIO0#xsJeC83R*Va@o<8@uiH7kl;|l>SgM_al8#=K5xh8qug2(jKiDJX&Ersad#`)s z5pGnzmoN6p8kt0e0UPb8;RomxFUB87AFMLH-fKpqBlY=A?ueyJrCl7DtZU(Qyz?s0 z+TRvg8t0lhB1^eAV-c^ODJuF%VNFQGyIKB^RS|5*u$4T4PnK$3BlC9iIMxlOIh>b8 zHI>x1HAdFfvD;3)F4N)V@2Ns#SqPbosS2HV%Nx{{x0))x*B5cJ_i_feIKJr9A%hJ( zD~pRg$J}Y0m;#Hl-(AyA3YD))%*%zBG+$lFXJnYgICvt|fmSoCJTebeWfAl>MF-+- zZ|{a!U-gld-(hRSlmq?xHPKQD{LeXFJyo%W#aLyN+%+q*m&h5VDbgvU&Ns|rJQ_;N zumFsaEt=tO8r25{-0A0;d?It_ZdmuS@aibd;B!VHFf~WUmG#!wwV@-2v)@Gr3qSu# z8=PLhKRc-ZsLg+0g8tXXzfvXtx&mDtKM6HJk0A2mBa+rFt|=g# z(Sew+IR_7M_UJzyNUZYZSs12)V86%sA|nHr?&Yk)gZbxe#te=^+AlAq!dcst?rzt;! zK|;g+?gS-hL#Ntju=ROIVjJsynOrEmEWP<+^?f{rR-iv{@hp9DJosg!=(B9}M7ZMT zO#CpBXNs=1$xjoeQtvnEzx!t#3T0prImye&bT|h_6di z(`JrGR?pC|kAoljoRlhQicQJzj$obq zTR@!dMc!x1ITlt%@~v_(qxcgx#&4s#CrqXd6_Usei;0FUhCbcZo|@n!j6>1df_a}$5R+f?fuyDH_Ah`;KHf-1I+l0e<_DQ!vqe#|arEx1kMS4o+*v&HsCg zSmPmo75CsuoW(zlnOFvghO77RrfDNFw}QyTfx)RD-cnxwkG);L)4ubM(oVQ_uZ6Ci zf|lr5hp;jSav5?8#};s0%PH!38hz3XMx(0Mgw-z!Z#gjiMx7nOZ}YJ4fhrdvvU?jd z;pU&;ujpJcg$u6;PnQh0$y9x46tc89P!$aVyp2t5TF1=dqDSKA1Y=BOz>Iopq2pos zD#BwRMWR|b0bnSl@0}?rUysFnqxsyQcSC7`86aA+ZEvMPBlX!kMKO42>pht`Cm@_A zRk6pV(p6pEpv+7ou}a;R$Jh6NPCdxWvH*Mmg39(kSMYz< zoBxdcm?;H0a2DY42kqToNBljTG{g(rJ4>fRu*wc86eu&TxroTEOW%E<#A~;DcA42G z;V&$Fo#oV6%wYqNE2^;&d@$Ibypb+AoT zor{W35}*MR!^YUfl8(tOL)|ww#h&dWu14)Ve2}e6w0$*U3tirj5saIoCDQ)&AIsoVPR#iiXc_GP+k375t!3c&KiW8- z$Y%>YjpN(HD{R5KppY!hfJaJ0e7>B_VV<<5jCe|@BFs^DOjpw)nT=*1njvlpRaBtAjn%Y+u~`v)Dwu?A5{?vDtvH5k(51^7wE z5s1=L@A$qqtiBytsFFhrAt$|O>u_8jXy@mKEiY;Z_Q(SJLt z|BG84Y@Y}Y7#O&&N~ZX48s*Q}+K~Ue8m|}N01tlLkgsCPEcZ7hAGMGmZ6vp+db(RB z2L)?6{AN=_b4-yiDewlm*42#nJ!Y`I`{U}?>(0GvgI;s&VR2#n@3T!;hu%6DxE=(%gy`qjmHarSLgbg ze~!>NCs)Pcld2w}=1Ix2=7;Osk;hF(&gA(+SPr4%yw%>i;5g>ki5S9eqYOdC_wNJi ze)VlH*X%|PNXeClalfk0-w$qfyl3a`hdNdKA5NCJ{L2&qc@47g>4%=_p^klZ*Q&HK z=lkvt9PZRT5o%aF5PTP(+$?A6N|v7=m?i^fF@#Q{UhJ=0mfl-0cJID>zKnh}cKK-Y zI~<Ik$r8W%Z}2MWLw$7GigmX7@#&K~+H~UCK>`kf5OL z;@P(fp%Wp3WrEH2u8ehiEF<^zcI+4X#`WqPk5K!~qa;O;{=Xm}ZZ~5(IAKlvLAKlCEt$5-q zxtl9+YwN@zlt_IGr4ky=rP5I;{%k&BlxJ-+ne5i>TsfZal-X@E-`UINV$8FWx5?^EW6+x*0e6omAPW? zZkoO1Auw%ce3O~$GVF|L1Vil(F>vj#gXSr}GtefTT7M8z+#TUDl~Np>^=4I zIy7bbdo>&Sx9bwsr=I^UJ?b;D;5K}6owY}8+4wZsrXoP@wjC4R z9Z;L}aejYNUBE%}voKF7Ls@l+Y9QJy?zxbLLdRcKRHj@>Hm-0Lcf^XN-H87CR|tlK z+o)va%5s!>x&y+fb(=||^^2^&H!(7|sgKxG*Du3g;<4jth=24sq*LLG%Y1z_Pa+RD znviyh#%!Quk(85k>Bp|h8vNDV8&iF2lqhza+qK$uv9&-1XXv>Jvw!D93r6vi9EBQ9 z7S#lWNV+MIR!bg>J7kTIh4*=Td~nE9s(EOQcF?z9x*Gce$W)BsULG>Sl2f?jpqg_+y3>Lk zKas~4N#9YFmfuN$?jTZ8b6xTN^^}Nlh9}{VhSzTP^16G4L(L>Dhtyt)F`CmZ#MxP<)Zob2eYgRZ<}o6z3*mNGAUcKhVcnOMO_X?7cE zItc2bwB<1*d5|iN6RWU`Fs!hwa5-+z4|E3$Dvgzb8^uDBF^8{L$SkN|5Gh7}u(OXO zl1wK4tR`nqmljL>(Xdz{79!gk@YknHpBT*sn|jez(uKtczif!*H}7twOc`%Hf4khZ zq@QY|@%Wm7YZ=@3^=b~MIw~!LB#2+MmLt}U7M;w7HVaYU#Ru+c_TcU=_TA%R_8xzi zV|T}b64|OKc8Kh69V2Osq(BPT162JRZ# zazuQl_Stkgfvj)Gl{p$7PAWW%ETj>pf{{#fx_)I^m}w-rVEgyVo8XLzH+X?a=ZKZE z9lNx3SUt0nGUgtPIXf;o5kd|=0<2U>@AU7L{%PZ0T3t;(+`kk(pOo`LJz40FWY`0O>Fa%ip3o4ZIIWAPl<73i-NP{){S*h!#k47u8eV; zs&@&E#JxU?{jOu_FWs`Pc)RXx5;pd=H|avgQP+;+fjv{ZBFPYkdd5@As8$(Ru%s{t-rCn3V&pF~3YcvpqFg$EDXG&)lE~EA z-;UeL!k<$a_65ul+GGrt6e78Wt5-=!gA0dF05UZecWZ@H3b5;6AlO1b;W}=WNw9+5 zFUVE}vS&J_%v{&y;Zgzeq?{%%I%xrtn-yf*xuK!|`NS+Ez#a1zVXoWm$xriFT4vUT z{#34IrpmgVr$pS;m;9C>UOJypRQfbhx=-PSOT|lVi1nu{)PloLa^Iu^2gD17q2vZ36Zs7Na~xn@lSlCTlEZmj&_Yn0rt$(~W817DNOUYk?_Xcb#()JjuiW z*i&!_FNJ305l=l;BBT0SJc*kT^aW-MG1yW4+*M=A0dP}}pwA4#-Jt(ahrv!!Y;pG1 z{dVlh+x*j*!uAvcO>Xn$rX^vi_vE^0Q`t_%Z83o&ijt$|Q2raM9kEoYvKbc&ccRl& zdPronzia}`WJmfRO4LYPnV3d%g4Ay40Zv#3&P0K|>WhBCQNnda>3sBx$^X#VQ<1ZQ zuG;&rXc`hD@l*4EJGSn3)k|qpCAh zu>N4mb_Joq%E1t7X6DfQ&=}Ck&>Hu7hF^`end*L^{-kfsveh|Thoo*&ff1qZ38txM z1!@UwsB9>$ukwAZ(wU5ROuNE;0<|1tudb$VGiane)CH$745oZS@~8F@tCOlPPi(DM z6TLCfv(AruNKl4SLJuI!p`;_r)*44v!sp}XgXN>7QN0qyFB&4~%zhG$Ypf@N>9qr{&f4xefD`r^d+Fg8s4IMFBTOwDZ#&!UK4oBww z&p^9iEyPS$Ly9pQ18Ay|q%N4H3`5U-OnBVn_c%Ykk-^18{h{Q6 z-03`_PC?$_lr0K4gOp9!)_YRkDabD` zfY#ASH?uZ9=UbE%nSJmt;(!rC_#GogtzjqGQ{;c>^?~$gG`)%E<}P7w7kRqdX%|F1 zvm_w$b>HS`O-&wEG3|(*BO-#%-T%@lq+}(aK^a+#QoAZI3zz6~RBjf|(|O{G{jk;4y25gdsM^79Q%P z$X-eEgXrOj#4$+mg9y5VPaTr1{5iRD_pxo`!Ns=`V0)W5v-ny|XWz~$Yef5+XcIX) zRfNS`OEb%Y{WiVyrCB2E51y_O$>Q^V5?|FM7xUl}V6J4Q-Di&vXsJ?=^?1uS zoQTn^zETviNl+$ECcWCH)=7^R(@QU3`b^F7*qGZ(@2*Ngn`;ASu4z#Mt>>BKy9NA< z{t%TKDF5!aJcqk=l}R%?Zi2Wv={Yq_aRG-QXD7Jm5Epb&9lga7ZVnR+jxi*@fJCxi zr&=7yC4y12pxHC64YB*o1agF5u~{&GsEr154|K92o@YBN=ZaGIwE>66cNrz*63{`K zN&wUy%^}oX*+r}xrP4^E73mT)j>$PEqm%Wlq5v*O!i1G1G{cH`ySmgQ)=Lqmy7%i`=uGM=?#n89&vw zAS)UsP>$SFOfPPF&(Ltd_eftOMH-pVo|LA~AegZGi4OGS$j*Fx@tz9~XJiw`l1O=& zf%1bh)==nWqqBi=kJUgrrydX3{j$%B81z4s zv0PNJY_tt7elmu-1Fb0IYBPBtgDLq_dm3LUTb_D z5@D7`XI}Ci2~c08qQk7?e(l)|v90jzU1f`1W3~75jk1+!@)7!`!)o$XTJE`ip{(pB zV?~rth$b(Q-na`2ap_dMj)QHJ+RL%LWgd{UnFfM~q^^wVmk%~ig!CV&l1{4hGNKw> zC`tuzyO&qHTgD|*;r?sAA@X0-wKYb5LwNASQ{(V|ctjCSn3N7!7O#RK8FO7X3iXJ&Ndus~?LqJo&%0j#ndEES^`G-3kBZnn$M9{rj=| zm0Dh({}F&kNc`T`3m6Kec#`-DES18Hn!-+k9sHxNcjGlRQis2@hQkYp|HxIs4-QIe1PY~ zy7QTOSS_L;iyPs;_SFP}_l)k;aSVQe`_Ka%G+f- zf*_2dh9iv9o@9=~t%J=Smb~WQ03__`%eJ2*p6=f&S<9_oJY`#+GMmc;r~#$=Q=Ucf zt2}NL@R@R#{iiv~tiC+RPG~|KU08BSk8_ z%hVmMO~wnVW$?GEq|`~va;Rqbkrj;)DQ6HDvGzcyl_$*f`$(z+zxL4Tq;m!hSplzS z(H`q~OIcgFs=z1t?!}D#D5M>s^h#>w+a|P)6@Fzfx^ZN<2y=O&?{}j@j z@WEL^_TJjAgYN&sn7IEbRgC+x5F=fh=AY>XbdFPG_eT*SA zh00`c*vq^-DfjcpV^&1y?l;`K(Oib_i=p6I)spdn8Dm8{+q^LORgTY<90XU-@&$wM%~+yPHY+9!ae-s=Vr42A zH9I`<^8qfs)yc}-(VCo(q)QEO_#hbKn&Nvkm@&m5>~9#~QeNqBt;Q&Q_6rAkgWR+= zc%zY>Os(-s?Mg%XKMtyz7M0-V>SdRWo1&Nd5c3j@viJ9QZydOg#Cl_o3LT~|mg7Dw z+<1mHAD1Q@;qJWLI+M)YG1?NB*ADshWo3M7qmuzMIWOQynLVr0BA~J&pUnYJ3jTNN zOpBcq9IU1~wVav*ni#xSk_9ySJ=Ww9^OdQ=iE<*>8XJWN5CSG6&E`(30uaHo(y**w zF+f+j$m5D_90tma%B>gqh|167vgI5ZVbd_lyU_?(FmVKvAo_+_a0O$xFP$^CXCVb` zBtdN?p)o)cLiTEA6fTr}{FGT?HzZkMm03lB>o)v6v(SI{SbOr!(Dl_>VbjdM7%^DV zqY6j@RD{W~Pz4C%2)zv*#&5C=KlZs+!N^7;?xM+!$VN&hNmoJ7e3*#whw;9}&oNme z;bSbVz14bBK?Z;$C`QUHj4xwt$r}QU#$vJIAbckP!T#TviXa|UbrHN3sV-GGdw~;u zB#0SVD|mx5k9;pvvK_2!>PyTR$&c5qgZztord2+2t_AUEiJ6G$x>e9~0$8UDWrVxe zDBtg&_JEXlHFzpHntWZdtD!nLza(2Ox0ZmJg!S^iY<+ z2KsYw1gAn2u>Q>!pId_(ZVLfEsYhk>%@+cK)vP^fZ)k^XP;_Xz?YA=tAwT*~j~K_C zyM6=|(*It*@KqmlY_()y+zO5_KdJj~redwLqO&&21}F-CrQeYr1&pxwGl-Em;FRa* zkU5Vbe@>L4@;rcxM^?a`yRG7dTub>4!%G(tlmDgiFd`h_g#|djRu@7ciO2&h1Jjyx%se0sv=MGDX_9ddy3Xf98bXvpRO2t=#;RQRF1nAG zBWMOO`uE3jRMCH1hJ=M&kc6cMAko}jZGZu1V#F&GqJLlf_x2DFZx?Nz!+>`*g8zgtNRM8SF80=e9hc1M*pgJ1<{OfKyQNHls9 zbG6!9?E54EdOK9d4 zSf~k+TFF$yv@^ZXsCZUx(=sPvq6T0F=$RgSON5WXbbCaQSX)g!%&{2l zdTRFRs&YRWU>XbmUy9M$PDGuWM)Pv81zUR=t8{feRhy9pih>kW^({rIYox#CiOW0w@t?jE9p^CQ{f!IT27LowP|lo)ml!1p>8+UG&Pp?Ulq2; zq173l2p5{O+AsU7M&GRv9R7jV3$LvL3nedu2=l; zO{}51e|45;0Ah-`1};!uO0k%d)x3M6vOlX*#Gqy)(?F4*@^2vi)5N94g3*!!*-vIx za-s}n{|PvbDR6<@XE*<12AW2*6@ZFdH3Lth`iiQG9O_?R>(f8t z{r@;(Oabp{-s$~bkk+t@sSvYoKI(^aLn8TyS8plHeccMmncAiw5MnW|Ut9N#F^8|re>u>LI`)@V5SgTK0U28R#NN0%$ z+4m9+z!wAT-(?$Cr*vlWdK;c{%Ezp{fTttB75L+Yam=}W~TQ3P@` zJGIOoul21k3I(Xn3H>;9e|!CklAp$|g>JA0fiVt6y&w=0jm&YPNo-@~9#R=Y^P$NN z-x36Nz3I17h$_qX*cFezU;iO(BGC5E!n7zb8SIvVTD_Ph=rnIvQ-qtQ-e!-2XfYy~ ztv_z?SLl*6>fOakvpH0n99XpwKXUCz=;B{@)~xGHJJsH3i`{~kUwV`SH04Gv0^-IycTMyQ(_Z&vP==yzjxMD!KT{<_s`pztS7`WS|S2*>sxSf zXhdQQ{|hZ~GiLEtiN}^BY?eES5|Y&A71}!7T|)#Bk(H!pFeP}*164v$`uD}x1anz2 z(T6JBM%A+PU3A(L>w;-f9{5|d{JBQ2JDU*}n3vXj<>gMPEcI7aUywR3~#h<1Cv z_`Wqj$_fe%)SRl%g2@erQ;=!(k(nx?0(9+hihNK3o2)5xC3ijSUxjn6cgGgopM`HK zRo=Q0f8eW=B$mG{8aQ#f&j>f@QGN^So)O3IIg>$tsuuGbK>e~$mYfu_x*w^5*=Bt_g{bGl4b8xzK$;O{9pWW;uOjtlGn?4K{)M+eE3G} z)du$HeY9-mARtGyjkKoP)v9$rKH%r-y!m?a+;nZbc^YI(c&_VZu*hk0mT>{^ca!Yc zI0Z#v);K(bQh!Dkf+L}oqY^q!J!KIJtMFZv2!#aII-{wy7#XQre_yCiLQSVj=;F8> zEQ7#v%YZ$rmx1wMNvy6B^#=0mgtFaiWUCpmL<5N1=&2R)fenc==UY%(353WG2yhmL zxQnDEH)2fvh!od-RuY6J=UR2U!6jXjoL)`_$V$D)9Ys53Gy;J!J{DhU%wu%E$ggr& zN7RCM8W;Lc>kTf@q8r$Hbd^ekIEhlq*QD9}!9^@}?$^+wgst)$$woPJLlVPyrnX^s zBd$Yxt=QiE(<81b*Aa?2QSpa{l#}f)33tfnpY`=ExA{EX#$U_ucl!BI_jOIwerK)h z?n`PC>?72q8@Uy&^0SrO=S{rqlzBjz83LA2VKRAh?tP|KDhM4IkSv;!`g_YnW#_aX zitx#?t#882L{8hY-{~96X{@a1H)ecem=i;8FzK?BlqH(pXKX!B z?Am~dr6X?B66)NXi9_`L*+pPTub(25W7TtEpSY(4~d8QLi zIKS`+#t#8Ty2YC!;}C^F`@mn{$}az~UOP$#5DyW%JYkD(@IpS#%3PlR@D#khEygzO{vJ(2so*KjIakS2|Lb8$51&)k$ ze2~l*TZijMiC$0w0&jg-0)x#VqU8CMx z`ze&A#EJ7M6tDG(g};7V2z;yhY1ZuRwtZf)D=qEypD}L*TrYIexU<`9nnfv zWptBuURT@%>6V|->!dyB#izJyDBBCu*xzPlM8Y6O29UC5b||Z9X=y7W9~wB#cr@up z@!W-YBKZ?zkM7rV{DYT-3U|DG>~NbY7-E^ACKQVrO|v%mH^05PITmTS|4f!RrDW6$ z?4nSDb2eJ=x7?LBU1k>Y6h48Arrg2D&!83fmy-G0Nr z5rYl?)#hxYRBTVz*oj$LS!3*ZGyH{q=lopz!E`?xsfJ>x?gt+7SKrG&IV?d)I^`99 zv@xuZh=ena=qYrS7sa-^55gx7uB$&>R`llW*%8Wia)7~x_o{w8GdqM9Fc@Ja%p+|f z-OO@>5OHdtv6ffoM~kFSCuy+rzd2C}A9M%!hWjwa_LV?smrofW3pY~APEl7ZIVXo> zlgpwNf$vzL%gg{7PI@E6X6mQhpI=T2zDP8C^Q#7o@yG#+#}RO5+QY{rO~ETpx>#B? zx(l@5!9OSO!0i=0Pbd(OD3brd1=P8(NV(AE9FB}nGl{ypPJMEBZ(9`ZFP`sz zA3yB8@h;mvC|x{ve_*~dA3ww{+jQ%k0sLR9KNx_!3LS5YgQ!XS|w6`!C}rSNl|SUfNjdn`N|&`isi1=EAudD3S$ML4BE4-81kL zhwN$<4fm!lX@~lpcX^E#D8YSoiUPX`1CYa!c6J2qJy%clSO(wE6ii-I8y;HL&7Iri zIeVGnD%M#r>-&yr-mxvaiD13&^{%5plDxcp*^*)$9Xa(_!dh2-tzRFjKXMcTJS1CX z^RF)KU-z|N*7yXej6_*}FRmY#o?;j$IdCDZ`qNL*`zLSJjHD7TuScaL=WAfSQemnU ze{*}er4N5Z7P3elvAa7m?TA{`=_qS{xy(2dry}a^^po{S4pMk+@mV*2LKgRwDZiZj z+JEu<;wR|YYvwZC4!yIks9&;vQRTYcT6@9sw(&sj{nTQ3)=&SWc{Z6FwSb#8dC+&P zcdaWQsm+`ce_*?<26#;uYt^W@>=QiqfAc~P@LjZg+i0F08gv5NxTsoKzW>FXT~nhZ zlS0ANeSoG$-$CzbnBf=q5M~>hKH~2|-B3hhzT*~F(me)x7yH4`Y1f>VAh2-ug}?)B zMv=$st9Xa0c*i;_OKEAJdcP7%&dbktodFl^N|riqv%e9wPp0i7Ibn2XLAyGp=j|H$ zKd8InZdjnp*oI9d#A`&&Iw;MJ1^aV%v!|E_)rQ2O%*EmH-ZnQPi1{%;4z^qL2x7f| z%N3j~7PR>B)Up=lHfJhyP_;8W`|0>&6rg`NJ`8*eo$3+J?98Ulz`H_qq~(oyjF_cH z|DCyqZ1R6%Y&`{N8Pxlv#=1T+5-b;~xsNCrv}v`IlHF zHqq8halvXI)okXnzAj2lp=pc$;eu?=P|j%J=W-@u_}*}pv{HWFNRHB?$^z5JO{gSv&~OkyR`if$N|~CW=r~<{XC`pk^A2 zTTndsa}Il+eNZ7LS2o7kf3QKuUzn_kvqJ9chSDrAx`>(t;-Z)&MD^oe9V|p_!|*Z# zqSS*we6mummcmC?h}p6Pnv2u=yotQ#p!8rxqBd3RTvDn-WhYj#T_tYpT9ZYwdU5{a zi*RMT^X}}HALQ=1w$ggyNb_EE$&55(S+OW3${2i!3#Tqu(#}cW=e;gKV8~UCpyi{I z$_jo8H)il`x&DZ5_hT&iUH(ucu_llYE||*ekvds~cyir3w`~CY#gVI)qUVP=(Pd%i zrkj9x8L?1aE7 zQP$U?Hiw+zEjQ<7$rjcJbt-?`aF(pwHxyz9D!pY=zvWXOU+~Z_+Sg|WnlG{xG))iWevtp9=z3B8&hb-K&d+r;mh&LYO-5h`-~Nw~2CvN^ zA&3s@uCpDlc{DFjgiZT6u+TVsv754drnT=rGuF9w`xyi>$m@-iR|y*yA-+ znxYAT1od*h81{|&B-oWoUp=#5SHIgEZtUC$g@b~R`N*VdJda^{ncMe1+$o09q<=+su~ zdUNtm=MANxuqct}X7iXFVi&DV=K@yE%4co<15;Wc3>ap6bO8%m)qx%m-Rm0o1`x`5 zd2JQkZLoRB`O+fpTF$*1&p8mQ4C?I;TF!15!g3Het)t(ncTyD_hqXx1mk^&vM1(-m zNzs>qSE1i}J>XVDo$3{^sqkp1X1w&WPf4>S4c|H5%sUT$E`q??1#7sp8WJm5QOLr; z6~fe+p;acF{Dqhqh$%Wbz7p0620OyFbGJ8+B}CR;`I0%;2I%a@L~>MW9wsOG2TuQX zIOPcC!n|jXMY6SnBZm+VIGAi_z;{J3tFlTwo{5mZQZ&P#k(=s4o&=O5? zilo?xS|5VQs|@6BgEE4=FnLAw4ts@+DFeS418;=^5cweaWikA4q9mdTG3rslYZE>Z zW>LXylQCq8u4Jstg;z~J-0zm0+0ui==+vbF4sLf$dUF_Vxp+lIgSxmU<_XHZ_1uF5 z@s>xQm$mV-*&S`F#~a)+3Y?0jYuqY>dSGGhGoo71DB&H*qCGI>tzwzEG!<6)vB)ME zDsw2LNvNUFWW(f2ABu`J?iPr$FruO9PRf5mL%t4+Bn+;K?&WUhVY?_pLqu=o@%u-O z%X3r9!gRTlBoiw`9}LenF9At^()VCy0!zX3P=}_RBH*L*O^O(p7L3OSi&7g)i?9^t zAp`XQTU9ywXWnfLXOkW?8f+v9MA#IdGbs4$Ax-I6AX8ubw@+eW7V>`)qbf%e=kdQ0 zN1b8*3H|m}T9~B43>|d-ngW4ON!VbQ5jq?nT@+LdF_Hu-4A?RK@gb`5>pDCMAzvx+ z(b@iy83-Ql@_-01q9~ftfFvOl$o~t>{?Xv{s3=P?@AWMo8n%e2_j46Y z5=CV^B{{knDr`Q5FF4G=y8~(@2}~HUN0UCkK5Gg63MBY!z(4gCEAxK9Zow6;sF`pT!!p{%|3LyQ#PMoYkP8Cr!mtp`iesEIf{a9UQA#( z5E;4@p^V$Za5b9~@!e2`<;>TIWen`5_H9X3MLtFJ8kRu%v>wh_0^&|&g5=`Y!iR4tudByKAZ0sdI}F@jw0nDDUw|xYuCK>r6_m+8Te;PVOi76 zVXhFI)5}itgR_}6GAz3K$GNlF5yli3H>s+uHYf}QHz{q=bB}}B2{3ON1x5Ce%yrW& zZZGpR!EcRBWpEX&D2nX*ZA=PURU8_Es`LQijRr&Y2Ukuj$Ru7VcR>b4wUqQ7TYa^F zsszqF{n4hPE86uB)m~_p{DKx3f`Nos(wJt62v7p|Fzz0{pFj!bhRH9rVP%G*d3Qs% z5||Yu_cfDBoKa ztqZ+(W7TIox)io(jtg`yntRETLc!9E4PbiL0?OWnaLYlv* z6t3KBOq#@;R^HxaV>$!ObN}CY4&Z&pJCsk57c68k%@Ar>XC_=tT;{)DC9bCuhTfjp z<8;Fp+?gQp=DV-k|4jMe0r<-}lWx_T)m<`l8ITrTd5Ii$^p|83)Cdc4 zCuM3|0zivY$?9}tIp0mrP!cN^>0zP{6SU&cj98}~yinIRI{J^)uGS6;us2Q&(>z?W zVN(>I_WV&UaRY{^JkbUB6KTRGAI&7UFV;t1u0_Orpw9PV(Z9Tt2l_!wHwvW#g42c4 z6N0C5Lko$osZeOrUJ`j|pzVB7m-eEeN0O5Mgqlgpiju&{$dHqx(4@nSWF>uR;)AiX zVJs14rJ!IVNlySMON*+a!pMlr9*DA1QGlY|3=Vsv0cdE_VMd~pLPb#l0BLDbRaPtj z4-HIO8W$_%e^vBi*$a?}-`|S@;8R6~mU%B?au?YBFNDZa3I_Onk0w=x{r}bDeW9J` z_n`QvF@7x>uuYS@v4KBxCivn+Z5TT38>{t%#~-WV?Zw+!C?X{|Sh8*oaOkFbv1^3e z=^S2a9KsBYowaM1?5XwJ?{`TSw3ira-_bx^_?^n+8K3)WPuUOkuF$W(`}w5ROHBMd z)pnK4S=M6B^v~$Yp(((u!AiUHVCQa%uM*Mu+4)6)F}K#BYdGJFLG0=o?#?Oj$?}f- zBY=tPiiE*ulicXOTVUt~X@^#VMxl9!G)gP7+E|uEHbYS1hmU8nk=o4}C0~xvs;gJKgFr1Qic6 zNoPE+W^LZ=%g06^7}RTmTi=L2?=)C8TZfV(gMcVn{15Il{PP&ufUZGeCO0PVA*k(Z z-^X{i<(!Pi)#UV?m5EdJvoUmp`YIb?`r&i8fHznYX6feHbq>XA!0&CB$$6eOu$7GW zYYI6jEOpJay7?cI9l9&nIr)I_~2wI?g#6~;_Z*5xOo^7 z-mfs%Hk^Vgy7F$FkxJB2v@z(^mRg8~e@I6a#|jKFC?Zh<)KZR9OuT$BxBb@4(vloU zL=d6y3n+d};*44+7K&So>pacFU}0do{ic!FcO*CI!vEPI zda8>;FfH&i5c8GyP5#|j*jFc4$=&(JFT=zmvZQpQ7!gfPmi)Ph{Ltgem6Vvz z)W2%|8iM7{@#`=&@yk9j!{MKwOl!mNhp!)zf{VXOa$pp2hh|%*n$6w56wI_(M%7JB1UM zRPaok@hFJJFF?swv@}^<8%}3Z+UInk#2m~5_+yqL9UA8pggosQi$rM)emE?~7ONJq zoBP=wcl1B3i4foTG=*!P!MzbRJMl42l*s{A+M!TZD8CYWVD)i8Bwg|wp%dBK;2zA+G)e9zD z*gbfca7LxCbolSk@!NN2wXRiJq}rL};``o^L1Lj4{v}zOMOfkn@Fy7v)KMf_X6XP$ zZ$}o@B*8!A0%P~a@kn?_-4=yMkTqSV9jkIg*QyyGa73yK0bWnFsWWSaprPfd!Bdyj zlWfjL+$~BDA|DJBPmVfD`6S;VPxUX^7G^=1ClZNbK-pnwtZ;r0%8Z=@C5-`xW{@LY z`=%iy*T)G`2~W|M4b2K^7!KI>jlT%f8o1S7%Q+= zdD*Cqjs+lRr@23~5v&hKR+g`YQ)nAh^BZC9)vf6Ag4|^1x?;czeeW{g+NBSNDHzqQ z%0%ffbStJL!mB+*pjlH?>NQnlo(?%d~{&x zBQns3MyL8P5W9HW77*J{_}J5`D?H3v*whthco}#k`=BccWvU#R0lQ4*&=I+^wXF}o zjNw=oeq6|~Bk{9T@IdZrru2VuOqe)&{kwltXrcv9VhM4NRXTy zpS+(JUyMsDo(@TgZ{Xh6=S%X@AWnKUNFtZi2)ilBDGHQoLF&g^6^&JKgCZI}Dy1sz z9n$~E+b!oUkUeZ0*$?e>sU*^kg-KTHF7>!u5^Bg99PDzJ_~GiKb@@hAfEIZiL#MGw zDrN2{`hBh7WH&A8k#58~iBVZmW%*^~Bv>}m^e%YgwBeC~HZBdN#1A|q|LLn-2zPPe zmXw_!M|W+rB~=&GPeD_nS5Un<`qf|beI^h1(D|1XovZ84jFJ-l>@7n^DmO=Kr-oa; zD38@hS7g~VitR)TLj}A81|!R8*GYkb`LD4t00t@wi;z7&Ym43Bq=sl_^RNMq?CZy;!$5y9b8`aR znn0uYA2y~-`K3?^p9V1~hN!2R z_U91znOt1OVOPalb}xSP%p~IZ+1P=ZIq zaVOhL|5%tz+tJ?HBOh0zpfU3n+_RNjg@#d7kpKo*JYhSY@_plPhLfNUORH4pNlBY& zeOqp>(tZjE`7%A#w1GXAYbqW@xp~7o8F;cdSrs`YDr&rL5^{jTeS!U_J>{{=_u2|~r^(=NZ0338ZF!K#qCN;xw>0UmRsrXq zN7T0=Dr0C3`*fOx;HUWoHs3wiQ!?x;Ek5-7g$|eP5y3;_*L_f4{Rn;RE zp>}1ZQx;p~qgVmtEq@g%To3-bJAn6Rp+9R4hu9>Lu7+NTQNd#f5oNllm*C$O!h;Px z2nm|2mqh!hN{UfM-qJF^X7s_xG^9BXhFF@Mqj6(q{Kv@4c^P6OleB)_R(L@+FwQ*XVh(VaawftV0KnR>0)MO$|Q& zdrb32h~xb{Grx#ufCsx_A6m^-*<$LTZDHJ5V!cBL1<|XukqtHpUPs4v_uncufm7+^8N2g6Q*XjmOEw zlh6sG=g{*w9$q?s^?1<bflQ8xn19Jh*4rbqKS+unBT@@xxYY`gsNI6>0fL{T2zhLf>uN9~hv<|e zYw#^Os0AWgilu`GcH0$>`dSm2S#d*~1jS$nY|mFp5JUygpNdwUaJPxFi7YMOsDGd3 z%#e4&GAt($9GAwCSj(DOB46Qj#~xfjBsdbx3=5`2;6)Qs?pv~UPn%CG(hUYRxu-y5 zrrkhLRat{=)3du6SJm6VfU)!A

HViwTD@Cr@^XGD|q&dBwsZHCiqfntGQb4C1C$ zI>21KsTotVSLHC67&5)XthMa}MRo^^s&FIK%;7t%Zr{N)>Mua)xfO(^wvIKJ@p>T* zv*9qt_D)(khY-a`-+9X&7F!DWfeW~%v?aXQ|LW{4fa+?J1&q792bbV3!3i!wgS)$X zfM7ua1a}Ay!GpU5_uv*JxI=K~UHG>)z-IHRcBq0&75y0=eu#W?Bv7pztwzM>~aln(rv5V~ZnBSX86*~6a9(7MI5Jaq zL^EUONS{8E(VW+C(QR0e+7#$tHhRC$H<)CG@SP2%Q5Aqj-RlYZ)<%)I^kxcLs3Van zRVWk@X-m3iVmsr-G~Pt&;fZJ5w+-p<)A@emYYg$m9u6de?ZaP(x~^Wy7x!{o2@A7Q zgdw*fOdrl_MqOn1A^$pKFUjo?=JPnQK0cL73wlBQgLF?#pmQPCyV{ z+An65D=aS5?|E_M_#_Ch<$lR#eEH6$$r6M6}Qy2v30b~=)kt%((dP3#&9 zULr%d>0)3*yK0A8zEcd0lt-`BC%3Arel+gZ1>?px$~63(XQ>Nc@0cfSAj-7HkCo_3 z8}k6tD`1(9&g&t&Q5av(IsqUF4?W{G}Zl6hoCP`>TJ)$BZv>6?8_-60*xA2LXPD7#dO$R^eINYb-i)*4;^^ZH(iY9NB)qTMWUKC=pR*;M9U5Y|c*+DW<>gWZ zkAG}rh!FKPK(DurkQ{Z0K@*yuLKh#OZ1yNjGVGS`K*;8OyBbFb%|svRKGtbe{`Ibz z-WHE}Ms1*~S9$fIjj&3(91BUBfPDm{I$E}{rDPBwbiU|P~hot#jR{E`EP!?F^ zR!s?Q`X!;`Zn~4=f#c`Ct0oR8=Z?CFtl75F4apOO;swki*5+E*&u^84!`iGIM*5{C zMQO3qO{+mEsvIl9Ct20Xu?mF5s}HNsJ`FHfz++pAF@-keBw31;#pHg~ttNs_SQ|wL zwR3Uex7zPVj6f= z)VP`IBr*F=vCk@KreZ{1#Wa=+{%onUsiwGMZ$UwYXPTCJM>MJ%n~3~}*}FJLst;iU zVkTLRev!K1s#v(HlU}5=zd@zH^x%v(){2HaEH+8L6|3^k6hP~Tp&^G|hdtEHlFX1+ zLo*GbuVQ%}5q#7|Dz@5=D|!K*%3dK{XAnkEtA8W=uz>ceN!Y?Fh{^Y&p5=z`Jq_;kR?aHWI=4gMISI4d{2`uq8`A zj+YUxeV7_GZCp~<@(jg&n5yybyu{~hltXpZ_Qt|994>hdswLzaqq>`#J-}FVw zX!F2)n^MDAHyv;x$|!+W^-=FDaJX1+ z&8<&}R$3s%^`WOm`1B_h#tkNIiz8E&w7>?s*CZ2l5ed13qhkenP7dn9h}~!q20CRh zfoWfvUwPY?xBR(iFj#Qf_m7KLA0mOT&#LX}JuiP)qRz=j)vX zp|dLbsH}|UyVN5fhcyZAn*p@l8!N0Hx`9+ghiOd%^pTzWr=yI|%YInd4IjXIU?a5U z6j!~PPPR|uJETZ)D~P_@H`IOWhyuywEl)*1f@=P3q($jIZvVH{SCijE`nb`n!8CN* zu2*e>HW6(aWJKt@zY_F{SWxKLmaf5>3HgFHgf;As-A+NxVXKlX=dOP|S*mwm5JoTc zR!goiAG0ztpTq$g1cL9)_~{8(vzO-T0Jqpa7}ofbmVbHK5DQ^VViDQbWv2-uaqa?- zpML_upa?FJe2f_c&#z3snffa>W97D>(|9d8UV|cpR$9&)A_AtO7YiTol;sWbOFd@; zJ$$;j6JXMkMIkI$dfT0F&>D_F?NT7$rm3MB?9G)iAcs;N_)zY2;TPB)iW@Wyb>d3k zT4xb6%;Z8KUx!Fh>%_=gGQqvJp!#2MGL>}du`CZ5*sOsYX%8U1*Mz{L2QGAMsY&JK zWmCgb!92q3J$t`tGXUFrK#2fu@3sYY{*xT49$(gX3R{%&^@Ljr%UzXiNM_ms=7eLy zE0~t^a)yoD?jOV>?HI$h6?l7WV_b8;(sIwkf11tJs947^*(t%OAUZOL8s7N4Z-Kov zwez0f$%juqpUM_p z&I#mIvS|dXa}tYq)Tbk>g^3=o$tC0yI8}5D3h^^B&EC@`JZO1U_EVgYlY}J4Dm>t% zqAq(@8_j9*01~5oD&{Hh3ww~jiMFBkUA9x9y%sX}QNrNc_|;6{+Vi)CnS^mUo59_( z=(TTY$h7d_R<%cI$b0wG+%^5>kjck2_j!ONmZxT`C@2Qaz__CLFG~*Z@FT_v%ko|q z(7;A+x{2zun}q1IzylKWq)2C8(RO!JHj>!lkdlWQ9Db0@G9KBIj29b9)$aRFx$C7y zwh(nJdZ^&BSw)`Z^&wo_S1Drm1$tOouBoTELNmr|H(by!J9;b!3r4TDzpos6vJejX z?+#Mi%tzLoi_B;=7sjaw0?hTN*``4`oa}_?0quaYZ7%(+H@%|M1rba2!I~uo9?*BH zQO#__@Qo{8gf*ARNK&_CyaG_a*nibkw}>XG_kU@Xr{eQl)g929y28N-%?NKk#*y!e zY#VtmEY!Qnitx>chAT9?%yC=6Tq?6 zeH)G{DyH-XPYU;|z{?6}#&w?1Wx|*6f;6+Oj%=EsZKbRR-_0EGiR$o(Kd-h1Vr$|B zX!%MViD#?D`12u*7hA5HT1*|Uw;iGgyS|m`9G!5iv#J}+w+%OCHjDR^s2RS>jQh;= z{YCr!JX`UZ9aE`?I+y_CCGNdv!$5(EZU71hsIK8}>mX#nI>^9UU)Ijr#vZWJwlln6 z3wg-*SpiayHk?rtFQCo_B@)B>0KCb>NGBLzu2U`ZS9^|0j$hB03fF7-9N z(y>Y^E?*5D$~3T5njGYg1vSW=3gs6L{r+XqdwDGxe)o86Is?*om_(Y0nR0n z@;Z&6+xT1^4A~kzRxdKssA>-g)5zl(ZnB}Go6h3_FEIVrHvhm6Bd~D zHd9H*1<4j?_$%a?OmVbTv`+|10dxI7-mge#5d0|rF4N}9TmR)v=MhJNEsL*BH+Exv zrITLXY9ROFrh3bK2sSCyI{mlFvXp}(VgXED6cOFix>z$W3(w$&p7O=?^k3B1#2jkD zD2Ek+jJue`Z(bwXCPrJv4NAT*L;|u*%|4197X4Dbw{{6dFx1vPoBfloYvX3^`k`bI zRu(=RB49FW{+d`4umk-)nfi|Q4%U|U^O+sdYUTS+idjl$9HBT2Bw2L9Yyxs=wQ6@T zZ(>$x3Hb@LnP&R&38hy%W%#tSLqkqgTs@$PeqVjxav~VNkB|+uf*fBzcddrj3n^UA zUxh4s9X9lBNy#>j2Zsk{8A3OLf--5j(OzF7(DGE!?$wd$Dsu{3Pz%*j^6*7G~*PTD#XmQmx6RXc@?CkXIal2_nc(e}XMOm5HUw4{xV1eVjc9aJv z@-qzYk1_;e4ZIvrWS5-M$p0X|EhZ~b!o%jnTJka3TgwFY;fn*Za4!{+U@7OAC5a2SdvTbMxRmt&G;R9%VrLuz!Ibvya~; zjzcjz6O^685+n}wp+bF<)09^4RoNR#s9y`V<@2Q_Rv>g9J4eZ9?=G&F>NkxSS|E3K zd=5y-m`i&rXRI(+`gYNax;qZ%TyY20f|$~dY(jO6h6hB{Rl@O?Y&unBUokL|S^?qG zzgiD%cR5yHtCOKt;bg@r?Jfi42*)Am`;m~^PpmGwa$+XnS*$Fb5Top~cEOb^Z0{<* z{bAB!PSI5>IJhKn4O5li_y^=QnCAJB%VMY&ABs`MAzcju>T18-Xd?zFCE_&WDvgML zH6H}w&SyEu7v@WHLh%;+$c^(MP(KwzZahEl9DVVN=$@V%2pAfjy(8XJ&6}xEiWL+w zR}xptiyl>*2#!q>G|WcI$lo?jS=Z=w?R@o;_ydOEz?U5$6C!FYs00k4-G$sy0^@BF zwOW7EUIw;b2L9Tl=Cic|OM6IyrJqJJ!57+*e-(SNUIaN}WnJPZ@h0*h9;45390m-Z zp%y8@T~e*KxO|&d$3t#_rr=4XiwrARD%weym4Y`wd>hGg%@o`Gu%+f6coCcqP_qTt z-yS9RchXZeKX`1iqvp(J`H}qhuh0a~MkE052N&wdtAR)}wx@5dx;Ra!g*$cZ^*YTr z$*Xmxld_OG*Tb#9YfDbJ+!}M9_YR3sE4tb-}tBEZb}RU4Fo-&M|+d zc-cIuoD*l^^+c_1PkcwLTd6Mnut|YGtlXItEK!6CiZJJP4=^O;&eGD|S5DOn3kPn3 zwq@cmBfdVpQ=6;Zy`ER$yGG{;p#c&=%aZLh1(uU&r|43(XO>I4 zEUyrP{IrmsYXpjse$=!TQByqKC*LSCmTAY{5LBM1>AC*x)Ru5!Y-j13YdIGpyCD=C zai*>sds7q((I(uW;iM)>{#{gr=)Qhwv&h^SelRhnZ7k8RX!{@8a!TzV6$8QPFoHM& z7=>lYk;w%7$-t;YY-I)f1)3xodp>4R7MQ^RUcd1|I9R@7a=t4;prA}HZq=>dtGk=Q zx90NCj-2atHp-%yGT-jen%6smy}zB!w-!-z0eWuzYYN%_)HCzF#k3s!dSBnI^VeK1 z;aoZnroMz~cn`-%af#K6|2mA9!M z%{8+jtN~v9vpK zI(r0+mQbCg?*L-Y+v8pMR2r9qnsVj^2E!W`RCk@g8C786SWuw?joe+r#hKIz_q+ln z*H&@)vUa(vZuw3TV3G(v8-npbk^aiE9NsrxSHM*NjJWjUxw ziN!z@P29I_P97!b1SyH|YL{}Y<9Iy@NeP3k*&-9Y4200%{nkh<%iFryp-k~XsQSyAr*~GBmw5mGkfV@*vI{ikfX??dck9v$Zg{F93a~XDMpA5CL+W? zx4O~laoq&Ubk}1+_i-XlWkFU~drO*G=&v{kjGk>VF=uq2#kf~=xsjI;B6 zZj=r!MD@(-77!kJ@ueRHm0`DSyyfy?sp8@tk=3<_Mc5xvdkFrTyrFz|2k7R_Wlzlp+#Zj(D4}RQ@sFWqMW4|NqGU%TxLv8y+F>ri~D-Yu_{Y!>de1 zwcawT;Y#v)?93o#kr%i135)jDjZh(4&#-Bl&KmD$~bai2rQp>U)&5NwSrZf zw@Xo|&wN2Sc$}D0EWF%$e_6??UvNJgcJ217W7{DU`@Sk3452m#^MG1Cq2l-&eFq(n z0ls0k(^~FxFs@q*<9W__KD~*&#mq_5^oAR!x*8QRyIcGO!79Wa{?{unWS1*G8*mLe z$PgHcA$*&tN4wtSs?Cv~Kp&4UxCz8oW{t%GVxE@oH0%NDEcl6MT7dGBMvG!k)~Wfe`w-Y!h${zZ-${S9B|rY+q}%fdo>^Vdw+s*9v0)#M+X*W`gYWmR3xi2!M zp%#J}6j>FhtpkoUU!%B})y|KnYo3%s9Pt(kgb+Hsti1U36(RCQN$y>}@rSDc=OhmK zRFhtz*nXv>Z?fo#IwIdzY>RKtZ3oF=T z3l`ElrmPQL2;(h9+hPR5_Uom93j}_#!v0XurAX)lHiG+OEK)8+Mz=y{Ix&Yhi`&bI z>^071LYjsW|HkL_{QUO3+c}j}{NPOuO{V0IgRGm=0lQ)x+%`Y2&Vk(}CnpbPRXWT) z3)A{k&c;K$qf4Wo9AUPWRbTnW*D7X9VxyN?G(KLR5Z@doyj0Bymk<2NcEJO&Dlsfc zA>R6@MoF}STgN2zEhHtGsC4ccNJVji?CWVXa?AgV|#geOC>xihSw8Guh z-0ZhpGimN*Cy&(Gmu%40YcEfOjIqZ?jHZMVL*W&Y(y=Er7CK{JrN}f+TfoNmD|Nl@ z{@Tx<1fp1;J2foJ|HX)8s3Nz!l!`2$SoTuP|CmFYL}~~ft0963!j^s{WbK7-xQL(R zf=jz7vxFtfkp?Vj=7(j7*v;Ax+vfxw`5?gE-0rr zO92WxUg^-%5rqnfx>9d`+8lwE+yuzU_}J=p z1AczIOGFPrc*XI+c^8LtjilG6I(Y+R>`PJ?4x&B=Ij}m(*GP@rOUP&#s3UNeAJIK& zo5w-AH+dCnw35qY@Uj>J=I7DrlzvtGr*UUTl?&QeL+m16`cn$w!-nxlb>63tmb4+n zE20&{1mfM3$ZoFA@f|No{m9|5#v~KTDY<+ksfhQZHnLy8)y3=0v#v;pwu^`VT4);l zsm4N{vH4vW*xcGQLS772KfQA3t*Y?=qk zy2+kx@m=tv5PPFnm5y{&dKIpcQKDbvQ)Q!py;nKZ-B}JwQ2AC5$}7Vie+a_&r>Euh z43-Um&IL{e2I#5HZgFxJuMdc1LBUEyYXr98C|}{Qi>#yA(0SAyetSz zIc;fV{lq-TttmoMI0}9@8N#envoMp_{06o{7y6_2X+Ez>XmDQ$ z%{$D!q-KQV;=PZat4G;N9V;QWNYaIH9rS@>3@p&t%!JF4HN;{eC7~+7GE!*DjU9^9 zq1re$vKLPO)62ugDIB5jY+Ls}C|Ha9H%25NT{}ex>*n^O%3bNKX=nS!OvG=Ty_*%n zZoSG~P0BfUXpX#0%BOkYXC}osV0*Q?w00!08P==~zxgH72Ypjt}#@$8sCJ}vF_?b5e%eYqubh1WC#Y!=E# z_?VqIn9@2G0y(;i+V1^7FrrJQ?0LHf#Uc&rS*%$G?Upcfm0z&;6}Dvx=B{@SBh7<-M~_&%pag2%BylJm?68-p+}mC59wyBdFR#?u`O9Zx^-K)V)FXbUgEowFo+r2Or4R?7GfuPY*K6nl6oSv(G zcwmr`wq@oSKq!er>e+tKbvgbSIqS#Q^yT+du%YuzA;DLtC<07;FsM`>VbmuR0>;H& zAarS~uh}i;O5d-8(|Eo++_WDuFHAj}LDpqYB1=MqM?^DibUCj*5!{bWiWG`FJ;i`L??u$@j-UhKP1+6TY1gw-R25Voi)^#SJA_x;aNP;N-($6 zT0ey;Gf1edC%?K+Knu^{XT03wKDrb5%F$D3aMc)%x^ww;>cfk9LFdrAH}OzppRmW0 z6u9BMPr66qn8~Q(V-{*$(Y2^NVBYAwCDV^&@b1->eO*!_0pHIkcCC<=x#dfZ-2JhjoCMKTb>6n&TzvqEJlWTQz77{)hgRdAN~a}b56|%O zr_i93TR-&Yt@ru07&O~?#SR>=Yd){t`orQhQ=NeZm{Mo*gBLVLu2&_pTvgzI0*w z3hI}$*ub1Csj(x_++}aP!RI4 zM$fQl;Ur1w_4l(ohNhbbpXH!7gzq%KY2U&4w~guj%1B+v+R6cNEJj<=)yB|X^L__D zpfUg`IF8nQR>BX6N0FKrm`aSa)!|o*ZD-AqV>W})p9@t*<=ow*N=I6u!#jw4j{|ZK&Bui zTP?Fx`69_wg@Doap-8o4?~zpCJyQ2ID+ilcBBu5!AM>j{LvY&3A+VZ*gp2i)zy+Kw zB3%&1g#$<2K|)pe7Y%fa8b!QK9}I%tLSIMD6-C|(f3qL{hY zi{2@h9=}UUmJXNc?2>3Il0n1CVx@gyUbGVS+dx(qkLv>E4~K8-l7>6q^=9! zb(l-OFZ&|Nt<+v;*EsGkM*MEkVn5N@;>qRi*)gV?E)=ePbdXI>Lom9~5sXpx1Gkf9 z@5Nz~(APS6)?Wh0hBtkzMX^gK&DPboqXT10Ow@vvTls{=Ye13TwNG9KIb6ITNR((~ zl^ac%56-*fP1(3S=N=C_n@Ar6d`lZg)4y)TR0?SodS{Qcnr_PX_BAFmiYF?~?ZYOd zt^pMf9IydV0z?XAC4oWEfY5-TprC+|aI};^+c1P70M^|u0AC)U(D$?UkCWqJpZi=e zBp7u12=M1?070B5Vxspr3;KU#9~TDyBPUYmR!`+65YQqHFrZtHn-8GN0FJ$huAQNQ zf`gr@mGQ&Toaa618jvZt_ufzg{_p*+^>@RgeIOXv={nyF)Bo$k!yfiI<#D-l+}{Ym zCm6b?6emlI*Z&Y1=>VUfgC5tIzORn{yWKH7fF4iDbK%D&1D}p%l=U#H;vVJ!K-shBm)bzmm?bLV#DNuv&FTmgaq36KI<uLb+NRgffe-3<*#1AKJkFi- zl#;CbN6N#LJ*PZ=FYYNt)%1^)Ki)Er56eHLw7LF~@-R8i`||kk=TpkD_a7+_SJiXM z<70mJ0ny*hEZ~9iBqtG`=fxrTW8RN^zVa#&qW`{Xz!!vzuREs<51$iV(HJt zA4esh_S+}=k@&yDy3eH_2i)#g0l(W&%p>XFam?p{$Dy33lg||QJbd#zO81=dI8gAk z8`ufYDSy0@9y{Ql0)UgA1O9khJoaPX`{{qTttWs#dF`K%=CNn^DQhM9ac6$B{=1!f z>}!3>nos#N>%SY}$G*g;x|<%=&jk^^a5i*xB}!@;dF0lt0e*SU<7!q`5**@QtAv2BTELRHr||x_{{ugJm?{7O literal 27887 zcmeFZWpw1&vL$S0W@akeWoCAn8OqGeRA!gU%*@Qp%w=X~W@cu#C%gMTymw~aTHn8K zT5BnlN-0x1TRS4o*%5iZfFOXNfPjFAfecTx64ro$fQA6Os6bF4nnJcVj>a~Q zx=L<##tzzauGUsWxnLkv*+3wG^Z#D{A4Z@pQ6_4I0V(h@;f0Vyx2*3>rL;7(I_RCF zk>*_GWd0PcuSfR=3**CM5Fxt}1VnNU7FpuJV*oNfV0o>Q|f&7udUdWLm` z&f?+rzT|BLCcKC38#gTLDoAbX@*v{uVg)2E)r!IR3f4ROghHbpn977-0i^?Gc<>!N zZ8N6*7mO}j$~by0F5K<`CJK1AG`=paaz|PMcE?tSn?hQei`GY!Qj;F{iu_=s_$upL z#C*rwme?td7A7+797G}R%2v>KT|VjSnr53CJTC zunvJ)x}ur%?4-C7&&JyXgfSS5S8v>F-x8034c08WYDP0fUWY26rrLy82*Re}-%8eZ zg}CCJzecX#wA2oTOm;sbQ~yGe`H7V4+Z*CyWk`5!$L(5z_;~f~<(@qpk1Nni-*tcWo-Z+7 z&{=!~Ng^}Rz5ESlyk4Zz*d+s}WJzp`$17;e6BG#O^Ai+E{=YZ{RGkiE5P(zI1lT+* zz$xh38(TTh)BW-Kw=?*E*aQ5hrkBUcNP#i}oPqBr@mM?eDmBTB6}`xjjL|zVW6HZ8 zdrEZv@ApShLC2g%f}iPCE}3pA_a?P@u6aoA&M1i@(7x#=v#lyUQt!>pkjQcNq7i4} zJw7B>rKe^0%n{W4IZO9^q2)Wd{&eJ@-dIjzD*e8^En4OrY64BP@QB)nb@d(0if{DCWAhR0yGCOCVprjAVk0!u2%Few)U0=wzigk#L#kOOSxSR zwD*pgk07c|zjKx<(RhVSZgKC@nSgbzj3}|b?gug|s}2n;39;@+aFY1% zV1+w3?0`$H=2ofai6V7VmwI=sUCCZdpX^{Yr-lY~)P*))0PSR|YVlgi&lZPW{aUa0 z-B68wNNgTZ>6-N8@3yOX8eNGCRcldpteDS)!i8`Dxjf3LyUGAXLjL}W}TT)>Dq52dW=(lT4~1XSjrR;Dw&X= zRby}R!eEuP)CxWA@?(-lt%29doq~&d$c-*Mw!%!egdEBZ5pm+Gt>hdbhA6yPQJO`m zCf^$E$S!HI%0kwVG7SUGhIWac7ZWZV{KZ#mTQV$qW0X@FHxF}OO%OVfX0>$nDiAcG zVMlDQ^{7OlwiwB~fJVZfyHGFFo}b;Q^;j?w*)xW$1BYI!_@N{{?H7lV zSXaL?bp$S}j!CKXcaUbOT*Uf0S<<90Qos4{UG&TCEZyU;-n{Wt zrkEC`Ji^Z)>!{V&tEOd)L0qLAdl&N2YR{Z|25eOy?$g9z#zH8ZN!KJSFE!!ubgP^_ zH3mRW@X}xBt<`nHe?f#ifj5=AQI77NTH3fNw8|nX>O$xen+&Rn(w=plDQjv|!i~N| z<3?hd@G$<>4m{EaA1GnBAz*FNfi&oHzUE9j=oGx4KRg$zXljAX6SBVa&?bRqCV2!; z>ER5@?!k_8-jwbWmp%1UR&|+0nB$CiLMr#Q*{dR38TbRohRaT}8XpeXs*Emw#wD6< z@y>2pB z54dK(l5gRFzxSnPZ4GXpD+pRf`d&7LnIoQibot=si8eS22fvzNOG&utR?lMeS+Q=i3XkN!xw3EN0G=}Nk!B(VVTGfLU(FUNx$V*u9se?B(wQLrvocsUw(iSgc*~szrMnl`oILyZi9bjfw%8B z;9Nat{r-r0zED3^kTex0h~jxq^g3^KZJl<63Oc`GOdWxWp2N&nrJYjpI6u0c7aH6! z>a>e*ViA^)al4wfOv9GCkD}}(6;sSHqSU{}2OM28WfAHTCQBWFs8Z*jtp_%Gm*k>j+u=*~A9&pFeaJqcuCExZU zccV#`lz-||EP7_@qy~AJSy}s1>e^Yg1+<&@(H^7C?9IhajTl^2rVa2FZvNVAT|=~p zmxLVKTWBbans4)x^DGsw&1{jND!a+cg7F zGDBB}2cFk?f>tk=<6B&GZUVFgkJhw@&JL+ccLRpMS!Gc&RO^enyz4J-TeXGS&3*wz zk(BZxMR6zm`^<sz!iRdXtbrPr=i5%*#y z@u-*zqXiaO_YkxFZI`4&Zz&AhAcG!%0a{eN(pg>xMst`@vJkhv)R!#UD}u(rXbtXY z8JXhk$#S1H@~h^L?YSk(Xq5DN$0|+jCL3!0FSZgatuga1I>`+(VQsz%Mw%%TGG~+u zsfa(~GgbIU*YS7D8hm)|7S-*v@D8NECrd`3^!8@^j=(7PR8cm2w0pY@Z}e-&G4^<} zNdHJxZ)StEG=qzpu3%HFuZ=8*02#a_LW)94cR_pb>#E^~>SHDw?_E-MGYZ$4i@`%i ziV7xs{DI;u<m+Y#9E9(c_7vz3kBS$6UPeD!7FT2|(7dL~w>-(@sQ8?3f!qmZOuZD$nKF(aDC|5L##n>RsuF0dzhg1qr`F$`RX9wdzc&5eJR1_m5gg3}MsCXoS^iG%o4j#Fl8g;wlzubjMOw^>HuU5WxE5UV zYbIKBCMZ%(E|y=y8v4;t0SH!9DCOv6%#iJ5=r5aoc1aqQ4ZxLKiO``8#m;;IS9b1} zC!*s9->JZ>=(uu?3w}3`dcX4f5nKp#CS=cL3dzaWEI1d^PhZk#IEU6`QFJWTnboWX8#Wct9xOkVmUI2($;2Er zH38uTF0){m;J{+<>{C+U6qX%S21gkeDPJQ&T#;-Iv&G$;tA1&legg{l5-hVZJz_>0 z3=HNHVpidPX(6StDJLW3^~?lx2O11SbMbzGU0~P{NZL$V8YK2Z^WacOE_(+8h6{7U zXHNSSmR&w2*ox(<%K8#~*os;*HM5?RK8cOVibUoj)WI1bIL+uCEiNpq1`_!2T%cr% zT8cES^eGrdRXm?Dwuapr8smxBVH5@<^q!tvqR3!BpJ@duj~ej&5$^^nRZ1Z?mf^ z@iFgf7Rw}>Is6cMOFL-Bv)x@s{n*8(Ta=9)bufwU&e~@t$TS#5^<;WSJMqcDSQr>i z3FyVFaQr`iO!#Ky*OJ;d)>wE8P=6Qc+6yKCg~q_aShfHP3=q*l!NzLW03jjtG$;!g ze*0lNP`Qaiew#qv{jHZo6Ta)Igf{zbdvNk9Fw%DJo>IV*x{e25%D9{?7*cH>EP@(F zPd`O^1AeSRoFXm>wCjlsOcL_xT0-D@D|DZWC<|Jb0Qk)Ru-{ z4fT%Fxz+2iusl+-4u5w3Q1{M~Pqk4W_g$(WJo(N{z@=OZBs5cR!P>P$Z~`G3L@wXg zB}YrEUO%Y;sjuE?YaX^hIf*!=!S^26dwvYMKj2a2pqMX6l; zA1%*4LDgGRf`H4YMUc8a3nEv{ngebrDfcD0ml!=k1#8C7N?6qSs_en!W?+GWkvOvF zezO*u&-9!N2bXax`*otrA#7WWUwS8p%>F$#FaN=cD52!V$i7cVmBH~x=?hrJn-WH` z92`FvE#(~L*D|@C66tx$I8uT{-yD5~duWa466r;PpOX+LsCVd6#)tEi|M|xL{O;DE zoN>%cKEjZkG2kaEl(Y6o@Afa79&NomJ>Pd9k3Ah(8_+prZP8tFyFAiges3~_Q>mda zEk zeN_a_JH&In^Uj(|=azb|DtaqX*P$C#B^6PjPXxwdGbTPkgbv#oZ3An zDTC+FX%dYhOkJX+N%|A-Zz;Ws(=q$HMl|r@_4$=*YA4Z`J6+Xt#GCy-*S9VL7QInf zT%lPBZ}8DsonPe!JCGZMU$IkbX}A(=Nxnj34TR2x)n)A?txB~+g-=Qf9QQ^|N(vt@ z0za3hXWz9N(j!w+zYilO87sf4<|KOSmqXpJPkLggR0e3^dta+V^T>1ozOZMWi!fxm z?_U%$Q4YD#S(mnQt#P8^32dvsM|ssHUs$=%ew9f0jLgHp_uc0a_USq$v`rUaH_{nb zo;9qS^b0AeD>d)Aw9ps>zC4--Dn^|{b>LV@;CgGlt6fJ?(dU^89fN8MVmr1@WB?iWPwLa(+X491MC-kbhhSGWXL$IbgGe1 zwv&CuM2^O7tS5Mu3|Oe8HHO|hFbnq?1kh}4?7GQ}0kaF30aa5c0X~;R%Hj3>n@M|s z5D5tWfA#>3q6BUH1mHxf44#1kC@e~e0^zNGA5l{#`(l^N4v_A$Sjg%I3u}~ce?I1a z?!QRm6c=Eb9_`1DZ6l<;2nw1zE)kSI1o!iA;Fn%Zgl(o4PVh~&E_Rs*itj3_^R<&u z1(~A zmWJ&dCNW4_-tM49?huc7?G&aVz&lyJYWu+a^7PUA-D@9hYumYurZP9{R@i9#4;|>A zm7;>*(3EO`uFfFQ9~qZFl_EzoV{2pjKVSdsr=O{7hT*cKdD7qU!`)syvF(ncP(Gzv z*S12dQ<6t%Xg*MtVPi{dL_qt*^4u55i%aRkcv$AdL*SSlNfEw$2Z6SJA^n+;?VjI| zep;AsyjbnJcZr9e;c$06HvJstVsL`5PX{HX;rXmJ{AkByU>GZ{`4O?5J$1!PtiU81 zPu{#wUwuWd^YoN=YbGViF+eaxX#m^sCO)#PQbQ%m5Z=eh)(ic{rq3gaLhxMAad3on zH&CzkCBdQ}E2i%e1p1Al^&VJHemTsF}M{pw(F*W-Tjy>pm(y%eeZf|I2oE)M` z9E2d&+zQP*j=(-wrS9e8OG5%5yg(juIZH$Tf_jysADpH4Ocla<`_C$k#;d@OlhpBZ zc@Nq)h=LbC);GN=aC!|_c**N+9KJIaZeGn!h=QjToDLm}N8jHCx_%^*vAwL0U&@tR zN9QYvP(_}H5MUzON$kCa&`ie#mXbTSm zQ*I!nh(^0I$1?!;7D$@Qm-cwwL*KFEE7S+X5LcXmNcF8m*AAkR%9_;f>q1m?0J}Zx z4bQ$tWo>-kANxVdU4EvIS17C7uTrI?+S7M@-dx)9-+sL8w_+l8N*3{jU{ZWM%VqI@ zoRCYCok71m`*%gnSz(3q&SK z1Pc{t5^~ZN#jvyWDTZC_ZiKb9*TcrVnt5w9KK1N7jO8%tK?7D7x1o8*IJG0NV`-j0x0sr+~q6X9>|Q{4MRT$qSU zpVJ~-BejpzKj-*_5F0Z(^bSs#(%cb^bo`}o>@=zdi7urKZ^07m9fl#C`>fRwc~zWl zI7jLb!C*}IVM(9;+x3_^vjhq1YY2xwn#cw#h4z)U$tBV~+z)}_0lQ7IC78#ukS&Pl zGIPaDqLU;}m%bYmlLt?&Dd--$MDyDvgGDyViL;}zA{C2EJ?Uvi9K*Bqr#^kbpmEx) zLs8vGZ{@}sni@J%Zq<1QU+@P+!{Ec|7a5++@y`BP7QR_JyQCos+^qi&)!wXSsFb5oTy?cqlKtAomD z`aDx*Q`Mv5=-xi85}R9+*yFFAh_6}DIgYw?R2#^@Pf52TOnAHn*CS_mhm~RNFuE7Z zyN$LB@yxNKn4iDIOnds9OyN+Unj9(_l@|4+F#_Y0@|L@oJo($KyQB`bTBSR4jT+C- zOKVd_j}1y~Tj2dxViH+AaeK5W(0LRp`aSxaMPRri1bM)y5m`A1`F@{Bc-vU?C?O*h zT_y+}zQ7Z^)EG^*5@=RM!AI2wQD;um6DuFz$ZSB+jZfu=WZLlPQR!B?MLs)cTq-sY z`2!Q^jW~Nk1#VK2N>bs9rSJ+*UTL%khuZdIt%R<>$-#ycZ1M}IMCFM!S&Bg3 zKfXi8;@gKgtkQTp@0N@mCtiDHyV*i#~fjG{go+4V&ZB)Hj|VcOaF{!^B6 z4sP5A8SZ}Ht}9_{zfBcW|5;R9_Zz>p;c{ijzS_#UkgChEaZPJyJKUi>$j2ZD>Hq}t zHFXCt5#67lDKijOG2BdL$lGb`hxz-PUjxpwHKAJr6iLr8eJ$jvS$dosrVx59S_l)R z+GY0%@MxJrNA-W|@_W<3{T{M8zkga8_h@S?;AA)W5pzuQoXe)Qxt2t;Fz)da{t|wE zyzLU1D5JGuBwO9u*&@KCftL!bT{ds(Y=J94r$X}*{^xr2G~U{6J1IQE%Dj#IDLYJq zeUm1X1-Y?jo_aB4f+Tlw6YhJq2R)6U-u@R4qYj`)i&na~f2r8I(G9lq{*cPf)Yj!z8IZiP>OZ@0+=n1#7F8sW3WQVZWyBfGt88}aF+PUyFlS_5 zH(g|B*r2fBMz-{MueC7C^``bWrV2S^VA(!bpXIvPTSG#xyvS(iJP4F}zpJ@4=Z|%2O+~>{P-R8vO*BbZ1HDpA8)Xa0 zn-MycHFzG|BbXjC8)OO+cer4p7kg!{6clnss|gO~QwUhn7#Ti*x^6VlJ-~a>V9eW-P^lUEfdGxb8qJ8ltL>yFgmd50` zS3-%(oI1WFfrXL4JC6-4PO7BR*rF38kh_Ac)H9o=M{viGJ%p)0K@_6cZ-^B|0?e9K z7RuCNyj(*NZ1+?JPff7bxrh?0Zv#gARP0m+WxQemzwyq1V3*}SmA}NN6;l%QBM9Q%;BaT z2xo1g7L*bO!dtA~1f$7W6DZu{z^^*oHBTP(7_Eq}z`s7+wUjV5K_4p~y1QH3S1LvG zX`fdPvd1f(oyV5H!K{SFLdBM6U$Jy6S%E&l2S%_OUS`$;CHE!1fe?Jtl66?0JQ;1$j)SrC33W+E=eDPe}(Kzf4(f75dVArz7 zI+5}rOa9PDy$FPMdAt?6!TncV<~Rbb;2=O^wVeV82<;!1YNl^*Z1mmH-rUCYFN4)M zm)#Y|c#rDij=wP#jQ00WxzGU%HzOidi8gt%s7JO?-mzC)Z5(YLAsegm2%F}aY#Zho z&eYuhwTu9E4`t%gC?aH#bb7ntFv+{v${*h2%^NH%g?_G#(@+6}svzgabaJU&S*0=hP6%BSIiy0gb*kZ zqotCQAAThl3*#R)85gZ=U%O>egWvW?>qjxxM(FBDbKFD1N4eUOL+%Q2qu+~Nqc1u; zM8N@e!I%uz%0i8NMm9qs;a=|-K&)AmrK+l;x-d~CH`)1C=QPt{>~0lSLglJ88MO=9 zKz!RSL(ywDz8G;okKP&Q>f*Xn&U`}l`^O+#G6rc~;V)g-I?u&rn=`BRoQ%PI6JCP5 z8E@Qjx`x&~WBwk@$X;y!o*^C2AtC8yvTETx7c7}O3!>z7b;Q#!s6%0Gds=jpHPpVO7PH)!#+AF$4__CL&U8PYnAnr#iQ`SD5D`vz-GV-Y#0z`PXV4->YW+0Mj6P- za(Fvg@WJ4(gCqbt!a@IaS|UJBd+hQ^U9ph(E|wIR2r{?i9K;j7Ew`3<|opKjq?-efaHM<1bz)$@6wmI}VL>t(p!1j&)p&h?R&qaFm@Kk{YX0lW#s zJK%=}t;y|{c`*kESE)9JfRDS5OdVLYw?m;W#{(nnRuw4t%M=(wdYC_LX3QgK?T|LU z(eti)zq87b5{l0JO>YBT6@Q}ix1#k!3I${O3@|S8tC}wL^r7W@^I>5iut}M{CS4sK zR9N~S(E-2Tv_`CtzugrSM*G-h0m8OPy z?;+#}qnsNggQKS}&LQEaTX-hVxH0|SPO~2qdtg}LrC*(=_-eB#-rX#ccfGj%2Fs;wx#0DLUpB zO+8=tE80hsjyD%W&wir`fio)17WSvj_2*zKwr>3|+!%k_QYkWLKRd#~NTfJKb1$ku zbm&PrOjYCXLq5juYRQUp5vP_I2+R*A~4ru4lj??bmXEo;1OT z-1f|paH(aK@Z$#;9(<>Lt&wOQ_2jYP*qQ!SSRSpEkdF`9WPH1m*AG~W4$!aiKhI}R z>MtioZhK`NF@NL5#0rlf3-(i!bE(K`A=GFM+WfGRc74 zV}+hp8Xg@9Gb1Z#8-gJ}A@|CUPSzNPD^2r7j>(*yZd%Kpe4br<*pivE{T<$X=aXmC z9k|}BGF$6t-iFrrk5Sp!OguwH(V3l_#jOnHVRMKaDrj3ad|k7(A3q;F~%ySHDDTq)R)* z_0e)uHt97|cnlcQBnWP6Oy2w!u@`(jkbzzVL3UMd@#Z<6c~KOMCztb;M%2~Vl8|}< zeJXLvO5)b(Fi`1OXySP@D7-g(CCqSsZ-h&AQV+SAAy76;j|KnT z4bS{W18r&8E*bulWMG~Vl^E>?6&*#g`->)nbJoCey^NMv=jW^HxocQIE!4R@5nIdwEM#GJCs$6!dm0v^s&_NdDBBP>~UoSh$awFe~X(CCp zBS#NxCe7tQSixRw*(vP}7>PI_vj<>>q_HJBOV$^33rCffHz(NtUT@}92jMUe;MQTZiEBE6_{5O+3Eg0Ssn1LL5HgbA-wLGo4GDuBpw zEieOPaQ1I%6zDnhZ(7WOXK}dE1hCM~*Tf1yy0?*3x^#r8RaE(MvTg9eh;d@M{jD(d zOQ<5PAoiePov&X}=Piq$`tkJSvBMSC-FX57k0Kc;4U8s%)tNMQ()JyZih;yeV z;~EOIGuKm$l@nqDHA1begS&Y9c`w&wawfM8wJ+siuu?rXU5F!-9GL%t|?#3 z6Ekhfgu8R~$MK3czE%HvX?`Pj!9@lS0pm?g`sN)lkSGInWr3!1oYVYO0kc-`)v$>|ry zX}L?IE3T-+Up2$!Pa&kYd24TKV7Kf!klL%lAFq88LK!ekXX`3<@9WcxA!%CI zXJ9Fyh%^SEcLI8Le^kX8+3UOf(PyJ~wzd-f>pdeK;Qd*GrtK^Pn)hbR6JnywZ|Oa{`4c_UKBu z4Q{WM!bs?cW6UGVU;d?;uW)$T9q=fx+~9o<#3!%Vc~uWnyi zH@g>N5{D;@m0Z4 zH$tT*RSQKFW`oC+#93^DX~K5m(+3_H>Urj3UfD9=oXmqjSm(Lu8&F^>BID?Ao6(^% zQ1Vlj_0j)jENGj-b1S3VwoJu5ZGXNrZ1sbsYJHi=LB4Kx`38;LMY1`ze;Q@7Kq+me zMtu+c5!KlLOl=L)GC`T9AYrve5t?{BxIAG2+{}!rbPQ+XX2*H9YXR!U8e3ZdC6HAO ziveZ-TAANgtFC57naB>~*Xb66J|S9Dph8?y?*r14!mcCu8u)5BUms<4ZGU4-a1X;y zuR-S5?pL1j3F0uCqiU zd)OU^@9|UqOvBg7WVidtv~q(+j1;$wA*Rq9B)_7Pj_VDh#u<+|A6!FdhUi-wYuT5i zzU|__g1J1?UQ>ImNYO{Pj_eKU@TIqxdhxPgcWnAR64rJ+eP1{X%ZoFu9^`$eujb?D zm25lDeAweZ|D-)9ux%sp?-*PciVS*sw=>>$vv-aS+TRZBojx3&WX8r9%-Y`}fUg_o zmOb1UJcs9v?JM9&i|02tlO07nxB`h=2+*M30&6R95mt;9g!6)xY#2vXo26<7d-0lS zy2VCdu-M$OlCOGD#eF_LXq%!{w!c&#-NYbgx4p+GUdPuA(oz`)QJ4lK^!y0#=VWwt z))ISGch>SbDoNT>JuFX`W4v}?3NX_ec=F}Mto$j&3~$0}YCDkO+r|lO9udm-Ojm~j zBR!ok^n`y^_<gU&m+Tcl3y{P48Vc*-P1ontA1^&mXNgKa!=fL1 z@|&C#Oj0oxt$Qb|`9c2$Y$o6`m+~GGMo@kYN;WzDa-+rJFzS@prw8Z@%n6^3IQBgb zqZo-s(~xF(ngXQx>Svbl{v?cR-}YFuLD4)BSFKE{yyNm z2YMl~CcXO#ND8XmXRxUMK(%b1-@()9vmgGm=mnMiDkDkvM%V{eClPYB7sNp&c=$4T zMV}lRFBXi~FgAO$FPLTE3r$H~E=F0!cyVwhTZ{HS7*|KnH$cqkmFA^%qf*bc!op?2$^;+$7nVF&WZ((P(Np$~tAZ zX_oN&BJ-&>ltfJ@%qjq~|BOBTmoDQF0Ha^Qfq($=*dLDD(AL@-@W&vBzcN(uGByBt zEZ`C1R}k=GjImUsA$B7CbCG~I-KC&$OOI0(&C`5;(flUhiSlT$V^LE?_x%O?>`ny;=d{>2L?C?ZCW!K+0 z9$C-U$8jUZOd$)~g_q!hXo~v`SF!UL)k3y@Pu%{Q0dJIv^ zCSBR<$FyPC`)05@+uLrog$>!qP3ncaTx+usmBS_$G?|KGU--gIf~-Ew=L07L1e@C- zR9S{SFPwj8M6FD(0aFcmem=D<7l{WSuY3y-&Gm!Jv7-L|(m^rj=b+6!)=*6;p9?O* zqbQ8ltb)-o2U6K(vG1*#z;^KvxDef7GO(a*>~B>BrVNUX0Ro@xlx=A*3c)cvchYUD z9Lw$C9)~jhwDlVj7d-K@o?(ji*@-tG&_OEO*6H$#$n&CNv6R>Jn_?Md(K{6u+gGTk+G4`Kj;fcv;LP4{wj=& zos3Ll0C?nt7X;EQ%PuxDZxG~9l5<`UAk08-7`C1bsxphsc9S%MM)Sw1IP%jpTNBSs zyvQauUz$pjIcm}|Sg33ZC-zb)(T+?x77D#`rHu6Yp76G8;=#AuqFy&O1!q9J)s_=IHK9yrv8xW-v_8LO$WZ$$f@tu z1b6M&ncdGB?}?#cI8DVTTqJmIiPn7O`_mH6JXim%;M8M*+zI zEESjdKBtH9Qd3cHk7w35LR2V#e(UPD=Pxyx+sNsv88;Tx6=l~ePwFpDzkvF+vdNkT zQZ^vhs4QM|?6YlZyZmv1+HlPAM8WTSFQNL<6|>uW*{gUqLrg$;H%}sz$6C9VdNVNT ziVYNZU#bXEW@JcP&yrI|y=vpY!cun$$_K?mVZ6T17Q$w+YoeG+NYBt(4;LPzDDF+0 ztkz4+IiItOia|aYPjn{iKbL}?mGVF{%lgd;+KwuoC57+P61!)Ll11bY^~WCiAF5BN z$JU78>9eRi#O@5R;uqeBe(=|Q{7ZD({S8Q?0jRD5R#bpd89F&Q+FGkwThW_48e9Kq zJw&-=Kvda8fD``Di&Z2yLJ!~>RQb-teLb4mVex@c*asQl2rVdIyrCo9B!Cq3iT{~t zLf}l+=7cvdhA(-O(T!?~!&9(anlv7EKow-7DB}+FBaV{hD|nK+>)ZmPk2KqBA2BtL z^Hqa+L${jt4Az;Sk}e}}EBE{yr&is#u>|oO5rM7XA|;_O=BL&mtiThu%?98$|CvT> zw4?#IfFp7M7_k1Sq4M^&c7KJw|7mNDqPzcKobYA9hu?B5X~_>Q_9cV?S)#?6Z39R+@`t!Cj+;1F~cb8SN)q)O5mqS3sIT(Q@` z1XO3CqrCwD<{-csqXLorH|8+?VUtne1=}Thb3eKi0b3} zIG4Y=Iyj-jS`CZa$9}wWuHW>iEp~NC1mC8Q@`}x`=Un>Ys~3e=_PSyO0GqRXJGRD; z)TtG5T~z9|uQnk%MQ_nlG;6{;slNAAv%jb=AXqC`HH%=LnVh;?6EBH&MGh=T+s zcnU!I7{E*C@_TrFx5}CbUnekT^m2QZ(u7Q(+Vfqh0%^SX-Op^NZ6|5CFj zXhZ4kTSt1OAU~WLe))Mb^F-%m%zM-z>>1j!9;;0uUE3*Rl+EpySNZP}uK0ef0k=pp zCStod5o6?{l=v@&<|K0Z(#W*2!6+&_AZmdMW0F)c#)64uO>mI>L4!9)#zRusIwNU{BE54~mq?8OCO z0x6(J`M)u(f6(E7=1B5mbS-;{(E2waUlF=pEMrr=3e1;N;a=DVAl%zo7gd6B<|4b7 zT(WZ9k43W{_IO90Gx93g2!Bd%OuHG&NY#o+qOkNJjNob9yxfRe#y$a=cu(V4h13|; zb+oI)dvXc@5tjFA3uN@cqc3VN#!fMH&tt{>kN6C}v zdrHI;N=^)S`ymYPsZYsrEw52TEPRYGCRqaJtdh=>+I7S7HHD+!^}SH6HuE)oeUj?E zAiXRj{Ut6p!EQkl8>8nW%bQuv(EHih%DyHP7KT^<6QKQ^gKcxn(ma6CVL57A`qu3_ z*~b8*xlx#tKY;EhP*I5skK|0af`1Xit6T_8Q0{ebunmk09?FHH<^f}funfZadVKYIC^j`sQvX4>=&fQ8OT-|>&*|2X;Y z&EE+8jlkas{Efih2>gw}-w6DTz~2b`e?Z{B&NqX!sqWJX7$0~5l>YzC_<;GZ;o|>n zd{7^+`^S*+&+&oaWi9RMb(UgLxhzZo`pANyuI=8b@K|g(89lDyrbq26bXsR%fe{kGE&cFlK)6&W`uBes`^=*df;~C8I<9! zA)6PW!sno%sJ1J8NUA@V*X>vR4RO|48tdF|eLV>n`qi}54<1&7e!6D(IO0*oMl9+g zesJ3^7~wcw49dIiHLdCLaOh*yjy^QhT9bm2q8^2OO1dvyMIJiUmN{lmL?K@J-rzPC zlooYknq+9I97zfWpJY6HPaXJ2;L^uC*EuN_d$xWMGZP=)&al51l50GC2{*I%rd%}I z8Akb{S($@!tp}srNHKX)%IB(b;C3O)Kw&?1lQN6D|f7KaQ6vu0vXp~Az9R8qC z>~^UdJTLR=Gte@Hs<=3s&x6TX4i?I4Z4vzQYX+J1 z3SDrT=|&nm^JHD~TXC5YEHRF05^a_dEpS;n8=y)RvFy}wA~tx&LY)&`x^Kn1N#MNpedX|tna(Q_?&THpK#^xr zW}*hOEO90)QG&OJZ^sV@9lETnjkl7(G?*IDENX%+TS1iVI|tA3Xb8uQL;~Q^N8g^w znjpT}H@H#gzV7hOxP2g4@A^h6d7;F32NwHYi}Q09XORVK4+l5hHPA!cRXu!)Wh4p^uMkr0oP$50YABrc#WZH(kbvCA+1WFNtK<5H z5b$LFnbodpaG)6gR!ad`jRcq~%bRo@8wHhD^_d_EtWC|(YKCIzP&-#ep6OFSrWL__al#(h*YvmvoG#bu}pOu$B&7>X(+_-yo4JrK&zE|L3>?&ISzsH?)Qt6k`PPu0{fK1VS*hmgYtd*9gg53SuHu& z$&B=gIjQg{?VkTuYApbg=-29Q&oZ3g)4w3dhbV4}83mXfN{F z+PY|6v|iE;AJ9hX?XBEN7EbBvK{b~v&yLas*uIX05iukV2jVB}eMxWjNjtkHcAK`? zT6tIl3W}x(fV2!^{Z`0l*FDygP*7Gc32UNV%ALQ`SjDM)FJWh{;C+oUPidHN6{w5X zcD0cAPE)IJZ)LjiIJ@Oow+G4Rqq5W?u}w)1UI2zlPqo`~Ta)Gf1FMP$PakhjP@#YI z2G&>K6HkCB#jXrfQlp4h$R#2#(%A!#FMJ-G&v3A-xm?RsCompkG@0)!saHcpa8?pH zG1#G}uMIEsZ;kg^`nDI|+d|VSt*DCu?ryFQ)AhFZ_p#R}Hp214-@i;A{$MBNKDK`S(<+mj?_v8rm~P=;x38b^f06i{$0+EK^FXRN;|73B^G94=?92(840x zGrr{dP%@ph?&tDuTNTh=@1d6E3bQeUX!=H5)r;Y%sr<_-h8sb`?)-cTwpMa5F)Rvt5Iq7{2GgI9%754f@sroZAvX& zgZ*uJKj^g%n6&7haUqv+(}#!T`EDv~K;8Re}j z$oGwv{7#;%*&fWwi?~DDoxn~%^JCvSWqP;p35LG{=e;54toMA|Mme~Y4hgfm4L0b4 z4K%gXOmG)$itv1`dIwY){WA^RZ$a|@Z#4LGSok*${v{3c|D=KAA2b-H0?+`m6-VsH zn8B#piP~Q@;QfOJ_d%P@rG&J2RMy(l#SL69b)mw=*3QN$n} z;ZUUaCMrdW5EQtg^e#2h#L)4Glz@OBMFOHUxj7tX61JYXbN^-kc%S)pl9~POwbuK7 zyKK4RX<^gm){_kOC1qlKSk+^(qa(V;tJEqR+bd0YVqn6re*?BF{%>=L4JvEd-wh!A zUv+^clym%8C(Dnf=80h20C$KE``4gZY^*~j<8*1<3Hy}57>9D0RKdlx@yvdHaH8`^ zFgyaCoRXj3E0n>k4UyYXJ+{h>VlA#Ks^hz2dS`Oi^&Rzlwy46BVY=fDyoqbF^vnhiTIc8*B+5hAOvN63CB%wtNNmG199SKgpl?lfwOb1kDP+knlE z?u=pJ%8dHo(LUd9f4v>xe(qJH&0p)No~*RN&wsTy)S~o-Qt)w>m_69Tk)j_Sx+3v= zD!Qqb*vVI{Vsvun*rtoNzYE51@?YQfbf6M{v}~DIJI^F6&LimjcE7Cu!*Q1HcJa%F zCBgmY>zZ#BqIt$7XsFWDLoYA;AJ>v4yyJ-X3h7+;*Q3e9_wg-()y1zl z$ITRrOt_Avg*2%&aKVL{ymFSa$LABgY9OXp1WtA~4wcTl)l`?3p7RN3WMI~}i=TV< z@&rS|(t?L#1`ZROGij9l2pr6#Y)79TE{A2K@(tzYOivqOXA(RAVYhB~93Gv<$;mam z*bv;XqWEX=jQd^IV|>MhAYB`&U}cd1-IIw_I10iUomY@VNdnHEPny7oj64flxBiRf zvIrQ0>Jk!~Fq#)%SG7K=lKh>Ha#4T*`b7n?8+nH{M2YchI$vD->M?sRshUd`8;%45 zjG(UR7v;($hX{;2yBGhXX1nxZXCOo%iUn8f9M}=^svf^ew5t6G{p7__>!J|Lm4ISr z`}P7p_9N{41lqSu$D3hdn$`uT6$A1!9+MGf)3fgJEVW~rH+H|}JHegMA^4&a?CfD7 z5MDj1)|XtcG*=y&B)6^CDzr#}TeWP?-!Ex5-nQYqp!{qAck^YHu#Rp9;~P6D#0RvU;QBM&ueYp_I2$UODCXnZ?4c^R%`JBOVm2dP zd|??!;kl30M4p56u`E8A3TGAXYViRr>Rz^Mh`FcKxU?RV-kuR7MDo-AR%RPFP!I^* z%uM<5$QRe6{MOkkR2!!xXAC(}lb&=rLz#@yl2PjHnYl4^Ziw&}T}_z&r4~^N!x&3F z5nGWrgPC*u^sM)KMBy5-k<+K{J<~9Yli_>NA!Y=F*P4Q4JxX=r^l5vBoB|Oeg=Qlk zl!ZK?HcQ5iLoKSF(~}8dCLfU&w2JxeBZaJdF&PB+7r8aDRVNf1gz@1nmBQ?hV^(=x z8d0aA8}e9eQbA6BD>83AygQNOse(fu>t_c23L)A8i`>lQx>-(&WqSLL`P4?Gm)uu1 zt;JG9ya^q{4|XMn*I+nV*(-H)M?O>jFp1hj@?@Ho1kYC=Bm6H zzqegkElcfQx7sQ@+}qN7MeT0m!oyWg8TV`^%6KJBsZWm!Ud?onkATs6b-ZrRVrdgx z&uwXvawuVv;XuzR$VgFY2ux^739lWOEmd~BH6GtXP)uFRGSigmas|j4reL3&Ztx2>BMUr2upETRN&n}D@ z#aF*a%)L^$Nx?a!VeT*>5Y!VImV%kG;jOk_tx=>uisbisx*_yZy||=u*ner?=JUS) zs8zP~EQQ_s`C>lwV*lKjIg`p7i#L;|Tq%N;g=s-(Cpv-A_MVVBZIB?{)`%t@8~l{+ zAR2Ba|DZ^tY6>^m=0mArHt&10MCZJ)PL8KU!4MN`7JRnKX~i=x0r}u=`i0!#qvuld z67)Dqq-bC{LKkToBn&X~T@4UFYV2c&&Wyk=LWSO`LXozWjhJY$qM*h!ktT(J)YE^= zh7Z4(4Smwxn6<}%I1`=~CfGJnbnW;`Av6-{cD;9R(=`5)0$1h9oA8B5gX&&Flb17+ zuWv4#xAM_h(2eNX3Xj&}mPm8d1+}u7a;u7GsoJ2+jLr9%p54%}?s#;{`?`gC&)Li< zCZ|qKJ5>!ZF$FKEu&lE9-hj(S=5!NAT=)(0HnsmR5y4uhR`N5#urwOwlI{6i{zMfNJ)4$qXg zi^Op@b<4WPAtx@b_~{OAKuqQqE*-<;wsQ8EUy65zk5+bh2EzPY(7A}tHy$3t&ff*> zgFd%tx3k=qLQe|cNwgZkhA^rR2K(9{jdm2UgbfCy^6xB!~Do zv8J-f#X5ovrjzGR(fz6BYNWk#e{@@G1op@b>Ob+U;Nxa@pV^gqEQP{_)n*-Sy& zUTFGMHhX}vRP((p(W%FQblR!1^9|)3@x!i(xanJ310D*pcYa)wRPrT8_*>Rsl~l&L z!D9iOE_(|B4Y%LrO&<~Y07-1z>7)!cIBU4;mRuDkdcJ%q4l{a{GetPto9#sHY!Xj6 zi|%0huI6p%?8Em-h|kXrusW(#`-Ix4XRoU?7*ZaqUlSw9(z|dBKe0$TKXAr{$slJB zK6Rvlj#5Zc@tsy5Ys*c;5VvBeA6Edwxn?m0rSGvNUNxT#nfmP?^+Nqeq+i?=cy$5l zf}0@(HMvu+4y}oO>%~@I>9(qmUGDNLR&a+cE4N~yjnjg|yB~DHPnN*dHJ{=t26sN0 z2kBBeHoU!zpb~q2*`()|U`km{roopghETiB3?nE8ntFLdb^UR9rrLw_6{E`rjtPXV z?*3$}h3cJw=#gz%x$g!y9(5zkWoNJ0hZlC9eq%C_V&4`6<35gt}xVqm>%h z{@V6)a(&iJpKV4~nTh^zvc7@=N7lm|)^xTd6ALC#Q55~h!5evB#-kIoBes%!AaiJp zSc`crt`saWBODSPUl7<@tfQ~j2Fe34)I zwD)*6w|G55>VsF{wVIV5?XHvKQKJhE<>(yu#m&#*?s7#D`?HkRPt>eT>pCp&R_&ZQ z!h^Wj`EE5J2C7>r4U-qur`eMC=-b$*ZQPR}?%)5}_)<`c5fcu6e>e--Cja2$Z;om~ z>K+ChKFEO_z(H)aksa#*6awSyNz#i%D<9DfLY`_36d#VlCP_gcZQ}brQT#8#*gy_2 z)|f=X601i)7x7ETF^~exTO(22cn&DQ^fe#=m=i++?C>7|NU1SEDKNN#B*j4fkpg2Z zfCQj}l0>*Hen9v)KP3yh00=N=NdT@7%vwMw(04?F zauHwufG#AU8fgC@so$PGPy@Ul?!PsI0I5KK0g2is|Idy7;x+&x4iC|j0K^lR6hVN& z=!21ZAmH$DIyrz|2?!vKssky9C$h;YC}kk!puh$M93JE)2iU`bfP-a_QT~1Gl*HLX z{5pgRT*KjE0g@I33e)-R8V*VXK+56HGC3tn4@B0!_}OO$$`7~j$mJdeWb&U4J)rt< zw}f1+WkjYX^-h3*!*z0UK)eb0cksKaIgoX@+Dgv4Z}xi@srCwF9WL3Cvob7x&mtA@ nfULuHA9B_cD{|J~J%OJ;F*R|@`ER57A0RmKDV1UW_tk#^arT~z diff --git a/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_FPU_register_file.xlsx b/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_FPU_register_file.xlsx index a4203141009209c0c7b485629646fcc7dff37958..766c02b2e1dee27e13e7477b09fc6f0ba900c01b 100644 GIT binary patch literal 13978 zcmbVz1yEkg(k;O-DSxVt;S-66P3AQ0T$-Q6{~ySwus=hltfbIxD&nks64 zMa^ROnwg&N>GesA1B0LdKtMnMkfCcR0{mjoFVC7b`ewGYG_Sv#COM@#=n%kGnpz0Y zmTE=Q@nbTf`S$#!Bb7qkZl!g;>T41_xD-Ok1PAXTe5!Q2Uebl9na;qCVzz4Lmn)}I zF9it^m`cpn8<`KdrB+p}Sc3%PP4BEpxfI=@Z`PxZY+7F!K&w0B; z!6Cj{(S^YQ0suII002n;BaN6ZG&-8m{>7w&rH!eMrKKs2qq*4+R*NDfOgrdc{Er_| zg|53q!F5AennHL>9&Z4noHvVH?lFb#1$OeofaQM! z@oVd{hiLM8JUU#(P#F5Qv|>aOUW$iQ(1<+ii7ra3QgP0rOrz5t!LFX!CnlLU(^v0v zC__7NCOYv2a0pedNENu!f>OG{w*9$OcLo+tGsER8T`w%;kPU7m$F+~dImh(a|PtBUVMm*eIk?Sb@k>6>cYAB$H z{Z>gjMrpxFWX98T*e{PZ;ver$iP`NJs91FwVSw49U2&t}oiJOLCy^BN3P(+l)YajL z@MCw?a&3?}7f5{^5S0Qbg!51(zEOYQdAx`(tAd-A|1SEGb!MTnY=|O%Ok>X<1 zE@NF-uDhDvx2`Bqje32|>PA&9LmE-9Ufu#py(KhFeoa`s;z{d*CMm2aA&fl&YhJ5+ z7P~7-S%yh{G+g0Lz9?($6b73Cci5sGwo48=HZtD~CRF)jhQuoNeG0WJaWcjji0xf; z2${fF5Z7rkpT;dC^Dk);bd2rR5HL0kq!tU0)sW)G*~*woNDGk#cDP}5{8;{0l#>ot zm{%gak`C=EXk-K1FgYc2k+1`I&KJ9fR&ekSFb=tMt#QQX;7ZcuR5idz1Rai?r=@9g zY$V7EyTPpoP0&|h+FtL&K1#9{`V|16YNbNcQpbR=qtxxyd+v{|C;I8IkQJBkpsXOT zO7q?JIRN2oqI0Bu7-@f4wQqiibG^NbXYQ+{5a`PvS*7A#Y)#fI@o#b9#>@2m$g&Ta z9wQtQk<+(Z9)t3>Nm=l_Ln{)etSB0u>+G8Zg8nF;}Ia3;heBH5?-Ix_tzyJWAFH!%WV;R<8J66v|+u?Py z(%PGw3H03JQ{$0ihX9!l(eGDIWKRwPj&t++W&rmY_*ji%LdT@FeKX+`+*j2P63kD z;|gP)oneD)V>K|HYAKSz)6~eVLAQCm3C6OCI6rS^KxyR?39ZW;3GmIvl%?{RU>#L3 zRTDYj*1e}v$ga~4g$V;E>!r+!S-1@wDa)+L8C3t>Np@Mb3@@8AVoDj5GW!ylG5;RK zdsNs{GQepuM4bTCPexrKpEH`_iIKeYnzW*e##KDQ6vryiXq9CdE=M!_<=QHc+god= z>Bv6Y>;+fT6IIRmDDrygyKeGY`ZUrn6vYlznE~G`p=@t{!n@M)OpV<}eDe{RO(9Nk zw9lZj)zJA4 zb*~Nya0U|$BMZF6i|`H5OAib#Eu6-;B8=TmcACrS3lNh1j^`V_ljhSccw{msv$sUD zzu#BWw?eA|YEeIuL1eoR`RU-aw?Dx9(}+iQ2yORZqS)hu5ew^BQjRHAtHklO>&`^< zByTa61lhOi4?j#%9+q?uIJ&dEC)e*O+!zOXr?NW{f55&Wf@4jdsA%PDg&T4o!;Q}* z`!<%qaNiNds=Q^rXcxh<3XxWYAiiP2h+Nly%dtpEKxX4P_+XBg^JMU9_&i$LkE<(0 z!OqE+t8P7-tn?eGq;Q4xaRX>s37tWO6)ruzll?Lrg+a7uacsMiogg+;j%2FWUKQHA zjh5Zs!@_6hepn{Ij0kPM3G+$0L1h1RKL`~S9Nl3{VfKxob#3eW| z5gKqWNo5!_Bn$Z%;e>%{*QUU5g>*;r)=S7Gsg;Xv?MjWu@~e+V+dWWY-iaQiFQ^;U zY$uqHu=ZB1Z^)@!+fP1dAQx!<2wioZDUUB{*lYOu=g>v;bLH3?>Fe9s{wE{*@qzwl zJ{B8Hj4>g$1CB0IPtVJPmoZO=_Ay)q%mgQCqjK65 zV`7JWE0e7cPB~Sda*G>7dN@IE2I8c_ADDFk`>DO!oSm$&h|QGgbO1WL&|QguKI@nc zD(!;WCdsk2xu^FTLw8*FaFgU68}xW%rPSAn-9%%VQsvc6oL54Gs$#QRU);@kA?2S5 zdGkMn{G_5vNy2uG1)=G<#OjvoX^Rr{0|`PD%%Fiu^!L2EI6W-Y zD+3$+cmWH}Ytu_p$eM0V&FEPctvKW)$qzF&AAoZRLPhFR61cyjYx-wL+QtZxWs|2S zkbX(l%<%{bk7?Rq52*u$8+X+?Vi_qmV~2NO;jI&7{L((?Uk+mJsHe(4@>rYBEPVb35FDPXI)a> zLmlscCLf=WZT+f(NHk&P6@~CsZrL#LgNPQS4(W*h9zYCNv@Z#J{ojT?1|RU%P*Vk_LVA3oz6GBpPX@aRvGKD9-ZjkosNgCiE7 z_$$(|s&KEq3BVSG;X@-bC*@Fn$ zz!b1yB(9b~^fAUS#Vrli$C&&&RUq_K5~GXpWeO>5e_b}guMi!fz88371wH6SvQz&u zz(*sNV00b#vsp)sWm}v(Fpijbq*K0ZV>>uDum+f1jh92!`vzVv9DX+2TSemcLdrCm zlwbVszf5EXiUm~=$@or4s`MqMDFz}vMSpx6xfKlr&d9J?uZv?w`d&wsr6}!;6LZuG z)i@w`2b!fREtYimlwlM8Vq;!~`%S^nw#%ODs)`QfE@c_8Z&?MuP<2%O z^JH%{h{kZ6a{`<0Jw6Z>0<*dAyujcbL`hIW4Wc`;bpb*XCZQ1_nmJz6+qL4*9cIL9 zsId|PFo{lnEP6A-<|@RDw>sa2YE@(vaUyIL%ya$n@f#hW+K-hbkH=A0`$oYoN10eH z+3=H689_0o36j#z;R3UFio8Si5G2M01JETV8sGxo?z!~@Gs)wL1*)TYTPW@M%MXo? zPR85URLy+06*9Yg>V={yDlF-8$iOmir<6-osCz-N$6dIip5iF-Ml+|So?^qVH+edi zr<6UM^cgd`OiuOBvQWBxCek}uGKTHB>>`1&gZ$J%Wwf7R*$5ZdeCl28d)IC1Vk|lf zI7R~FPMhu>xIAG?hdIH_2`j!>3S|d*I2Uf&Ez*z2=me~NkhV#(d$mAlIdWKL;q|_0 zt~w@?ImrfP#0rYj?NE2k6N6OSrCp)v$)U3vBvALe0Q+>BQNd^Wixe9W(#Is5+|)B; zQWx9PN!!KreYVu)YYtLRhxajON8}ClnzM$Zvjz#Ak<5k7VDiw^SUOI}()QoFbf?^t z{H;!ViCqN3chBK+!b`=-^o6t{&u9#F3}USPAu0#=-}uqa7+;tQJAR7Q7J!*5hUGI# zGh{-H=d0U!m=KcP#_;ly^Hnf7H-j`5@?|SlO6l+Cd)pe=YXFQPb?aUF@IgKiFJtG* zYAJPsK9um&CLpLRR)@6H$1M{z(&RARM#0s*+D{C#sDN4D`H5T15BI9g@9ZJ4ihfX?Zr2{FYd z0moXO$<2$FW=F2PCD?hxud_A>q`BPO9z|EMHUVx@2y`mV;sgoU%O}^gwLliGUrR5O zXj<{THm!|55h3d$xgNj6_Ox+k0KuE+;Jl}6D@^C|%{|N=$A-n8H4gENX}ul{ffVuI zT}(8j8>Hb{U>*b=DTG#H#jiVOgQICVHi#hgbrh&>F0Btrbxnqn%rLVIwO{VnU#iNd zUH)j9Q!?!5B+KHD@v(J(j&W?-v2POiJ?qfIXRe83S4$K#o7e=heCUXSWJ7C5`fw6J ziL@K*)+li5O}I1eun$gDC(4-Hhj!n(eq=NQB*S09UUFftf6ZuM|5`(~c1~vcKkiKq zRmNn$(4n{;E9#wTczsf@0%n z+E;gNb@dkOeZ6o&h&Lq_RC^+L3Jw;~ARjJboa2crt}BOUT122=pp8GL(i#x%E#3lO z9Lm?MH{xl8rR_d>F}I`x6zwR6xwEUR2Kl60g#5Da1a(mBTFEGw$TOxps|^+WA$*z# z;*=x$fP7v1GNZ=$TGg5bp}t5E(5*^3W@fr}!9WY7Z#F34v^wYxPg@&|0yL{Gcv1?; zBM8I8vu*+f>aDinmlkltGR9~#9)QS{BMA7=_d`&_a^&@rBl$U-A(!-9*qG_fK{!zb zj?KXu!G|={;mA^z9l3zcq^9PDsjA!YB8bguvNmGI}%P#k-I7Lh2h5XFKJ03rE8;GF70Csf&5>eqZ?I_=pkZcQbx#T)fe zlVpS%M?fq!FWEmsF1hzGR18l?Y~%vFDR4&0vLLPC=IV=%JimlnQB(7~$UU%rTNN-h z@H~?afUgAvoI43ozWR>3D|stO0p%(>6tfO8j0l-(5m=}y9-g9{S(m}YqPYa;jR+!* zQQWlxZ-d9}sHM3SwM+@MWnz^sQSF_OKT;LS^f z5gl5k{9IN)?@*C=e6XIfXnuWKa8rFzoJMNmVVZo0UVfO$oG#putpOlB@KmJ#cEn>p z;mL0`^873dCz)%wEP%FC6$6a|;B&D)EQ88bD<&4KOBg2B-5j^`6&DBA4f9vwBZ4)`xn%EUw{y`!~#a{g7FrwNqN4=mI*YL%PgWER=_G;=lU$OQN1N9OttIGaK zr^6cIr7pC950xHOnabfz4bhb-KozBCtoNM57gAp|ihXb`pJ|rJ(eBPo$OAZoS=H2& z^Dy^4xK2EPUjuR$l%*xo%SLL$|F?jQ__CSwEOn)AEUj#5buDf5Un>GP*#Qe5I)uh+ z%827mu$TZUzR3U^lT5L6lgVV=_np*l2Hq3g-eV#e%?ULf4u=@xEje0KK_3Im1&R&J z&=K|m_Z58Tbq&*)$l~TtE&E_lm`gl31_`4=>_D#=qll?tm&KzB*ljB`E?vB3WLfm> z4OVkNRAQu@i0~1GI>Wwfif-2p=>TAW?*}W$IQ>C}1DXd=^90i z(&z2Z51u!OqQHDTa+n`Vw)SD``!V6Zadr~#1j8B6SLM~=xX+7t4b6mN!f$E1xv; zDng-&z>on@G040NtZjbA6Y2|l&i9MQijyg8>~Fx5k{IgIOp+qLm>+U3s^5McnlB`d zJePH_p~Ez_;S*L^3-b8Ty|#f`Plixg&^PSTkU7}~C%n5RJ)J(DY#hVoI}w-Etms(+ zc12_&RY9zc5{~;RU~zECb3;rG_rW7Q#p~SlsDSl*D{^Do7~FWq%Ei(9?tyd}A}F-+ z8qXFbcCrXAHGx8T_SJhqZ<;kK$+b17qKl{6Tbl3wsAK#cZwpU+R*Xp~wVV=lmS~9w z^x%zC<;~+qC_TT$08mq&ISuS)Oe$aR-$6tUuM^K^t{PMY~hbbLy$)0%ffvtp;F@l;zjrlQcQN* zWUhsFYFeKCpd5#Keq_YHnyn8w$+yf$ffdfsGg3O#0(@%w#;FEUC!}yae-pe&AZ(<4 zP2M`56O$8a9ZWltlq`9@$yQe^(EN(ehW*@llQHFe6gys0>P|5hW}BUD3?C~JAeD%1 zrR0FtL-(qb23uVVq3WXA!NI^0hqFecTiZx(w1tuFL$^`a8&FJvPqLr{zWNb^(fR=N zJRgOo-YU-=zX^?BgCOe4T5cTgzr{e`slJ@-%L+K1Vv}oyvTq6O z*ksGrR#uFWCF=-TaAvTny31L9*t^D`^WuhNy!A07IqnL(z6#j3JnuV9>;iwKSl7JK zp74cU#D86{uO;_i%qp3i(Hh(7oBxP641e*=YubVT#{c*pwXI=FPes>Q#b|=ZQrE1s z;N4gAG!todFx_W2|D*D-RD0Lh>(g7V_%?L-GHPm8vI_bb zGaS^c7w1-C_)+gFBJ#eP_p6$H(JVvo{E>`K^(v6Kiny9Zy$R{I2Zped_c529wsJIviX7OnPgPTr$$Pb|^ zMlNxIDr~|1U=Qn+>|+69VA2<|k^YtJ*Y*56**~&u^Wic$Z#snT)5RS8#dJ(`U9p$U zgk=?2i!~GSFmfsA>{$|(mYEnCq)|GI z4?StaEMdC5G5M8&`ZuTAKtmU3iG+A^5|3QTqRq?b@LXt)87DxJXWSXfS4UBzSZ{M* z+yMSRH}3C_GQKXTLsfN~^=?G>5pwBXMqfN2{9J~^C=v4SXC@89)7xa9@_XZiqT9}NI36a#Ul>DBQO_<5yVNW7}d6$@`CeO3; zbvr-5Gxupx=?W)!S52MaOV>%}2D}`jMG&Ln>?28TR>| z!759bwRv?J_taM9d`Vo)I+NPxhfBi8vqTEzZxOPApWokdf^CY8iIa-9Ewok}@M^L6 zN=9%-x2Q2OQbTcXb*AL6l);k5H|~-;O3z>4-rlY`*|d!d8%xMN-!IO$=a@)ve6e>+ zou_yYS+hlP6=aApIc_k^pA-r!mz<6(Vm!i-|(Oy_FQ z#2NnUU~#*3{`)t$UHL%4Xr~ZR8y+!BQ0wo+{i4jWu=QZwXk8=BDOf^tVcM{{6|v^x zj@#(=11q}D_(fUwi9!q=Uo}=Gmq?4JPiWt)=W~CgFL5^`sd~GFg$f9gr z(LTdnr}D#p#|CwwV~L2qy;8!^)|^9&r<4HU4&_tPYI6yG;fQqgxE3I%<&h345m_h) zul+%4)#@CiZq^*|+EPCJ`RgC;rl}v%#Cf8wITinX#4Q%yCU!OdzgfJiSGRU@O z^TF(`PB?GK)DMMPxd8A+6+A#C#ou;NRH-A=;CF~5oLleS3tm_}?Z7Tg^$6*}32uBk zaX7>z-XiL^s`;`5G?|y&g9)#T_7+f;s4Pk?=MFpu3gR4;X(6UBZTBKb`!Tn2i&}i0 z1Xdc2*YqYPoy@nI=PLgCylPqVeuP=bLw8m#VoW~)q2B8X+?+aua6`Cq3|F*w2GQBc zA)$+c*!L~$n@RDcw`6SI;^c(K(K}fJ3fkEHxt5iQF*XUXWrfDU;k9P6^ewJEAd6ey z;c{ci14764=&E=P)?voA8QaNl4ivQ$?Dq?)burgJOz1PUzgIs|)c)e$k0d_QT zU-gNGT&L1WJX*L+HdQ(X&})-L)rIM#1etsDq@pU~(*hstV0v0^-*EX5@M7RhV1SOw z{2nW7@%E5VCIqxtj9Op^rsBhMpw}pdXpKR6k9-uaB$1dX{9Qp{%2jLAyKu%~4s{`- z!U@plnGi;;+U2?27AfdTZOG4>SNU8goaZ3pTL)#5rmN&rjPe ze4^9E@_@mP>kw~%5xY-f@_RpO~nAg(d!sB zM~AG9GEPing{TMaA;_O}5+u;j#E9+FyAZSGl*H-)^CDFY&)o`WK|ZByF`#h&zcY1hYw41`h+UM+HAPaYLcMis0FROcQ> z72i2w=cY}s9aDP+N7v&=pq!(&i&N}&beF$EEC$PRDWe!(#$I6Ev^qrdmk$pVIM81>u8fZangZd38$ShGT1>Vi(haL8i?q-iS%v>M0(@ zeTF-uJn{w;vD+h1gqCqB=+fDrkfU&2mf3i3l0%fCK%mLRTz3&*X`98}uh-(DQ-A0I z3!WZevs&N8`IbGdhG8D zE13ETK=!lx)tG5NxQSB=n=C>1E>Fh5++9Y(sdZHhKL9$U=ct~Y=zUAuGjR{V7sn)a z?>y3P49IO~1IEfd$>4S;$}h&=X~v5AOGPDpvEr|%l8f@I%_C@p8oT&5uf z=WxDJ9C4gK^Omvn73$qL#ULNtmCgF&E%7;o)=MQokc4AQCd+ZacwP36$1{?UC&Vt- zI-zQiyFp25DUj$!(RuZ2i*x0^f5}SqM@Bj*Ho9)Ic|Q7$v#B9ciab$W8RwVstkN0S z_+^Qa5VQcikso!&@e@3h^@JRBF?B@eyH-qlNA?}l89)SLVUI)_;I>E_gi*Qc;G1IQ zx4IfTGTQp&BwX&*Xl9L&jm7mlwVdP0+}aIi=h!;%cja=jI<0;lx-@f~yiQpeLG+|l zq;55Py?2IENPfolk7t167)Yg#Q@D)|Ia|Y!tHarKhMyMznXYwQfV|KZDHvsR{4iNI1fU8-Sf<^L!;Wy zEw*D3sQtS2jLH)H9oDc`+0K*%rI*U6?CF*aEKb(F0g)UJtqtpH>NDcUll@)DosBH-@NX zc%}o`IQq3JDamJFIIaly(7;@D4&{Ya@|2RPnRHG5AjC1XzA@p#8KTsO(d%cr=12I~ z%xG8>%;!4<06-W0zZLbkzomeGDX?C%?jQNl5BXJS_%H1~i2{5=2^Yk4=13?F{(5tt zA^1Lpi$mB{D#w%B3dUtR{YNHb7p=fKWkA6=VEzKNoJ0JTxzuTw+yZ&0Hc{E~PMP~& z*=`{~qDXEl+^ImJ?m?%@-H8S*;w(m(1@TYuz-JPv$Bs7!JXKod*~kb<#Q@XI98Vqg zZY8L=DM_#@cQS2L*nNq~iNkGKLeu?p_>iN%TSVp+ogk@Kr(Lakuzw}Lqua$Vexd(s zPWVrr|0p&7*Ym|{a75#|&k#*PA5SpH&9PoOow8#!%#P(NZR^9st{oqT!0NvFJedu6^EV7dwWv7@>pjTom$jVbXa185WJ+Y~eB*CvV3LS*;M zUS7d*yu3jqWV*wSsn)w6p07@-^8NpN{fvO@Gk)LSlppJC|yDb?W{>yxKA~ zzwHSTvb}Z3hTr;p_25L*CX(Xwxcb~;|DZq-XtDzU!9EbT34qE5sl8dyk7 z9VAp0-nca3buU(wNQ_nV-nwPW5wvv@-S?ldTm0yx5gc5Sw1uvWd$9oi0HS_#?zj@F z!Hr~4c}7zUhrBr`GtqzF=EqF2*m2gkVp5g z2j_Xdk-gs+hXO_>=AQ|Vlym1Q<>UB-OyxyYa$_b`ri0^>`Si08zUA*5rfjSAJ9V>D z5c;F>4dopG7!govKqR6894_Zf;2Q1=snq!y_tU*U)$`LNHl45IT{}YHD-9pd0A21x zJT3NkcN_HSP39e@JXaDY`~~VF%UQtKHFA+W%pLh=t7H3jRcypYNK(#Jny9dXwW5Q> z`46yq@Cs3!4-9dC?FEh@yx{bgDK`68ozVXl|9@SwL@%1m^C0*g-=pwdkBgPNhZbtd zssKsQcc$-dI@(XGMA&y7_1iBs%c}IG6El%GG{9`Tc6>>^+naP)@(PJnDSBWDaScZ? zp_y{uT()ch$?}+T%@5ery5Q*+Engy*v1cuOn6A_AOX!MoF4d+TGb-?dmbv}_O%SPs zB*?no2M7*+u(tMG#;Sa4X2*fsu}(N?z&)UIWp#ge)W;st&n7KmIOTbqAx?4uP@M7z zRSmd~l4x4=Wh~_~Imr~;MfL~{<-pke-K9FT{|)@^oC`bb7PIxHAw5rACn1?tk56SQ z6#y?vrgXP4po~~2X^*lkqfGK$MI}FY_;PxV0WezndGlUmZSnU3*(RaM3>)Ugpo%1Q z_wDv8Yy9cSgS7{?^&GIQ#!w9Sx%wK6UEw$IRuOuQm$k{VuF;Xg$GW90LW`3)!G!46 zaRjF^whLJ@@|~YQ27=O{1+fIs3rfF5B;oZV0U;N%mge>2Z5F5R`}~cpzywNHJlg~A zWc{AO;kg8kl3*NalFm8w>p5q-w}SjCU}^i; z9@y(VtMXe~*u8X7H9tC8>D#Km-hFh%4M@Id)djCz1!Ji57ttUICgVW;NIn7)+xN~+ zbThg4+T%TNu4i(fCh_qpR|Rb^+4dwVVSFi)Po-*eGQOZYjI>Dd+!7Mu#L9N4iBE~X zFtekpb*o-ME}U{tFd&$f6XP7=p_d8)4W*P@M}cN$pGFNg&ZTo zf$gT#|I9&*ZrZ4BBa`}eTVGuOR?fhjh84Q@!#YLLBx~;@+N$hl+FiC}J&;(z(2>l` zfMw*uR5w5oRQAu;1*lSJ`6OLHCdJkbDJT&i5}*}7Xal+hrbv(5aLZ?YYW6A$N#@36 zBvoo8EgeY!wnoO5j3=GPa|Rv%kQ3!Y=bA3f*Z8T`cLV^){-m$rZGe>->cEcd=K7gO zI2Bg6)AbzRQ|)fi`|uV4`aDy%@P}`+mf2~wJBQX_T*QusHMOXgPw!Z3Wn>QLw_5I| zo1j)%1E!a~+U>9~{E!U`d#-REzC7KvX4LDBL8wKrBaPKtHz0&71Fq$mHJ`NQcHfK} z2sUtNJ$@#2wFI~9qI=JMg9)n} znQjsB#KOOLuY`#MV|04U?)>8j6#1-{PM5S>GI2~{3@ONbMUXiF`}O%U!I1c{yX^J)N_9V{wjueJ$ZlH z^2|{~Z2n-{trB{`Nw~pN*?ONB`PVcnxzu?HJ>i(LXyie**k^ zP5wLivM)>Q_Z#D%eTY9%e!YYK{WV&!|3vwbYW@lEYpM1-KrYUo06)^OKLL&fepWoM zb`2V*Oe}{EpQ~`uA8rE2clOe$C2%$Eqg#d#s-|$e&ohCa=HGRVn$e zSpV%A{VmnM=0?AxOi}zT%HQ(+>&g53gf&wAiSmP;Kb`qCR{su=N%ObIwX`_sOOyiu QKzsQad(lo+(7k^8f8_|ne*gdg literal 21281 zcmeIaWmsL=(k_YxcXxsl+}+(B0>Rzg-Q8V+Yj7uMaCdhNE`i|AU7gg>0H4zc0wOsJgCw!%wVqbPleTUZNjr}y&!JKG*}NONdYWaJ z*8Jx3y5wmXIHpf0he1bT1hVv(`Rl(##VEt9|&YF=dk;lOb$jLV0W&DUKxTlh} z??Rjj&NR_$7wy(I12cNSW6$H@EU#5KDT|D1-J<@LH#HcwJelp|L}!&4)c&AfBG^;X zHT4|#Ql>OT=qI}FktjV8W!w?-{CmP&EDZ>L+H$#;Al#nc`*`FGCF1b+&~;v)KNm<$ z6?S~NfFP0??^+VX9;+9rG;+zrE?E@Y}^#%n3dVK{2lK+QMK+*nY1OhM$8vvb$ z0T=}xdm~E+I@&*;|7#5XFSY=GyY=#T87WW(fHClYB^+(%TA?JGwxkm|kTHA)W=MP1 zWlM`KXnDRB6>!XL#COlAa>;T_yEd-Pcg;uia7IoRf%4BVo@rI>mU?b#fji=$9vay-^R)&Q)M>dZZlL!Och%sJRYll7rP{QbjgyZnp;THRqZ`| z7&`n&WB`g!{^>dU;LKu5QBjmMC>=C&@BW1SU42`Dhy#kxYMQ9$K7AV_La~}P-B8{w zLk*9?_{Rx0OIpdWS@i+_VYUos!A_m(>Kly!#CEvmM2*7 zCdT8bmo}{}j9Fc79!S?K_}ZAxKtRDoJsa8Yc0VG`e~u8rxFWN z%XJ}&bbXL|cWN>J1xdIzoFZou5prlJ@W~tT2c;*>B}^ajt{)EYvO*V@Ls`w0 zTX9LS-v%k!_21d(Vm>osgPXy93L|vW5x$IB#l75a+eB+6D71)ee3muWDj8;`oGuX= zM;j^L154H);k6w6CgZN{HwWbzDD${Yv5#Z6Q~utoF!}usD7T|1qHuH-j{s(!B*PM7 z-(H?VPLG#nM`<&#hc>i)likS6QM2KsS`J+(ny8?`#o`*G3U+&W(H^&Up>W(>a9M+4 z#eu4_FD&&P<4^>emowg8u5%L1a>aXvwx$yCnTj8-YcVu+*gFkm@yW3?rS3zjXO1$w zY*Rk+tht<8tUDHwW^FGVE{N%o2uJM-)4sgzcq~9H?G^d0IXQksGY$qJ1pTMI> zZfEV=Fl$e}7#!XgZ|Oefg3gC*^O&sskWqFwJHdBNh&Y{f6e17&q8)tmEyHp$S9S7T_L%s);?qks?BaXIQs1gi}2N>->VeNn&?wT;j+K@sKg+ zqf(_F*oz%d9_G(EgLRYL*SY+020>ZJY7TTx=r4wGw8%Ob;vIb3uisJeT1a@?Qkh5M z#Tya>dAp8JlF^_J`4tTKJ8yZGdJ#}|Kt$+z(ss8X)g_Q!le3L0`MM50w@hpdo$mTD zCaNd#e;5n9XcTLBs13M}-n0&k>8~y>9130beJvS(eEH$y&=zn&<(%i>?34HX>GAsF zL3pFA&;B_!^N71uc6w=j<7MDvQRw=L-E^FH_G#PZx0+0AjOfk{aDH20KtR|)kiY;< z{?q^cU7!D#F9Zfmi~;BV-~DJyl(FcchYdapcn;Zo%qv)1W=Owb1aG&-J2A)I4d{2S zp0#?uMLC_XpDaw7j1WNfzJC8WXZh3W^8pIz+`18E6bf1{6K|DPTFLF)$Xb4QXv2up zcRXYBhywJ>mCs95tm(VRDo#>yU)YD0`&M~@V@oE@!@VM8DT5GH>jHBFRX;b-B8f^c z`q`G}?vbZYF-|C}?M?eMSQTCxS?QoQbeY(&qT^+o0UHaQoQ7BlD~BL+DA}zV$2 zSBpi1k zOSGusu1B`uou!=~;$v!Q(AM8Ku7zL8x*e zqqeyKqDxXq2$d=n_|<*nwxuxhLc2{fj(B$Y;ZQAOL5`LickK=(gR*3Ixk(wis?k|v zcM#`UsW`_A8cp~V{t?*sR(>@cV>P49K92a{&P+*CMD^XtAe2}jC;7W3xIu*5eB5WyuOs3pM-inu~Zm$8ShGbyu2)sRyN9>^xz86%rBeBC_x!nF`hSZ1P1 zZ;olIyVEB5A?w43MH3HZ=%)Ri+`0iX(%tbQzAixmN5>>%CrFm3Af8%~WIAH@xDHCA zCNTB0yp?uq9_ljCI}r}5yrq0a?bhw9DvpcQwm6b?l~epA-#O{Yp3oyEq&U zT%)%+8|BZAx4jO#*cA@^b2wCq?}UhdGaBx|G{|@Heco(e+y>1KFEDf^BqEL=yW=aH z-x*VUF!0aiNeiYQcXFSlL#<#$Gb@@Bploi3*?Lu(exz`iGZHrPL{y?}#MLK!M2N%)ioifhd+9Zz6q0B)@@~j4T)RPA8{dMMIOJKb4Hu5LrLw-1ZM$y^XmLX}? zp*2cB5@%W@$?br!B&T6bWRDaz@jP3ocgcygwI>mGsLI*N!S&IJLWtia$GAl@=7K=# z8bKkOlIR6Pu9v8)sqpwaqau-*%qAE&&BjMp1(|m`9OBS~2YS1CA&i|~O_w_mZ2Sbx zpol`ScKC1Nm3g96`e@mzg|e?LL^u(2MA zwAJ2Up=Uhnfgx~~hIx&zK`l=~Bj76MK>bn^IYjAcR_i968Y$TAZ&e#CA_IYlSsIBX z^7RZtvxjnbG&22!$dnN!pUfcQ9dsdS_0Y>D+RtBBrmukfkqww5 zsaR<>?fj93Cqo?-ONC|WQgv6a+f$zQrXX6};Z_kQ6%62K#()Jl>W{6EJDg)|QJCDy zXXC3RFoqGaku(T7_D8HGZXyxANNC)MLd3uniq_j|uHf^(l$Z#an(z(bwh-0!P|F}` z7xd3{Orb2mUn|v&$Y_)*%NFoI7>;1PCZT{FWvt(rYvlMB3A=k{=oY`5>3BM zo1>|bl@Z;q=U-OsL|r2ShYi)6?urlg^2Z(P_Yq|ByL7ACRw#9H(wI*gHxy-9SQ6_| zP=4{;*M;)pQaaFH7P*Pw*ro?k1P@9eP*xAb?gdyL1q~U;MFmC+)vh~dxOkZkSBIlh z_Yp4oM|gU)kW!z#?=^>RZ5j0q;-xiSqPB7-&v^(H7)29Fn|A4{&*`-9?(#29r9|2L z@dwHEVH%#qhnG}qC`9QadpTHppq^OuxJ8li@9Ww34lu9!>(xFanfGDF_1+?*1}y7c z4It#492p9VE_PJUt{2mb5CvglDtxPQ{4U+w8I3RkO^BW+)$9^zIua7rf8rW?Cccp` zE`FE0n{t({(`NfEw2_gJl5G&%9`re7$Oz9D-^BxB%wtGSxFS|1M{x&e_64 zLlQ3>e?C$WsPfhb-*jW0lVGo49z^oWUs$o9|l0koxNs^ zRj8=juTZ3=+tYn}y*RVsyL@@rZN)(7kSyj6!ytRPm&@jRJ-tmS2|?ShbiKLG-;W{S zdEATO^YJ{GT;DtB3`CHK4Eh=p(|$}H{EqWv0ODzkBp8V(87!RttB{k9D7vkU-xrvL zu0|LedtEGy^XaEXqhs&h{djicZ^(VWIs3s#VVUy zDQZAgvnPDD!=#MZx|7ouC?rYJx51?3p8Me$oXdZp6DI4p423dvkxjRXw80a}roayQ zC5bmrvW5}T!ld{invbxxvbDqKSE}5e$3+EN`F-iRBP>eBq04O+u94bB?3;DGgO86J z8GL?6kk<4q7V+>y(dcnZ4I*t?8ScCV*fTVJB-cr+BhrdE?NF}NKD_>@@Xewgo8Zq; zGbRZll*cgkKva=+7Ba1KE#ou9Ygjw}p?=#9l11p-van6?*fKN4toKJL94@^V$i_F` znv+o7w8>_di~0+!dU#9SZe z9Q@ziIBM0&#&HR&eQ1p-whZ8DjX>$G>RN>@g_VWNc;v2*$ zR;q-a)FW~6Ntm}lsvW1jre3{o*;IYfHi_x_*7jWVh-`R{GXhl8(P$GK`UzzRib+^r zx9I>~xcq#d=ty%;-=TQ5cfH;XGl#zRC^MC$irQN?k!Pzz>81%LRf)oNHGHFRc1ifd z3ORI!Ow+5b`i#)!4t8*YVP@TUX?k60|Lev_md`gA>NF0jBN=mym0zoF6-RbiE{Xeri_T8@b~ql~$I1=gacd4^PAY|*JVVod0XJS%JIT*OBL}6M8Ri9S90}=IK%_T}pcmq7NfkIL#i}Vq z%ND}RjNRgFE0Dx+#I8u=wKJB@*~aCc-Nb1w6RDD03EA@3T?uMbN$mY`O!XPx$+Ue> z)+r0NtzZISlr}F;251^bi*=>0vo6utY=&YZjAO zy_mcBxWtb#M!4K){|<61fTa?u{vsC(Lf~saBsmIqyzycb((d6E5+?61^nTT+r_(OU z_%XuO$EmwTt{ew%Jc00_>stHGRLCZFisE%#lqM(*B=syGa`>W1=dm)1Orb;eygEoD z@^Fd051I)F!?@4&7k)nzE3j}|esl+vaO!T{&w5=eRB)Tb8haamD$kRZVN3hgA+%mi z$tO%xrg$`eHcPbMvKN2+ULmu%mr8bRfgKTc=3Q6(_38E9@|ag!TOkLVzFpiQ)qNhT=EiCY)%=*3JKP!E+*sQg()-NThT$A_D`)c{ z;|3lIuy)z}$&-1`Angi`GdTCP>M7jS%XVTo_~kik`C~Td2K%oXkmjUD-udcZAd)1x zzI?@b&het7GSJ=q;AQv?=+?ZI_UZSI*o`320&v6^9ta2!X8aLjI5@gl8aezCSd4zu zvRPq8^&+T#loRWH0Ge4ne}Na?cZv(X-JNoBe`DzQL< zz~Cm5<>C5+)Ge*eEQ!Qrm9_gIF&G1wR1>2J)jeUF&&I(BFlthVJAjonafAmhI zC^wVdr3G4GQz3^+;zRo%hu3S;vZI)Zmtt*x^ zHX~XiQz!)Xbj1s9+k8>1U3{%cOw@*YB}9QcebWVA;G==m;@1#U16>cLWN~c{#M$sM zbf3(Ut=DCCh~`YvLS3Bvv|fHZV^}yf*{;I2uJ-4emXI}7;WOpR)mFwrTS?te1R1r# z$&;TC@Y^v{?k5Zm3Qp-mNn^<*FWfsjoRDGgU(U0%Y0;SJdUCB5VHo<}KIqz4F z)Ga42#CSDSH!d3Ug9KkX#=rK5(;>=h(vl(I(R2XWxpq|e;D>b`mKEBmdJ-+tAlSqi zP~HytnK18d5tlGV&$9)&Kf@A8Sxjyvjoc8y>L@naWWZIO)w|n?@;yAgSeW3x>bj9G zGs%TI=+Cb$*b2oA`+A6U{^TTAD=)l4p#DKRo7NL0J_cu=|ySV0>`BPJWx_Q-Z_`20D?+P3IR*Ipj) z?R=v1o@$@0_xG+_f!m4)LgnyC*cyc5lh5NsPeLS5Gcyd27{81B_pT&F=mA=30LUMs z{zofK_3Vudl^pHOtWAC?XSu4D+zLOUr`WKM+I`w)Y`scQd=BL-8gfYMxHfPj@5j^lDSbXUTimC%IO;A!_n3j*kB!= z_f*Q%_7%2!JVb8Amt9?ngCHF$%$JN7BPbii6g`5IakL6QW%6VQseM>V;6jTB09OI)x*k*r?6D4h!0OxHQ=dw`=7DoV?*3&IMGL?s87be}cYp_JsIw}1{ z94Xn93D0FiOWX-YwTHFb<5fwc;K!CARc$awk89JO-9g@fKq1jUlx{DLul1lJ@=x8g zYw%4f=58!SL&JOInTVmg$KokK@C!#BRQfRbu8c~}fHF)yfPat2`-T=uStZc)0geq* zPS=*6{VsVQQBo=g1@URA{vIk&fQ(7T;RN|~$4#&>RIRa`58N|m{fV)scp;XaGZw6= z=8JyhmcTM>APCYxEvbVBv|yLR_lJa^viF9}(qsegQEaUoD2E)7hb8qGcnuZy#lgzT zBId@NY+o*8V8ZGp4Ts&Ma@l~b@B{6B1Sl>>!ehba+e7096SV|s7BiN9E{fEM@v{O? z_J|+W9}aB2BU!LSNfEkas3w%L!ZD7p!84H5u+AIJ1f}Oa>Q-YiL(KEySGFq>Kk_Yu&33*16k;VgErthN4jiJ#YL*EF zu6`^EOh9)W-XbyFXmWQviB-j_d{1V&4T-;n5vk=wVo7Ed{FHPZ{!2=YNX_S()1w|& zH<9CI2zlMyF@uV3bk=9`)w7fXW{{IrLTde;hTGHqcduws3f)`o4tjgn6GN@Pm5Rr%;t#T~PbA#Pmn4xFc1y_iBv z*LSS8Q+>h_ffP!WLAisw5r-m8Y>$&`)Ty)M>mcoC&XP^bVk5t~USfNMsCOGjyTo%%f?}wLK zE^W*`K3HL01oyx!q)0|COLFROX_9??$fPDW6T@O!OgdTu6ij|G2)JM_v$q+|4~sxTRsyuu*xvMVzmce zo!l{oV_|r66W%-De5vh%o>XCvd-oDp{{=dKumv*gQIsj)-g|@GaqT;ix~(cm{qSd# z%uA6L$@s(bok)7@Qe6EnH1p!+_S$k*S6>qIY$y4xAWcn<&)4L z2MvNml*K{GY4x(isa}!vBB}yc0=me71G4a-T9LF1B&^#Gn+7?^(#HW3y_!tar40R$ za?ACw8u6zeeNk|d_tMZN8}kUt$NM=kRlfO0YV#3vlZQIsWjIz9G2bCB5vH$k_AEZC zPWH1d*$*qWBz(}2UNRr14G~Ho^Z3aaJy~hiq_O?2DQW(ga8ox7<#wBk8%^Rou&2va zD7;MTC&S`^gDqV4z}7aMi!vvJppQ%+0f2-5t|NlrVN_uOQf&7CrV{_j(m(1B|H%OV zS%~;65B#ePQ64`b3rdLCe@6BVbc?o5Iln*gw5z}1V+DdQeXEq_3t08?SByG|BpDpK zc81F?wvN#O`)eby+Md)%7k~SCd4E|qD^0qCqarvrs*1?K0KxxZt+p*%+^;d zq$^$&39q*|S|+HK?GM!l7jZ~AZO?IvKND*Ps3{CW$V`Hgy6qzSI2fFrHO21Loi+Uq zN>VmI?w4oCG5mC33^LX1zw_t7sB{-%f-`0@vFXqBZ{q+qiwftxr>#SVmYzx)yu&*$ zdclkh302JZ&X_K9W}TUSx*$~k!fW{mnAZMVve)qi9c%!}QUmm#{7=c+0$i)3k-d_U zqvJ0#@a8iEt-hJ{Ny3<94?k*<95zijjF&HMuTx*5^c<}P3h6YnUi?uDDKVI&VmxZs zc0|*S-UHZl&{-b&H3YPP{3@huYR1`mv%`MOF`-{K&%hNHk5G{wZpC*72nkF{#dH50F7h`eZq>rFVLiQszBvW)@yFs7uG zotPp@m~F10Z+O9tfhm2IA4Ekm$j*7NhAUC>Qe>w`Wr(juV=3jx>r`N;m?N)?%_iHB zlQo<$s(#CA-!ZCp3;;&A0%kaff6Cs##>xuNXXfxL^B1WkWeqU6YdGh4;F<%;e0I1v z$#CR$zCc<#XnD1DoMqq1CpN}5)TKsnk<_Gq)nM9<6u^PP>{O&J#e8NS z5mzxKamo}M@sY%cjBJBDj`ZYLmk+{}$%J!nPZ$-q>VwxapY`C6g#8+Ic7CWW>XmPS zca~KRhRM?YNdsd?W=#0&7El|Ujc=4{R~(f=iXY?0^1JAZ^Xo<{oW$uA8pHzd{9Vv7RV1K#&^d0!c% z2oX5o5vp=Dk>Xso_OL@VaMS3!Ju#tERw2k5ZUM;+9)JWL$f-i<{R%M~WU(MjomoWu zC9bo&OwH8#a~+rt4x9`BxM=KpDHKae<*X3uD1HH_WYU>O>xDXN$kD8`@@& z+>23zn|}4ph8aj4S(Y$9Q7ByL5}lW65#LR3@%>B!U)Q${NwQyL=bHZ2gp?lzmHSh* zuX_L3urtrdO}hPNk~%zB`s=&jsWuI9wvsVGwV?nMqxh3vj;8iTdWJ@ZLjR!|AkF-b zFMiR^FmA-U=RKmxZPEh*@q8aE;=W#A^pkkOj~Rp1;qAo+9`i#Yp87hc#!CeYC(BlAQwHZ5`-SUJ?HC5RMb;a>rr3w>I2&!} zcEV*SnZ>y!b*VEVu8!67c&GARUGbXNzLz#+;}d&(L$Fy6a_+4RM$u+=rmQfT{^`&{ zup;>omKaL%vsRTQl7S;(H%fM`!m@N#BjN++o>C=s7*)1w2tU0cYY}zT-OAiz$M)PZ zr%zLg%o#s=;|kHr`if-vlG(QA=sHGLNmk^|D0;R$1r(Xl@f`D$@K*y*5r_RFaCLfS zuWy``&m$+7b71B`2V=D)?=HR?79t?)+2;6DvUl=otD~Anak*@s%bZ7lw}pyb8pHIPM$!0nmHt2`_tATRw>LMwC!`OYdZsR zfZDLla7Eu;_nblYW+>*g_pnuQZ-g0x@N67Ksf@OEF7{+%(01PiwEMK^wCD_1+5b#TM&oah$CTVlRofE^8yvXcA zF~R08Tq;c&i`b(GF;TZ zz|+b#H_M?}H)bS3`1Bs%Mqq)Qz#rpPa{z|_j>~!-aGC%1=Bw1iL6?9dasV-4{_95N z?QLxT^eq2>@76H3>kq~Wp9Q@HEVUAs*lDsY!uQL*UzirG6x1F7k+LA+s84+HFmjjl z_+%WC$!6(xN3Ucrw9m2x-5V_Auc}aW+TeftRp}G|c0hf5#-RSY|(V9A@ZxE`8DRf+cIQpI+G(w$PYWRXJ}-w zXk?by!oIKXH{J4hI~}y@ip_t>Kc6fX}-N6V^tQ~ao=+&0p*KZwT z^}(a<+3q$E@53p#X@Sy$Z^~3svN6yG{KoJAH>HnZw|7UcF>$2#1kJ$%k4?^f_ zWf{_sEHulN0d0?}>8hOfY!sZ$afa=Gxy5Q3VRc`Y$hz=8yZ0&^YsIQ#I~U+u$r==e}(cP!H{f*LOt!WQez1es-oRqy|qEj+hxD1eQ<;lQ}N5kcTk*7=2ob z>+%dbFqh0YdKvs(e1!I1W<675R4J zG%_bS9k?ZlQPzU6wqlzb3-PB3ugV|f@>|6jWm;`73HtR{wCrdY(`jeEREzwmmuG`J zN@xTuV8SoJbE?e}y_eD^I|_HEU1u3l>rr2a>Jj~ugSw^hAv75zYUF{MkYyAY;ywcP zjC~rKPUJ{T9TDA>+r$_ak|`B%S#RW)T9BK>C;OwvZ@({?c|~tsb7hwxCOoh_n?FfhDfo zte9kR2k8;r9wrx$5Bnkz3q(PFtXz+PEZ`_7C->?ND8;sVZA!_J6ltSY8a@jqkRopn z{_GA(%Ao&Pvvaoot;;ejKQ=CQt>a`6Z#^DJ;{1F+iCPMn()*+K1MoXTQX8TSF#hCk zD)%?Wb@2`DMLm3{4{Hx=+ehv#OXXvI{q!_m-ezN0WyjZ+tTUBYWT$dL^`e($aJlR^ z&eUt8oG%w?;t~`bX^0qO3um_VpoB96Y4AwGT$3*giJ1sl?`kTbfkPi90qfP>B`E^rpqeE zPqkE zKYhy~=iU024qY8jC6+}8#M*v2lr`Yn-8)ze1|s^id7SvRO#?MAB+;#A3A8QtY~Rv> zmBH>KBU_rrw(CK3uiU2m*EA}>Q@1UM$OOz$fdq|5cJU{81!wetkwB4+gp`;#3`S1L zz{@Z954Q(;tJ4JYe9_4F6C@-I+jiIMFikTEAD^yK7Uy*k*D8sN=|T=KtRwWdpT-PU zIut`6c|KN7TXlZo?&xUoJQys|#n zoHDwTvem%ljAZS@L0s=-$h}<`SFNa6hNu*s;~+jX*cTw~4Y5W9CvgRScKo&b1CiOt zOzOt0?}%R%VHiU@N#Nsr{AtMs?-3v9u#EJEW9hsUWsDhe<%RU{_egLQViBc{?}d6p z#c8|4%nfDuzFVtL_|2U%$IIoSQD6s~7WNtY8h@(SiE&O(YmkqD*BU~6uE&Ctm;Zcs zJSE>?PtgF1H~rz18LIWE=w;o)lKZw1=yW6D+|R0ze20AVQ^HdDwhGz;)yy1LmTF17 zq=<|x6=hjDyG%;7dHIC$6wgxK$8egwdMY+9p7y0IFA9_#w|RY-`(E`k3z9~vy=AZ%jej3}_*}CfRSM}+LV*`nzZ`%r4Q zj$N=#3T{Bk7}zxrm|n#|1$kKkq{1Ui5dqwf&B%dH3Rh5l=+GAA)9LvZDr0}wd6H)s zgE%k;p-JcCg|a*TXqlQ}UHGx@2gcyG`!n(xtUGlS$AEa949%&7dbuV9&V}fg!px)` z6SG13ube8|^RVjn-#o{2XN(POT?_ftEaV|fM^KkQt$?QMlM@sJKZ1mQ{3Pa$Y+H^_ zqhW>&O~=pa!;ov9jyRyYH<(5dY@8a-!<387IE6|{1lA)@9bV#&Gmn~RoxflIqA|qL z4ST4XC^ylI&+g1gwNtQV+#aP%eaRb+pP)4{d5Ho6T)Lj2KoHHtNMuM#Y5YtzbNEpU* zK=mXh#eVh*{UJbFCNp2V59UKa3x1?9^;V+mBW>8Tass?66ODpO$K>3F7LX04sZY}T z=OR}okgF%K=K{8|bGvW;R>2Q_I-W#4K2c!f?xg|rvAT6b9loP}~ za3vKcWve{SJCHnYjzdd1PXzHen>&_dIk!2ZFZpYpI0O+9P|X2VXFk@R3Ol=!S3}?v zrzw}|#TNW0o20?3J$ZNHr1>tep?E-@ovL6Eyg{W4C=K6E&qJ}2Z*}Rr?ocgq!1CHk zw4gX@pK^~%#5H0Y-e1phdTXzX!^eTW7AOHr?J;z4BviPR=Y5e8W6#^Iq}!=s{~V`W z7GF;YemdFv0@3w^EMK8~T>PoHZH6h*Z}K$X^f>1ByH%faR((u&2w2`Nrh4bkAtBTb z+`?1Bh(&d0gF~m(zMY}(YrXu|K_LR+CF<*5w^6<|#BwD~!6Wuu&vL8f*>>R|{-f#r)pO;;qIY<@$l$Ly?7 z18LqoK^Ab;pl`jq`7D$N6*~1;|;F62nwm4d@xoVvEd9+M;7Mig!e^kLS z(Z$wwh~o9Y2}+;N>O`MB2hBs*XiXuhZp)wndrk%FbsHKE_I>vV8-73RlrAj_s znG45FeJaO3reVclWzZU`$LNL)b*9qChtrz+yarxbxErMvh}YF`1Ji_Mkp2)|L8JuV zK^tu?%kVluQcU05;Rzqec{ix*C}Qg&2xd9J?Sgt>d98L*eV@!Uppu72Fi>e=MF9Cm z^YjjcbhQgq4ba)CNjz4s(Uy`n&Cs$=;zE}gw@G#kbQj+);gBS#c#wB&WW388Sjg<6 zQ*ij;=TeqGRMeXpY{#DSIj)vjWiCO6M>Z*$ja3avEh$M)6*VID%3b0FX`WNbVie=I!v+Et(Z)lDh}yRS z@dz()R!hC|Gh4B^ToyVAZFpWl$7bhPcr-qegbv4G!>e|Mp{2;sU?riM^)|yJ#{1&F z&t#5{H`i(UApM+z3}&{wUh&NQV(UkEvf&o@0lIsB4cT&R#N6@6{R%FNu7Jz_?FO+1 zNIFAT?JA24r#kBkk`7AKbZfm`c^woK z)xJyb6YI_9cLh`nBFs2TW1a@At)&1%J(`pTz`=Z?o2nT)jJj2|7K{0jIIv|K3V)a( z2I*V(`1$ME{@}}qEnRrHl?E9DSv@l8q;zkFsytM>4O85Xh(e;uwf<#1C^gFZ6w%;h zIieIa9?@9NjykYi@Z!re=P5A-TaI1`6C*F~_E4Y?qH7{t2^W*^hFmP_33~a0>1W?i zmS-C(0zD6)pA6FXkvtJsd{rlyG3<{CqA{w?33vlS@mr;8a6C*a z_drW@AMH!CpBPm)06+h~iGc^aPW@u+`!DSK z!Iq6xWx5dk!=k$s(U8#mKSjkG#-}Ve5Ns55@s#{kqWp33I`h=+yprr>+zd9Cn6V=h zbV215lkGF}qa4!pE$_k2jfv0XwKZ9ajK>Maur2!emauIF2f-FLQ+1=a;4zQ)509pH7{0%^&yqt0FTR93f7*GPk3b{0aKH+P~V%*}?vYmF1*8xwAYgdJA#V0vw526o4 ziA7MPKSN!?QL(<=;r9Wm{J)`~`<+)t1b~8Aze-JiqoAIx?SB~v5ZQko8S!0!k{e*r z*1H?{;2%*L))e9VstN@(?u*qx67D8OoJf>X{=Jw(S>E+gMdOV#)+9bh`{a^GFN-aC zJ&9K5NvRW(3OQ`Kjou%_PWSE~WKq*P7dHI|Bs1tEJf3$YD-=Uh2lZ(eyZ0qe!nOs6 zEpHYDvuaM%%>>Q;*k!n|()+PJVfQBU$la8Zzaqy3e(QhW%!2DXXgWCXkvZ0N|Mt|v zAp$;sL?~(khq$5mT1^&&i%ppo4W1dVq`!=>yBSvV(8z$LkHJLx90_rZd)CnJ50MT^ zZ2z4Ce(P$KxpCvl({yvQwuTMUPpwIKO>J9`?=u?71H`?jBrkpBD$2awUZPDCr`$u2 z2i7v=OK&&FgY~n=dcTY-Sa(c=Hu{`90+fY!*yZxXyX$TonMyYGA6;kFF9-J;2Yg+} zcQe;d&Z^!t_g>^IqQMt!O|m_&dXG_!1A533Pi>^X|g=!Bn_UctF;Z=*i4J%L+EMJQC~nBF}1l^ zt0C(jx5uuIdw#l?E{ob34=EyUv3mSOuSHNOA1w?7qexIO!-)CK?k?dg?wU?qR3$mr zV=WhgHk(|>rpc`20vndMLA_xl2wWcJhXBNGBJsT;FCYefW#L^i^^a$ma7uQ8aof{X z+UC1$H(+b5S)47qdae!QJGLMbKwntD)qUBEOo|9xquD<9#+#}BA}RR+RZp^#=R>pF z^Nfx6PY*JtX2`zV7lLsY^=Clgca~3Us{g+%_$Lbhr9uD;JaW%;9d$Bp=q1Buq_B2aMPb^p#U!K+M${zDHoS|9 z(ZRVS1vlteLOfFE;FvtZ!C6({p!4(B2c|mjudZuA`}7TLOu|h!{a{0!+s(ag8x@mX zFTzw5h;UMcr?oAdQNTygNF$9H<>6H&)5J2%TbGfp8!P#oyjgO*m{b;U2DLhXo!krJ zpE_iEHu3O>Xn^ydkaE|$1-Fp*&ZNU4EH6X#J7I!NEHsil1inUjKUO{ewtd3m5+whB zM}uGS+<$5CTN>#7qJiTdG#H@(&;X(pTg+}$e?;v_?N1u;{6T~3kd3BN0%}|etb=rP zR5CFo@%7IA!@D*B4Q32KN}6u^!-i~`&G>AZ7t;PjW-KcuVXY3`X`eqqk4(lHPCYU# zLavytb;1^BDk<}J!UdrJO}0!8~4 z<<~spExC*0b2}vHqHczQy|I)BgitEeOK^ From 7da3501d4c30d837b536b980400377fad2b49319 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Thu, 30 Nov 2023 14:00:28 +0800 Subject: [PATCH 02/97] add new interface for coverage used for cv32e40p specific floating point pipeline coverage Signed-off-by: Vaibhav Jain --- cv32e40p/env/uvme/uvme_cv32e40p_cntxt.sv | 1 + cv32e40p/env/uvme/uvme_cv32e40p_env.sv | 5 + cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv | 32 +++ cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 236 +++++++++++++++++++++++ 4 files changed, 274 insertions(+) diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_cntxt.sv b/cv32e40p/env/uvme/uvme_cv32e40p_cntxt.sv index 1902c853da..c953b3a886 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_cntxt.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_cntxt.sv @@ -30,6 +30,7 @@ class uvme_cv32e40p_cntxt_c extends uvm_object; virtual uvmt_cv32e40p_vp_status_if vp_status_vif; ///< Virtual interface for Virtual Peripherals virtual uvma_interrupt_if intr_vif ; ///< Virtual interface for interrupts virtual uvma_debug_if debug_vif ; ///< Virtual interface for debug + virtual uvmt_cv32e40p_cov_if cov_vif ; ///< Virtual interface for custom coverage // Agent context handles uvma_cv32e40p_core_cntrl_cntxt_c core_cntrl_cntxt; diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_env.sv b/cv32e40p/env/uvme/uvme_cv32e40p_env.sv index 833d048a41..224198fb77 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_env.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_env.sv @@ -377,6 +377,11 @@ function void uvme_cv32e40p_env_c::retrieve_vifs(); `uvm_fatal("UVME_CV32E40P_ENV", $sformatf("No uvmt_cv32e40p_debug_cov_assert_if found in config database")) end + void'(uvm_config_db#(virtual uvmt_cv32e40p_cov_if)::get(this, "", "cov_vif", cntxt.cov_vif)); + if (cntxt.cov_vif == null) begin + `uvm_fatal("UVME_CV32E40P_ENV", $sformatf("No uvmt_cv32e40p_cov_if found in config database")) + end + endfunction: retrieve_vifs diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index e52641cc31..4d0e52d0ee 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -504,6 +504,37 @@ module uvmt_cv32e40p_tb; .pending_enabled_irq() ); + //Interface for coverage components + uvmt_cv32e40p_cov_if cov_if( + .clk_i(clknrst_if.clk), + .rst_ni(clknrst_if.reset_n), + .if_stage_instr_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.instr_rvalid_i), + .if_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.instr_rdata_i), + .id_stage_instr_valid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.instr_valid_i), + .id_stage_instr_rdata_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.instr_rdata_i), + .apu_req(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_req_o), + .apu_gnt(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_gnt_i), + .apu_busy(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_busy_i), + .apu_op(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_op_o), + .apu_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.apu_rvalid_i), + .apu_perf_wb_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_perf_wb_o), + .id_stage_apu_op_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_op_ex_o), + .id_stage_apu_en_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.apu_en_ex_o), + .regfile_waddr_wb_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_waddr_wb_o), + .regfile_we_wb_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_we_wb_o), + .regfile_alu_waddr_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_waddr_fw_o), + .regfile_alu_we_ex_o(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_we_fw_o), + .ex_mulh_active(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.mulh_active), + .ex_mult_op_ex(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.mult_operator_i), + .ex_data_misaligned_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_misaligned_i), + .ex_data_misaligned_ex_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_misaligned_ex_i), + .ex_data_req_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_req_i), + .ex_data_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_rvalid_i), + .ex_regfile_alu_we_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_we_i), + .ex_apu_valid(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_valid), + .ex_apu_rvalid_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_rvalid_q) + ); + // Instantiate debug assertions uvmt_cv32e40p_debug_assert u_debug_assert(.cov_assert_if(debug_cov_assert_if)); @@ -601,6 +632,7 @@ module uvmt_cv32e40p_tb; uvm_config_db#(virtual uvmt_cv32e40p_debug_cov_assert_if)::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_cov_vif"), .value(debug_cov_assert_if) ); uvm_config_db#(virtual uvmt_cv32e40p_isa_covg_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("isa_covg_vif"), .value(isa_covg_if) ); uvm_config_db#(virtual uvma_debug_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_vif"), .value(debug_if) ); + uvm_config_db#(virtual uvmt_cv32e40p_cov_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("cov_vif"), .value(cov_if) ); `RVFI_CSR_UVM_CONFIG_DB_SET(fflags) `RVFI_CSR_UVM_CONFIG_DB_SET(frm) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 06ed86a768..3019553ca4 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -460,4 +460,240 @@ interface uvmt_cv32e40p_rvvi_if #( endinterface +// +//Interface for custom TB coverage component +// +interface uvmt_cv32e40p_cov_if + + import uvm_pkg::*; + import uvme_cv32e40p_pkg::*; + ( + input clk_i, + input rst_ni, + input if_stage_instr_rvalid_i, + input [31:0] if_stage_instr_rdata_i, + input id_stage_instr_valid_i, + input [31:0] id_stage_instr_rdata_i, + input apu_req, + input apu_gnt, + input apu_busy, + input [5:0] apu_op, + input apu_rvalid_i, + input apu_perf_wb_o, + input [5:0] id_stage_apu_op_ex_o, + input id_stage_apu_en_ex_o, + input [5:0] regfile_waddr_wb_o, // regfile write port A addr from WB stage + input regfile_we_wb_o, + input [5:0] regfile_alu_waddr_ex_o, // regfile write port B addr from EX stage + input regfile_alu_we_ex_o, + input ex_mulh_active, + input [2:0] ex_mult_op_ex, + input ex_data_misaligned_i, + input ex_data_misaligned_ex_i, + input ex_data_req_i, + input ex_data_rvalid_i, + input ex_regfile_alu_we_i, + input ex_apu_valid, + input ex_apu_rvalid_q, + + output logic[5:0] o_curr_fpu_apu_op_if, + output logic[5:0] o_last_fpu_apu_op_if, + output logic[4:0] if_clk_cycle_window, + output [4:0] curr_fpu_fd, + output [4:0] curr_fpu_rd, + output [5:0] curr_rd_at_ex_regfile_wr_contention, + output [5:0] curr_rd_at_wb_regfile_wr_contention, + output [5:0] prev_rd_waddr_contention, + output logic[1:0] contention_state, + output b2b_contention, + output is_mulh_ex, + output is_misaligned_data_req_ex, + output is_post_inc_ld_st_inst_ex, + output ex_apu_valid_memorised + ); + + logic [4:0] clk_cycle_window; + logic [5:0] curr_fpu_apu_op_if; + logic [5:0] last_fpu_contention_op_if; + logic [5:0] prev_regfile_waddr_contention; + logic [4:0] regfile_waddr_wb_fd; + logic [4:0] regfile_alu_waddr_ex_fd; + logic [4:0] regfile_waddr_wb_rd; + logic [4:0] regfile_alu_waddr_ex_rd; + logic [5:0] regfile_waddr_ex_contention; + logic [5:0] regfile_waddr_wb_contention; + logic [1:0] contention_valid; + logic b2b_contention_valid; + + initial begin + clk_cycle_window = 0; + curr_fpu_apu_op_if = 0; + regfile_waddr_wb_fd = 0; + regfile_alu_waddr_ex_fd = 0; + regfile_waddr_wb_rd = 0; + regfile_alu_waddr_ex_rd = 0; + regfile_waddr_ex_contention = 0; + regfile_waddr_wb_contention = 0; + contention_valid = 0; + b2b_contention_valid = 0; + end + + clocking mon_cb @(posedge clk_i); + default input #1step output #1ns; + input if_stage_instr_rvalid_i; + input if_stage_instr_rdata_i; + input id_stage_instr_valid_i; + input id_stage_instr_rdata_i; + input apu_req; + input apu_gnt; + input apu_busy; + input apu_op; + input apu_rvalid_i; + input apu_perf_wb_o; + input id_stage_apu_op_ex_o; + input id_stage_apu_en_ex_o; + endclocking : mon_cb + + //calculate each APU operation's current clock cycle number during execution for functional coverage use + always @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + clk_cycle_window = 0; + curr_fpu_apu_op_if = 0; + end + else begin + if((clk_cycle_window == 0) && (apu_req == 1)) begin + clk_cycle_window = 1; + curr_fpu_apu_op_if = apu_op; + end + else if((clk_cycle_window != 0) && (apu_req == 1)) begin + clk_cycle_window = 1; + curr_fpu_apu_op_if = apu_op; + end + else if((clk_cycle_window != 0) && (apu_busy == 1)) begin + clk_cycle_window += 1; + end + else begin + clk_cycle_window = 0; + end + end + end + + //Model APU contention state in EX/WB for functional coverage + always @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + contention_valid <= 0; + b2b_contention_valid <= 0; + last_fpu_contention_op_if <= 0; + prev_regfile_waddr_contention <= 0; + end + else begin + if (((contention_valid == 0) || (contention_valid == 2)) && (apu_perf_wb_o)) begin + contention_valid <= 1; //set contention_valid + b2b_contention_valid <= 0; + `ifndef FPU_LAT_1_CYC + prev_regfile_waddr_contention <= regfile_alu_waddr_ex_o; + `else + prev_regfile_waddr_contention <= regfile_waddr_wb_o; + last_fpu_contention_op_if <= curr_fpu_apu_op_if; + `endif + end + else if((contention_valid == 1) && (apu_perf_wb_o)) begin + contention_valid <= 1; //reset contention_valid + b2b_contention_valid <= 1; + //if no APU execution during contention then nothing to do + //else TODO: check if during contention another APU transaction + //can go through? + `ifndef FPU_LAT_1_CYC + prev_regfile_waddr_contention <= regfile_alu_waddr_ex_o; + `else + prev_regfile_waddr_contention <= regfile_waddr_wb_o; + `endif + end + else if((contention_valid == 1) && (!apu_perf_wb_o)) begin + contention_valid <= 2; //stalled write complete after contention + b2b_contention_valid <= 0; + end + else begin + contention_valid <= 0; + b2b_contention_valid <= 0; + end + end + end + + + //sample each APU operation's destination register address for functional coverage + always @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + regfile_alu_waddr_ex_fd <= 0; + regfile_alu_waddr_ex_rd <= 0; + regfile_waddr_wb_fd <= 0; + regfile_waddr_wb_rd <= 0; + regfile_waddr_wb_contention <= 0; + regfile_waddr_ex_contention <= 0; + end + else begin +`ifndef FPU_LAT_1_CYC //Case for FPU Latency {0,2,3,4}, with regfile write from EX stage with highest priority of APU + if (((apu_req == 1) || (apu_busy == 1)) && (regfile_alu_we_ex_o == 1) && (apu_rvalid_i == 1)) begin + regfile_alu_waddr_ex_fd <= (regfile_alu_waddr_ex_o - 32); + regfile_alu_waddr_ex_rd <= (regfile_alu_waddr_ex_o < 32) ? regfile_alu_waddr_ex_o : 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention <= 0; + end + else if ((contention_valid == 1) && (regfile_alu_we_ex_o == 1) && !apu_perf_wb_o) begin // write for stalled regfile wr at contention + regfile_alu_waddr_ex_fd <= 0; + regfile_alu_waddr_ex_rd <= 0; + regfile_waddr_ex_contention <= regfile_alu_waddr_ex_o; //should not be >31, check for illegal in coverage + regfile_waddr_wb_contention <= 0; + end + `else + //Case FPU Latency = 1; regfile wr from WB;LSU > priority;no LSU contention, F-inst regfile wr succeed + if ((apu_busy == 1) && (regfile_we_wb_o == 1) && (apu_rvalid_i == 1) && (!apu_perf_wb_o)) begin + regfile_waddr_wb_fd <= (regfile_waddr_wb_o - 32); + regfile_waddr_wb_rd <= (regfile_waddr_wb_o < 32) ? regfile_waddr_wb_o : 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention <= 0; + end + //Case FPU Latency = 1; regfile wr from WB;LSU > priority;LSU contention,F-inst regfile wr stall + else if((apu_busy == 1) && (regfile_we_wb_o == 1) && (apu_rvalid_i == 1) && (apu_perf_wb_o)) begin + regfile_waddr_wb_fd <= 0 + regfile_waddr_wb_rd <= 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention = regfile_waddr_wb_o; //should not be >31, check for illegal in coverage + end + //Case FPU Latency = 1;regfile wr from WB;LSU > priority;LSU contention - FPU reg write cycle after contention + else if((contention_valid == 1) && (regfile_we_wb_o == 1) && !apu_perf_wb_o) begin + regfile_waddr_wb_fd <= (regfile_waddr_wb_o - 32); + regfile_waddr_wb_rd <= (regfile_waddr_wb_o < 32) ? regfile_waddr_wb_o : 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention <= 0; + end + `endif + else begin + regfile_alu_waddr_ex_fd <= 0; + regfile_alu_waddr_ex_rd <= 0; + regfile_waddr_wb_fd <= 0; + regfile_waddr_wb_rd <= 0; + regfile_waddr_ex_contention <= 0; + regfile_waddr_wb_contention <= 0; + end + end + end + + assign curr_fpu_fd = regfile_alu_waddr_ex_fd | regfile_waddr_wb_fd; + assign curr_fpu_rd = regfile_alu_waddr_ex_rd | regfile_waddr_wb_rd; + assign if_clk_cycle_window = clk_cycle_window; + assign o_curr_fpu_apu_op_if = curr_fpu_apu_op_if; + assign o_last_fpu_apu_op_if = last_fpu_contention_op_if; + assign curr_rd_at_ex_regfile_wr_contention = regfile_waddr_ex_contention; + assign curr_rd_at_wb_regfile_wr_contention = regfile_waddr_wb_contention; + assign contention_state = contention_valid; + assign b2b_contention = b2b_contention_valid; + assign prev_rd_waddr_contention = prev_regfile_waddr_contention; + assign is_mulh_ex = ex_mulh_active && (ex_mult_op_ex == 3'h6); + assign is_misaligned_data_req_ex = ex_data_misaligned_i || ex_data_misaligned_ex_i; + assign is_post_inc_ld_st_inst_ex = (ex_data_req_i || ex_data_rvalid_i) && ex_regfile_alu_we_i; + assign ex_apu_valid_memorised = ex_apu_valid & ex_apu_rvalid_q; + +endinterface : uvmt_cv32e40p_cov_if + `endif // __UVMT_CV32E40P_TB_IFS_SV__ From 2ce11c8ff381ede1c1efb758a4d90e65d9559fa9 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Thu, 30 Nov 2023 14:06:28 +0800 Subject: [PATCH 03/97] add configs fpu_latency,rv32f_fcov_en,zfinx_fcov_en based on cv32e40p core supported ISA config Signed-off-by: Vaibhav Jain --- cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv | 26 +++++ cv32e40p/env/uvme/uvme_cv32e40p_constants.sv | 108 +++++++++++++++++++ cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv | 3 + cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv | 26 +++-- 4 files changed, 155 insertions(+), 8 deletions(-) diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv index 01cdaafe8d..5edb260838 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv @@ -68,6 +68,12 @@ class uvme_cv32e40p_cfg_c extends uvma_core_cntrl_cfg_c; bit max_rand_instr_latency; // variable set by plusarg +max_rand_instr_latency=<> int max_rand_instr_latency_limit; + rand int rv32f_fcov_en; + rand int zfinx_fcov_en; + rand int fpu_latency_addmul; + rand int fpu_latency_others; + rand int fpu_latency; + // Agent cfg handles rand uvma_clknrst_cfg_c clknrst_cfg; rand uvma_interrupt_cfg_c interrupt_cfg; @@ -89,6 +95,9 @@ class uvme_cv32e40p_cfg_c extends uvma_core_cntrl_cfg_c; `uvm_field_int ( trn_log_enabled , UVM_DEFAULT ) `uvm_field_int ( sys_clk_period , UVM_DEFAULT + UVM_DEC) //`uvm_field_int ( debug_clk_period , UVM_DEFAULT + UVM_DEC) + `uvm_field_int ( rv32f_fcov_en, UVM_DEFAULT ) + `uvm_field_int ( zfinx_fcov_en, UVM_DEFAULT ) + `uvm_field_int ( fpu_latency, UVM_DEFAULT ) `uvm_field_object(clknrst_cfg , UVM_DEFAULT) `uvm_field_object(interrupt_cfg , UVM_DEFAULT) @@ -110,6 +119,11 @@ class uvme_cv32e40p_cfg_c extends uvma_core_cntrl_cfg_c; soft trn_log_enabled == 1; soft sys_clk_period == uvme_cv32e40p_sys_default_clk_period; // see uvme_cv32e40p_constants.sv //soft debug_clk_period == uvme_cv32e40p_debug_default_clk_period; + soft rv32f_fcov_en == 0; + soft zfinx_fcov_en == 0; + soft fpu_latency_addmul == FPU_ADDMUL_LAT_DV; + soft fpu_latency_others == FPU_OTHERS_LAT_DV; + soft fpu_latency == FPU_ADDMUL_LAT_DV; } constraint zero_stall_sim_dist_cons { @@ -523,6 +537,18 @@ function void uvme_cv32e40p_cfg_c::post_randomize(); // Disable some CSR checks from all tests configure_disable_csr_checks(); + if(fpu_latency_addmul != fpu_latency_others) begin + `uvm_fatal("uvme_cv32e40p_cfg_c", "FPU Latency Parameter not equal, fpu_latency config value cant be used"); + end + + if (cov_model_enabled && (RV32ZFINX inside {uvme_cv32e40p_pkg::cv32e40p_core_isa_list})) begin + zfinx_fcov_en = 1; + rv32f_fcov_en = 0; + end else if (cov_model_enabled && (RV32F inside {uvme_cv32e40p_pkg::cv32e40p_core_isa_list})) begin + rv32f_fcov_en = 1; + zfinx_fcov_en = 0; + end + endfunction : post_randomize function void uvme_cv32e40p_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cntxt); diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv b/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv index 3041699ce4..1815475bcc 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv @@ -55,6 +55,55 @@ parameter CV_VP_OBI_SLV_RESP_BASE = CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RES parameter CV_VP_SIG_WRITER_BASE = CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET; parameter CV_VP_FENCEI_TAMPER_BASE = CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET; +parameter TB_OPCODE_SYSTEM = 7'h73; +parameter TB_OPCODE_FENCE = 7'h0f; +parameter TB_OPCODE_OP = 7'h33; +parameter TB_OPCODE_OPIMM = 7'h13; +parameter TB_OPCODE_STORE = 7'h23; +parameter TB_OPCODE_LOAD = 7'h03; +parameter TB_OPCODE_BRANCH = 7'h63; +parameter TB_OPCODE_JALR = 7'h67; +parameter TB_OPCODE_JAL = 7'h6f; +parameter TB_OPCODE_AUIPC = 7'h17; +parameter TB_OPCODE_LUI = 7'h37; +parameter TB_OPCODE_AMO = 7'h2F; + +parameter TB_OPCODE_OP_FP = 7'h53; +parameter TB_OPCODE_OP_FMADD = 7'h43; +parameter TB_OPCODE_OP_FNMADD = 7'h4f; +parameter TB_OPCODE_OP_FMSUB = 7'h47; +parameter TB_OPCODE_OP_FNMSUB = 7'h4b; +parameter TB_OPCODE_STORE_FP = 7'h27; +parameter TB_OPCODE_LOAD_FP = 7'h07; + +parameter TB_INS_FMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FMADD}; +parameter TB_INS_FMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FMSUB}; +parameter TB_INS_FNMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FNMSUB}; +parameter TB_INS_FNMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FNMADD}; +parameter TB_INS_FADD = {5'b00000, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSUB = {5'b00001, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMUL = {5'b00010, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FDIV = {5'b00011, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSQRT = {5'b01011, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSGNJS = {5'b00100, 2'b00, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSGNJNS = {5'b00100, 2'b00, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FSGNJXS = {5'b00100, 2'b00, 10'b?, 3'b010, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMIN = {5'b00101, 2'b00, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMAX = {5'b00101, 2'b00, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCVTWS = {5'b11000, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCVTWUS = {5'b11000, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMVXS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FEQS = {5'b10100, 2'b00, 10'b?, 3'b010, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FLTS = {5'b10100, 2'b00, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FLES = {5'b10100, 2'b00, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCLASS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b001, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCVTSW = {5'b11010, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FCVTSWU = {5'b11010, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FMVSX = {5'b11110, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, TB_OPCODE_OP_FP}; +parameter TB_INS_FLW = {12'b?,5'b?,3'b010,5'b?,TB_OPCODE_LOAD_FP}; +parameter TB_INS_FSW = {7'b?,5'b?,5'b?,3'b010,5'b?,TB_OPCODE_STORE_FP}; + + //XPULP instructions custom opcodes parameter OPCODE_CUSTOM_0 = 7'h0b; parameter OPCODE_CUSTOM_1 = 7'h2b; @@ -443,4 +492,63 @@ parameter INSTR_CV_SUB_DIV2 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b0 parameter INSTR_CV_SUB_DIV4 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; parameter INSTR_CV_SUB_DIV8 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; +parameter APU_OP_FMADD = {6'h00}; +parameter APU_OP_FNMSUB = {6'h01}; +parameter APU_OP_FADD = {6'h02}; +parameter APU_OP_FMUL = {6'h03}; +parameter APU_OP_FDIV = {6'h04}; +parameter APU_OP_FSQRT = {6'h05}; +parameter APU_OP_FSGNJ = {6'h06}; +parameter APU_OP_FMINMAX = {6'h07}; +parameter APU_OP_FCMP = {6'h08}; +parameter APU_OP_FCLASSIFY = {6'h09}; +parameter APU_OP_F2F = {6'h0A}; +parameter APU_OP_F2I = {6'h0B}; +parameter APU_OP_I2F = {6'h0C}; + +parameter APU_OP_FMSUB = {6'h10}; +parameter APU_OP_FNMADD = {6'h11}; +parameter APU_OP_FSUB = {6'h12}; +parameter APU_OP_FSGNJ_SE = {6'h16}; +parameter APU_OP_F2I_U = {6'h1B}; +parameter APU_OP_I2F_U = {6'h1C}; + +//Additional defines based on DUT config parameters +`ifdef PULP //PULP = 1 + `ifndef FPU //FPU = 0 + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32X } + `else //FPU = 1 + `ifndef ZFINX + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32X, RV32F, RV32FC } + `else + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32X, RV32ZFINX } + `endif + `endif +`else //PULP = 0, FPU = 1 + `ifdef FPU + `ifndef ZFINX + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32F, RV32FC } + `else + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C, RV32ZFINX } + `endif + `endif +`endif + +//Base default ISA for tests if nothing else is defined +`ifndef CV32E40P_ISA_DV + `define CV32E40P_ISA_DV { RV32I, RV32M, RV32C } +`endif + +`ifdef FPU_ADDMUL_LAT + parameter FPU_ADDMUL_LAT_DV = `FPU_ADDMUL_LAT; +`else + parameter FPU_ADDMUL_LAT_DV = 0; +`endif + +`ifdef FPU_OTHERS_LAT + parameter FPU_OTHERS_LAT_DV = `FPU_OTHERS_LAT; +`else + parameter FPU_OTHERS_LAT_DV = 0; +`endif + `endif // __UVME_CV32E40P_CONSTANTS_SV__ diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv index 3e03846598..baa1c59f5c 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv @@ -27,6 +27,7 @@ `include "uvma_clknrst_macros.sv" `include "uvme_cv32e40p_macros.sv" + /** * Encapsulates all the types needed for an UVM environment capable of driving/ * monitoring and verifying the behavior of an CV32E40P design. @@ -53,6 +54,8 @@ package uvme_cv32e40p_pkg; `include "uvme_cv32e40p_param_all_insn.sv" // fixme: remove this and import package from core-v-cores (e.g cv32e40p_tracer_pkg.sv) `include "uvme_cv32e40p_tdefs.sv" + cv32e40p_isa_ext_t cv32e40p_core_isa_list[$] = `CV32E40P_ISA_DV; // CV32E40P supported ISAs + // Objects `include "uvma_cv32e40p_core_cntrl_cntxt.sv" `include "uvme_cv32e40p_cfg.sv" diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv b/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv index a8a3b0eaed..24d6c341b0 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_tdefs.sv @@ -124,17 +124,27 @@ typedef enum { } fetch_toggle_t; typedef enum logic [2:0] { - EBREAKM = 1, - TRIGGER = 2, - HALTREQ = 3, - STEP = 4, - RESETHALTREQ = 5 + EBREAKM = 1, + TRIGGER = 2, + HALTREQ = 3, + STEP = 4, + RESETHALTREQ = 5 } dcsr_cause_t; typedef enum logic [4:0] { - CODE_ILLEGAL = 2, - CODE_EBREAK = 3, - CODE_ECALL = 11 + CODE_ILLEGAL = 2, + CODE_EBREAK = 3, + CODE_ECALL = 11 } exception_code_t; +typedef enum { + RV32I, + RV32M, + RV32C, + RV32F, + RV32FC, + RV32ZFINX, + RV32X +} cv32e40p_isa_ext_t; + `endif // __UVME_CV32E40P_TDEFS_SV__ From 5bc131a3718a80dcbfe595bbf18689434d87cc7c Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Thu, 30 Nov 2023 14:11:48 +0800 Subject: [PATCH 04/97] added cv32e40p specific floating instr specific coverage for rv32f and zfinx Signed-off-by: Vaibhav Jain --- .../env/uvme/cov/uvme_cv32e40p_cov_model.sv | 20 +- .../uvme/cov/uvme_cv32e40p_fp_instr_covg.sv | 766 +++++++++++++++++ .../cov/uvme_cv32e40p_zfinx_instr_covg.sv | 772 ++++++++++++++++++ cv32e40p/env/uvme/uvme_cv32e40p_macros.sv | 110 +++ cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv | 2 + 5 files changed, 1666 insertions(+), 4 deletions(-) create mode 100644 cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv create mode 100644 cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv index 519f0f6a12..2068dadb06 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_cov_model.sv @@ -29,10 +29,12 @@ class uvme_cv32e40p_cov_model_c extends uvm_component; uvme_cv32e40p_cfg_c cfg; uvme_cv32e40p_cntxt_c cntxt; - uvme_rv32isa_covg isa_covg; - uvme_interrupt_covg interrupt_covg; - uvme_debug_covg debug_covg; - uvme_rv32x_hwloop_covg rv32x_hwloop_covg; + uvme_rv32isa_covg isa_covg; + uvme_interrupt_covg interrupt_covg; + uvme_debug_covg debug_covg; + uvme_rv32x_hwloop_covg rv32x_hwloop_covg; + uvme_cv32e40p_fp_instr_covg cv32e40p_fp_instr_covg; + uvme_cv32e40p_zfinx_instr_covg cv32e40p_zfinx_instr_covg; `uvm_component_utils_begin(uvme_cv32e40p_cov_model_c) `uvm_field_object(cfg , UVM_DEFAULT) @@ -113,6 +115,16 @@ function void uvme_cv32e40p_cov_model_c::build_phase(uvm_phase phase); rv32x_hwloop_covg = uvme_rv32x_hwloop_covg::type_id::create("rv32x_hwloop_covg", this); + if( (cfg.rv32f_fcov_en == 1) && (cfg.zfinx_fcov_en == 0) ) begin + cv32e40p_fp_instr_covg = uvme_cv32e40p_fp_instr_covg::type_id::create("cv32e40p_fp_instr_covg", this); + uvm_config_db#(uvme_cv32e40p_cntxt_c)::set(this, "cv32e40p_fp_instr_covg", "cntxt", cntxt); + end else if ( (cfg.zfinx_fcov_en == 1) && (cfg.rv32f_fcov_en == 0) ) begin + cv32e40p_zfinx_instr_covg = uvme_cv32e40p_zfinx_instr_covg::type_id::create("cv32e40p_zfinx_instr_covg", this); + uvm_config_db#(uvme_cv32e40p_cntxt_c)::set(this, "cv32e40p_zfinx_instr_covg", "cntxt", cntxt); + end else if ( (cfg.rv32f_fcov_en == 1) && (cfg.zfinx_fcov_en == 1) ) begin + `uvm_fatal("FCOV", "Illegal Config with FCOV enable for both RV32F and RV32ZFINX") + end + endfunction : build_phase function void uvme_cv32e40p_cov_model_c::connect_phase(uvm_phase phase); diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv new file mode 100644 index 0000000000..525d156f99 --- /dev/null +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv @@ -0,0 +1,766 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright 2023 OpenHW Group +// Copyright 2023 Dolphin Design +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// +/////////////////////////////////////////////////////////////////////////////// + +class uvme_cv32e40p_fp_instr_covg extends uvm_component; + /* + * Class members + */ + uvme_cv32e40p_cfg_c cfg; + uvme_cv32e40p_cntxt_c cntxt; + + `uvm_component_utils_begin(uvme_cv32e40p_fp_instr_covg) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + extern function new(string name = "cv32e40p_fp_instr_covg", uvm_component parent = null); + extern function void build_phase(uvm_phase phase); + extern task run_phase(uvm_phase phase); + extern task sample_clk_i(); + + `define FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND \ + (cp_is_mulh_ex == 0) & (cp_is_misaligned_data_req_ex == 0) & (cp_is_post_inc_ld_st_inst_ex == 0) & (cp_ex_apu_valid_memorised == 0) + + `define FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES \ + illegal_bins clk_2_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 0) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); \ + illegal_bins clk_3_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 1) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); \ + illegal_bins clk_4_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2, 3}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 2) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); + + `define FPU_ZERO_LATENCY_ILLEGAL_BUSY \ + illegal_bins apu_busy_curr_apu_op_not_div_sqrt = ( !binsof(cp_curr_fpu_apu_op_multicycle) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ + with ( ((cp_curr_fpu_apu_op_multicycle + 1) * (fpu_latency == 0)) != 0 ); + + `define IGNORE_BINS_NON_FD_F_INSTR \ + ignore_bins non_fd_f_inst = binsof(cp_curr_fpu_apu_op) intersect {`APU_INSTR_WITH_NO_FD}; + + `define IGNORE_BINS_ZERO_LAT_FPU_OP \ + ignore_bins zero_lat_inst = ( !binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ + with ( ((cp_curr_fpu_apu_op + 1) * (fpu_latency == 0)) != 0 ); + + `define IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU \ + ignore_bins in_contention_lsu_wr = ( binsof(cp_apu_contention) intersect {1} ) \ + with ( ((cp_curr_fpu_apu_op + 1) * (fpu_latency == 1)) != 0 ); + + `define IGNORE_BINS_NON_FS3_F_INSTR \ + ignore_bins non_fs3_f_inst = !binsof(cp_id_stage_f_inst) intersect {`RV32F_INSTR_WITH_NO_FS3}; + + `define IGNORE_BINS_NON_RD_F_INSTR \ + ignore_bins non_rd_f_inst = !binsof(cp_curr_fpu_apu_op) intersect {`APU_INSTR_WITH_NO_FD}; + + `define IGNORE_BINS_NON_RS_F_INSTR_IN_ID \ + ignore_bins non_rs_id_stage_f_inst = !binsof(cp_id_stage_f_inst) intersect {APU_OP_I2F, APU_OP_I2F_U}; + + `define IGNORE_BINS_NON_RS1_CV32E40P_INSTR \ + ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL}; + + `define IGNORE_BINS_NON_RS2_CV32E40P_INSTR \ + ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_INSTR_WITH_NO_RS2}; + + `define IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE \ + ignore_bins non_stalled_contention_wr_state = binsof(cp_contention_state) intersect {0,1}; + + `define IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION \ + ignore_bins non_fd_f_inst = binsof(cp_last_fpu_apu_op_at_contention) intersect {`APU_INSTR_WITH_NO_FD}; + + `define IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR \ + ignore_bins contention_at_lsu_wr = binsof(cp_apu_contention) intersect {1}; + + `define IGNORE_BINS_NON_RD_F_INSTR_AT_CONTENTION \ + ignore_bins non_rd_f_inst = !binsof(cp_last_fpu_apu_op_at_contention) intersect {`APU_INSTR_WITH_NO_FD}; + + `define IGNORE_BINS_NO_CONTENTION \ + ignore_bins no_contention = binsof(cp_apu_contention) intersect {1}; + + `define IGNORE_BINS_NO_CONTENTION_LSU \ + ignore_bins no_contention_lsu_wr = binsof(cp_apu_contention) intersect {0}; + + `define CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES \ + cp_is_mulh_ex, cp_is_misaligned_data_req_ex, cp_is_post_inc_ld_st_inst_ex, cp_ex_apu_valid_memorised + + /* + * Covergroups + */ + + covergroup cg_f_multicycle(int fpu_latency); + `per_instance_fcov + option.at_least = 10; + + cp_if_stage_f_inst : coverpoint `COVIF_CB.if_stage_instr_rdata_i iff (`COVIF_CB.if_stage_instr_rvalid_i == 1) { + `RV32F_INSTR_BINS + option.weight = 5; + } + + cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + `RV32F_INSTR_BINS + option.weight = 5; + } + + cp_id_stage_apu_op_ex_o : coverpoint `COVIF_CB.id_stage_apu_op_ex_o iff (`COVIF_CB.id_stage_apu_en_ex_o == 1) { + `FPU_OP_BINS + option.weight = 5; + } + + cp_f_multicycle_clk_window : coverpoint cntxt.cov_vif.if_clk_cycle_window { + bins clk1 = {1}; + bins clk2 = {2}; + bins clk3 = {3}; + bins clk4 = {4}; + bins clk5 = {5}; + bins clk6 = {6}; + bins clk7 = {7}; + bins clk8 = {8}; + bins clk9 = {9}; + bins clk10 = {10}; + bins clk11 = {11}; + bins clk12 = {12}; + bins clk13 = {13}; + bins clk14 = {14}; + bins clk15 = {15}; + bins clk16 = {16}; + bins clk17 = {17}; + bins clk18 = {18}; + bins clk19 = {19}; + ignore_bins ignore_idle = {0}; + illegal_bins clk_more_than_19 = {[20:31]}; + } + + cp_id_stage_inst_valid : coverpoint `COVIF_CB.id_stage_instr_valid_i { + bins id_stage_instr_valid = {1}; + option.weight = 1; + } + + cp_if_stage_inst_valid : coverpoint `COVIF_CB.if_stage_instr_rvalid_i { + bins if_stage_instr_valid = {1}; + option.weight = 1; + } + + cp_id_stage_apu_en_ex_o : coverpoint `COVIF_CB.id_stage_apu_en_ex_o { + bins id_stage_apu_en_ex_1 = {1}; + bins id_stage_apu_en_ex_0_to_1 = (0 => 1); + option.weight = 1; + } + + cp_apu_req_valid : coverpoint `COVIF_CB.apu_req { + bins apu_req_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_grant_valid : coverpoint `COVIF_CB.apu_gnt { + bins apu_gnt_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_busy : coverpoint `COVIF_CB.apu_busy { + bins apu_busy_high = {1'b1}; + option.weight = 1; + } + + cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { + `FPU_OP_BINS + option.weight = 5; + } + + cp_curr_fpu_apu_op_at_apu_req : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) ) + { + `FPU_OP_BINS + option.weight = 5; + } + + cp_curr_fpu_apu_op_multicycle : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff (`COVIF_CB.apu_busy == 1) + { + `FPU_OP_BINS + option.weight = 5; + } + + cp_is_mulh_ex : coverpoint cntxt.cov_vif.is_mulh_ex { + bins not_mulh = {1'b0}; + option.weight = 1; + } + + cp_is_misaligned_data_req_ex : coverpoint cntxt.cov_vif.is_misaligned_data_req_ex { + bins not_misaligned_data_req_ex = {1'b0}; + option.weight = 1; + } + + cp_is_post_inc_ld_st_inst_ex : coverpoint cntxt.cov_vif.is_post_inc_ld_st_inst_ex { + bins not_post_inc_ld_st_inst_ex = {1'b0}; + option.weight = 1; + } + + cp_ex_apu_valid_memorised : coverpoint cntxt.cov_vif.ex_apu_valid_memorised { + bins not_apu_valid_mem = {1'b0}; + option.weight = 1; + } + + // cross coverage for F-inst in ID-stage with preceeding F-multicycle instr + cr_f_inst_at_id_stage_inp_with_fpu_multicycle_req : cross cp_id_stage_f_inst, + cp_curr_fpu_apu_op_at_apu_req + {option.weight = 50;} + + // cross coverage for F-inst in ID-stage with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + cr_f_inst_at_id_stage_inp_while_fpu_busy : cross cp_id_stage_f_inst, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + // For FPU config with Latency=0 , apu_busy is expected to be set only for FDIV and FSQRT case + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at ID-stage input at various stages of APU latency + // clk-cycles of the ongoing/preceeding F-multicycle instr + cr_f_inst_at_id_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_f_inst, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + // cross coverage for F-inst at ID-stage output with preceeding F-multicycle instr + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_with_fpu_multicycle_req : cross cp_id_stage_apu_op_ex_o, + cp_curr_fpu_apu_op_at_apu_req + {option.weight = 50;} + + // cross coverage for F-inst at ID-stage output with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_while_fpu_busy : cross cp_id_stage_apu_op_ex_o, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at ID-stage output at various stages of APU latency + // clk-cycles of the ongoing/preceeding F-multicycle instr + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_apu_op_ex_o, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + // cross coverage for F-inst at IF-stage with preceeding F-multicycle instr + cr_f_inst_at_if_stage_inp_with_fpu_multicycle_req : cross cp_if_stage_f_inst, + cp_curr_fpu_apu_op_at_apu_req + {option.weight = 50;} + + // cross coverage for F-inst at IF-stage with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + cr_f_inst_at_if_stage_inp_while_fpu_busy : cross cp_if_stage_f_inst, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at IF-stage output at various stages of + // APU latency clk-cycles of the ongoing/preceeding F-multicycle instr + cr_f_inst_at_if_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_if_stage_f_inst, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + endgroup : cg_f_multicycle + + + covergroup cg_f_inst_reg(int fpu_latency); + `per_instance_fcov + + cp_apu_req_valid : coverpoint `COVIF_CB.apu_req { + bins apu_req_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_grant_valid : coverpoint `COVIF_CB.apu_gnt { + bins apu_gnt_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_busy : coverpoint `COVIF_CB.apu_busy { + bins apu_busy_high = {1'b1}; + option.weight = 1; + } + + cp_id_inst_valid : coverpoint `COVIF_CB.id_stage_instr_valid_i { + bins id_stage_instr_valid = {1}; + option.weight = 1; + } + + cp_apu_rvalid : coverpoint `COVIF_CB.apu_rvalid_i { + bins apu_rvalid = {1}; + option.weight = 1; + } + + cp_apu_contention : coverpoint `COVIF_CB.apu_perf_wb_o { + bins no_contention = {0}; + bins has_contention = {1}; + option.weight = 1; + } + + cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { + `FPU_OP_BINS + option.weight = 5; + } + + cp_last_fpu_apu_op_at_contention : coverpoint cntxt.cov_vif.o_last_fpu_apu_op_if { + bins curr_apu_op_fmadd = {APU_OP_FMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fnmsub = {APU_OP_FNMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fadd = {APU_OP_FADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmul = {APU_OP_FMUL} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fdiv = {APU_OP_FDIV} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsqrt = {APU_OP_FSQRT} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsgnj = {APU_OP_FSGNJ} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fminmax = {APU_OP_FMINMAX} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fcmp = {APU_OP_FCMP} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fclassify = {APU_OP_FCLASSIFY} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2f = {APU_OP_F2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2i = {APU_OP_F2I} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_i2f = {APU_OP_I2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmsub = {APU_OP_FMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fnmadd = {APU_OP_FNMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsub = {APU_OP_FSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsgnj_se = {APU_OP_FSGNJ_SE} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2i_u = {APU_OP_F2I_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_i2f_u = {APU_OP_I2F_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + option.weight = 5; + } + + // TODO: need to add another cover point for F-inst at ID-EX boundary ? + cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i { + `RV32F_INSTR_BINS + option.weight = 5; + } + + // TODO: to add rv32c coverage + cp_id_stage_non_rv32fc_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i[6:0] { + `CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC + option.weight = 5; + } + + cp_id_f_inst_fs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] { + bins fs1[] = {[0:31]}; + option.weight = 1; + } + cp_id_f_inst_fs2 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[24:20] { + bins fs2[] = {[0:31]}; + option.weight = 1; + } + cp_curr_fpu_inst_fd : coverpoint cntxt.cov_vif.curr_fpu_fd { + bins fd[] = {[0:31]}; + option.weight = 1; + } + cp_curr_fpu_inst_rd : coverpoint cntxt.cov_vif.curr_fpu_rd { + bins rd[] = {[0:31]}; + option.weight = 1; + } + cp_id_x_inst_rs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] { + bins rs1[] = {[0:31]}; + option.weight = 1; + } + cp_apu_alu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_ex_regfile_wr_contention { + bins rd[] = {[0:31]} with ( ((item + 1) * (fpu_latency != 1)) != 0 ); + illegal_bins rd_addr_32_63 = {[32:63]} with ( ((item + 1) * (fpu_latency != 1)) != 0 ); + option.weight = 1; + } + cp_lsu_apu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_wb_regfile_wr_contention { + bins rd[] = {[0:31]} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + illegal_bins rd_addr_32_63 = {[32:63]} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + option.weight = 1; + } + cp_prev_rd_waddr_contention : coverpoint cntxt.cov_vif.prev_rd_waddr_contention { + bins rd[] = {[0:63]}; + option.weight = 1; + } + + cp_contention_state : coverpoint cntxt.cov_vif.contention_state { + bins no_contention = {0}; + bins contention_1st_cyc_done = {1}; + bins contention_2nd_cyc_done = {2}; + ignore_bins state3 = {3}; + option.weight = 1; + } + + cp_b2b_contention : coverpoint cntxt.cov_vif.b2b_contention { + bins b2b_contention_true = {1}; + option.weight = 5; + } + + cp_fd_fs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_fd) { + bins fd_fs1_equal = {1}; + } + cp_fd_fs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_fd) { + bins fd_fs2_equal = {1}; + } + cp_fd_fs3_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[31:27] == cntxt.cov_vif.curr_fpu_fd) { + bins fd_fs3_equal = {1}; + } + cp_rd_rs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_rd) { + bins rd_rs1_equal = {1}; + } + cp_rd_rs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_rd) { + bins rd_rs1_equal = {1}; + } + + //********************************************************************************************************* + // Cross Cov description for reg-to-reg dependency cases in instr sequence with F-multicycle instr + //********************************************************************************************************* + // This Cross Coverage captures the cases where latest APU execution's RD addr is same as + // rs1/rs2/rs3 of the next instruction in pipeline. + // Design is expected to stall EX in such scenarios until the previous instruction retires. + // The test scenarios are captured for correct RTL behavior, expecting EX stall in such cases. + // And for any conflicting design behaviour with EX proceeding without stalls, tests rely on Ref model + // to flag the resulting errors. + + //********************************************************************************************************* + // CASES WITH/WITHOUT CONTENTION AT THE TIME OF APU RESULT WRITE TO REGFILE + // WHERE APU WRITE WILL WIN (APU LATENCY = 0,2,3,4) + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with fd to fs1 dependency - case with APU latency > 0 + cr_fd_fs1_eq_nonzero_lat : cross cp_fd_fs1_eq, cp_id_inst_valid, + cp_id_stage_f_inst, cp_apu_busy, + cp_apu_rvalid, cp_curr_fpu_inst_fd, + cp_curr_fpu_apu_op, cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_NON_FD_F_INSTR + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + } + + // cross coverage for F-instr following F-instr with fd to fs2 dependency - case with APU latency > 0 + cr_fd_fs2_eq_nonzero_lat : cross cp_fd_fs2_eq, cp_id_inst_valid, + cp_id_stage_f_inst, cp_apu_busy, + cp_apu_rvalid, cp_curr_fpu_inst_fd, + cp_curr_fpu_apu_op, cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_NON_FD_F_INSTR + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + } + + // cross coverage for F-instr following F-instr with fd to fs3 dependency - case with APU latency > 0 + cr_fd_fs3_eq_nonzero_lat : cross cp_fd_fs3_eq, cp_id_inst_valid, + cp_id_stage_f_inst, cp_apu_busy, + cp_apu_rvalid, cp_curr_fpu_inst_fd, + cp_curr_fpu_apu_op, cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_NON_FD_F_INSTR + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_FS3_F_INSTR + } + + // cross coverage for F-instr following F-instr with rd to rs1 dependency - case with APU latency > 0 + cr_rd_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, cp_id_inst_valid, + cp_id_stage_f_inst, cp_apu_busy, + cp_apu_rvalid, cp_curr_fpu_inst_rd, + cp_curr_fpu_apu_op, cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS_F_INSTR_IN_ID + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency - case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, cp_id_inst_valid, + cp_id_stage_non_rv32fc_inst, + cp_apu_busy, cp_apu_rvalid, + cp_curr_fpu_inst_rd, cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + } + + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency - case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, cp_id_inst_valid, + cp_id_stage_non_rv32fc_inst, + cp_apu_busy, cp_apu_rvalid, + cp_curr_fpu_inst_rd, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + } + + // cross coverage for contention case 2nd cycle with ALU regfile write + cr_waddr_rd_apu_alu_ex_contention : cross cp_apu_alu_contention_wr_rd, + cp_contention_state, + cp_apu_contention { + bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention with ((cp_contention_state <= 3) & (fpu_latency != 1)); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NO_CONTENTION + } + + + //********************************************************************************************************* + // CASES WITH/WITHOUT CONTENTION AT APU RESULT WRITE TO REGFILE. APU_LATENCY=0 PRIOIRTY APU WRITE WINS + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with fd to fs1 dependency - 0 Latency + cr_fd_fs1_eq_no_lat : cross cp_fd_fs1_eq, cp_apu_req_valid, cp_id_stage_f_inst, + cp_apu_grant_valid, cp_apu_rvalid, cp_curr_fpu_inst_fd, + cp_curr_fpu_apu_op, cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_fd_fs1_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_FD_F_INSTR + } + + // cross coverage for F-instr following F-instr with fd to fs2 dependency - 0 Latency + cr_fd_fs2_eq_no_lat : cross cp_fd_fs2_eq, cp_apu_req_valid, cp_id_stage_f_inst, + cp_apu_grant_valid, cp_apu_rvalid, cp_curr_fpu_inst_fd, + cp_curr_fpu_apu_op, cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_fd_fs2_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_FD_F_INSTR + } + + // cross coverage for F-instr following F-instr with fd to fs3 dependency - 0 Latency + cr_fd_fs3_eq_no_lat : cross cp_fd_fs3_eq, cp_apu_req_valid, cp_id_stage_f_inst, + cp_apu_grant_valid, cp_apu_rvalid, cp_curr_fpu_inst_fd, + cp_curr_fpu_apu_op, cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_fd_fs3_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_FD_F_INSTR + `IGNORE_BINS_NON_FS3_F_INSTR + } + + // cross coverage for F-instr following F-instr with rd to rs1 dependency - 0 Latency + cr_rd_rs1_eq_no_lat : cross cp_rd_rs1_eq, cp_id_inst_valid, cp_id_stage_f_inst, + cp_apu_req_valid, cp_apu_grant_valid, cp_apu_rvalid, + cp_curr_fpu_inst_rd, cp_curr_fpu_apu_op, cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_rd_rs1_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS_F_INSTR_IN_ID + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency - 0 Latency + cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat : cross cp_rd_rs1_eq, cp_id_inst_valid, + cp_id_stage_non_rv32fc_inst, cp_apu_req_valid, + cp_apu_grant_valid, cp_apu_rvalid, + cp_curr_fpu_inst_rd, cp_curr_fpu_apu_op, + cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + } + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency - 0 Latency + cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat : cross cp_rd_rs2_eq, cp_id_inst_valid, + cp_id_stage_non_rv32fc_inst, + cp_apu_req_valid, cp_apu_grant_valid, + cp_apu_rvalid, cp_curr_fpu_inst_rd, + cp_curr_fpu_apu_op, cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RD_F_INSTR + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + } + + //********************************************************************************************************* + // CONTENTION DURING APU RESULT WRITE TO REGFILE WHERE APU RESULT WRITE STALLS. APU LATENCY = 1 + //********************************************************************************************************* + + // cp_apu_contention = 1 cases + // cp_contention_state = 1 indicates that there was contention in WB at LSU-APU regfile wr mux + + // cross coverage for F-instr following F-instr with fd to fs1 dependency + // case with APU latency = 1 and contention with LSU + cr_fd_fs1_eq_nonzero_lat_with_contention : cross cp_fd_fs1_eq, cp_id_inst_valid, + cp_id_stage_f_inst, cp_curr_fpu_inst_fd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_fd_fs1_eq_nonzero_lat_with_contention + with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with fd to fs2 dependency + // case with APU latency = 1 and contention with LSU + cr_fd_fs2_eq_nonzero_lat_with_contention : cross cp_fd_fs2_eq, cp_id_inst_valid, + cp_id_stage_f_inst, cp_curr_fpu_inst_fd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_fd_fs2_eq_nonzero_lat_with_contention + with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with fd to fs3 dependency + // case with APU latency = 1 and contention with LSU + cr_fd_fs3_eq_nonzero_lat_with_contention : cross cp_fd_fs3_eq, cp_id_inst_valid, + cp_id_stage_f_inst, cp_curr_fpu_inst_fd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_fd_fs3_eq_nonzero_lat_with_contention + with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_FS3_F_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with rd to rs1 dependency + // case with APU latency = 1 and contention with LSU + cr_rd_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, cp_id_inst_valid, + cp_id_stage_f_inst, cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_rd_rs1_eq_nonzero_lat_with_contention + with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + `IGNORE_BINS_NON_RD_F_INSTR_AT_CONTENTION + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency + // case with APU latency = 1 and contention with LSU + cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, cp_id_inst_valid, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention + with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + `IGNORE_BINS_NON_RD_F_INSTR_AT_CONTENTION + } + + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency + // case with APU latency = 1 and contention with LSU + cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention : cross cp_rd_rs2_eq, cp_id_inst_valid, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention + with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + `IGNORE_BINS_NON_RD_F_INSTR_AT_CONTENTION + } + + // TODO: does it require checking rd to rs1/rs2 equal in this case? + // cross coverage for contention case 1st cycle with LSU regfile write win + cr_waddr_rd_lsu_apu_wb_contention : cross cp_apu_busy, cp_apu_rvalid, + cp_lsu_apu_contention_wr_rd, + cp_apu_contention { + bins main_cr_bin = cr_waddr_rd_lsu_apu_wb_contention + with ( (cp_apu_rvalid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NO_CONTENTION_LSU + } + + endgroup : cg_f_inst_reg + +endclass : uvme_cv32e40p_fp_instr_covg + +function uvme_cv32e40p_fp_instr_covg::new(string name = "cv32e40p_fp_instr_covg", uvm_component parent = null); + super.new(name, parent); + void'(uvm_config_db#(uvme_cv32e40p_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("cv32e40p_fp_instr_covg", "Configuration handle is null") + end + + cg_f_multicycle = new(.fpu_latency(cfg.fpu_latency)); + cg_f_inst_reg = new(.fpu_latency(cfg.fpu_latency)); + +endfunction : new + +function void uvme_cv32e40p_fp_instr_covg::build_phase(uvm_phase phase); + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cv32e40p_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("cv32e40p_fp_instr_covg", "No cntxt object passed to model"); + end +endfunction : build_phase + +task uvme_cv32e40p_fp_instr_covg::run_phase(uvm_phase phase); + super.run_phase(phase); + `uvm_info("cv32e40p_fp_instr_covg", "The RV32_F coverage model is running", UVM_LOW); + fork + sample_clk_i(); + join_none +endtask : run_phase + + +task uvme_cv32e40p_fp_instr_covg::sample_clk_i(); + while (1) begin + @(`COVIF_CB); + cg_f_multicycle.sample(); + cg_f_inst_reg.sample(); + end +endtask : sample_clk_i diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv new file mode 100644 index 0000000000..52a1c6395e --- /dev/null +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv @@ -0,0 +1,772 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright 2023 OpenHW Group +// Copyright 2023 Dolphin Design +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// +/////////////////////////////////////////////////////////////////////////////// + +class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; + /* + * Class members + */ + uvme_cv32e40p_cfg_c cfg; + uvme_cv32e40p_cntxt_c cntxt; + + `uvm_component_utils_begin(uvme_cv32e40p_zfinx_instr_covg) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + extern function new(string name = "cv32e40p_zfinx_instr_covg", uvm_component parent = null); + extern function void build_phase(uvm_phase phase); + extern task run_phase(uvm_phase phase); + extern task sample_clk_i(); + + `define FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND \ + (cp_is_mulh_ex == 0) & (cp_is_misaligned_data_req_ex == 0) & (cp_is_post_inc_ld_st_inst_ex == 0) & (cp_ex_apu_valid_memorised == 0) + + `define FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES \ + illegal_bins clk_2_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 0) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); \ + illegal_bins clk_3_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 1) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); \ + illegal_bins clk_4_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2, 3}) ) \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 2) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); + + `define FPU_ZERO_LATENCY_ILLEGAL_BUSY \ + illegal_bins apu_busy_curr_apu_op_not_div_sqrt = ( !binsof(cp_curr_fpu_apu_op_multicycle) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ + with ( ((cp_curr_fpu_apu_op_multicycle + 1) * (fpu_latency == 0)) != 0 ); + + `define IGNORE_BINS_ZERO_LAT_FPU_OP \ + ignore_bins zero_lat_inst = ( !binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ + with ( ((cp_curr_fpu_apu_op + 1) * (fpu_latency == 0)) != 0 ); + + `define IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU \ + ignore_bins in_contention_lsu_wr = ( binsof(cp_apu_contention) intersect {1} ) \ + with ( ((cp_curr_fpu_apu_op + 1) * (fpu_latency == 1)) != 0 ); + + `define IGNORE_BINS_NON_RS1_CV32E40P_INSTR \ + ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL}; + + `define IGNORE_BINS_NON_RS2_CV32E40P_INSTR \ + ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_INSTR_WITH_NO_RS2}; + + `define IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE \ + ignore_bins non_stalled_contention_wr_state = binsof(cp_contention_state) intersect {0,1}; + + `define IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR \ + ignore_bins contention_at_lsu_wr = binsof(cp_apu_contention) intersect {1}; + + `define IGNORE_BINS_NO_CONTENTION \ + ignore_bins no_contention = binsof(cp_apu_contention) intersect {1}; + + `define IGNORE_BINS_NON_RS3_ZFINX_INSTR \ + ignore_bins non_rs3_f_inst = !binsof(cp_id_stage_f_inst) intersect {`RV32F_INSTR_WITH_NO_FS3}; + + `define IGNORE_BINS_NO_CONTENTION_LSU \ + ignore_bins no_contention_lsu_wr = binsof(cp_apu_contention) intersect {0}; + + `define CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES \ + cp_is_mulh_ex, cp_is_misaligned_data_req_ex, cp_is_post_inc_ld_st_inst_ex, cp_ex_apu_valid_memorised + + /* + * Covergroups + */ + + covergroup cg_f_multicycle(int fpu_latency); + `per_instance_fcov + option.at_least = 10; + + cp_if_stage_f_inst : coverpoint `COVIF_CB.if_stage_instr_rdata_i iff (`COVIF_CB.if_stage_instr_rvalid_i == 1) { + `ZFINX_INSTR_BINS + option.weight = 5; + } + + cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + `ZFINX_INSTR_BINS + option.weight = 5; + } + + cp_id_stage_apu_op_ex_o : coverpoint `COVIF_CB.id_stage_apu_op_ex_o iff (`COVIF_CB.id_stage_apu_en_ex_o == 1) { + `FPU_OP_BINS + option.weight = 5; + } + + cp_f_multicycle_clk_window : coverpoint cntxt.cov_vif.if_clk_cycle_window { + bins clk1 = {1}; + bins clk2 = {2}; + bins clk3 = {3}; + bins clk4 = {4}; + bins clk5 = {5}; + bins clk6 = {6}; + bins clk7 = {7}; + bins clk8 = {8}; + bins clk9 = {9}; + bins clk10 = {10}; + bins clk11 = {11}; + bins clk12 = {12}; + bins clk13 = {13}; + bins clk14 = {14}; + bins clk15 = {15}; + bins clk16 = {16}; + bins clk17 = {17}; + bins clk18 = {18}; + bins clk19 = {19}; + ignore_bins ignore_idle = {0}; + illegal_bins clk_more_than_19 = {[20:31]}; + } + + cp_id_stage_inst_valid : coverpoint `COVIF_CB.id_stage_instr_valid_i { + bins id_stage_instr_valid = {1}; + option.weight = 1; + } + + cp_if_stage_inst_valid : coverpoint `COVIF_CB.if_stage_instr_rvalid_i { + bins if_stage_instr_valid = {1}; + option.weight = 1; + } + + cp_id_stage_apu_en_ex_o : coverpoint `COVIF_CB.id_stage_apu_en_ex_o { + bins id_stage_apu_en_ex_1 = {1}; + bins id_stage_apu_en_ex_0_to_1 = (0 => 1); + option.weight = 1; + } + + cp_apu_req_valid : coverpoint `COVIF_CB.apu_req { + bins apu_req_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_grant_valid : coverpoint `COVIF_CB.apu_gnt { + bins apu_gnt_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_busy : coverpoint `COVIF_CB.apu_busy { + bins apu_busy_high = {1'b1}; + option.weight = 1; + } + + cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { + `FPU_OP_BINS + option.weight = 5; + } + + cp_curr_fpu_apu_op_at_apu_req : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) ) + { + `FPU_OP_BINS + option.weight = 5; + } + + cp_curr_fpu_apu_op_multicycle : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if iff (`COVIF_CB.apu_busy == 1) + { + `FPU_OP_BINS + option.weight = 5; + } + + cp_is_mulh_ex : coverpoint cntxt.cov_vif.is_mulh_ex { + bins not_mulh = {1'b0}; + option.weight = 1; + } + + cp_is_misaligned_data_req_ex : coverpoint cntxt.cov_vif.is_misaligned_data_req_ex { + bins not_misaligned_data_req_ex = {1'b0}; + option.weight = 1; + } + + cp_is_post_inc_ld_st_inst_ex : coverpoint cntxt.cov_vif.is_post_inc_ld_st_inst_ex { + bins not_post_inc_ld_st_inst_ex = {1'b0}; + option.weight = 1; + } + + cp_ex_apu_valid_memorised : coverpoint cntxt.cov_vif.ex_apu_valid_memorised { + bins not_apu_valid_mem = {1'b0}; + option.weight = 1; + } + + // cross coverage for F-inst in ID-stage with preceeding F-multicycle instr + cr_f_inst_at_id_stage_inp_with_fpu_multicycle_req : cross cp_id_stage_f_inst, + cp_curr_fpu_apu_op_at_apu_req + {option.weight = 50;} + + // cross coverage for F-inst in ID-stage with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + cr_f_inst_at_id_stage_inp_while_fpu_busy : cross cp_id_stage_f_inst, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + // For FPU config with Latency=0 , apu_busy is expected to be set only for FDIV and FSQRT case + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at ID-stage input at various stages of APU latency + // clk-cycles of the ongoing/preceeding F-multicycle instr + cr_f_inst_at_id_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_f_inst, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + // cross coverage for F-inst at ID-stage output with preceeding F-multicycle instr + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_with_fpu_multicycle_req : cross cp_id_stage_apu_op_ex_o, + cp_curr_fpu_apu_op_at_apu_req + {option.weight = 50;} + + // cross coverage for F-inst at ID-stage output with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_while_fpu_busy : cross cp_id_stage_apu_op_ex_o, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at ID-stage output at various stages of APU latency + // clk-cycles of the ongoing/preceeding F-multicycle instr + // Note: Added 2 separate similar cross coverages ID stage because of different + // arrival times of next instruction w.r.t APU Req + cr_f_inst_at_id_stage_out_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_apu_op_ex_o, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + // cross coverage for F-inst at IF-stage with preceeding F-multicycle instr + cr_f_inst_at_if_stage_inp_with_fpu_multicycle_req : cross cp_if_stage_f_inst, + cp_curr_fpu_apu_op_at_apu_req + {option.weight = 50;} + + // cross coverage for F-inst at IF-stage with preceeding F-multicycle + // case with apu_busy or APU needing more than 1 clock cycle + cr_f_inst_at_if_stage_inp_while_fpu_busy : cross cp_if_stage_f_inst, + cp_curr_fpu_apu_op_multicycle { + option.weight = 50; + `FPU_ZERO_LATENCY_ILLEGAL_BUSY + } + + // cross coverage for F-inst arriving at IF-stage output at various stages of + // APU latency clk-cycles of the ongoing/preceeding F-multicycle instr + cr_f_inst_at_if_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_if_stage_f_inst, + cp_f_multicycle_clk_window, + cp_curr_fpu_apu_op, + `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + + option.weight = 50; + `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES + } + + endgroup : cg_f_multicycle + + + covergroup cg_zfinx_inst_reg(int fpu_latency); + `per_instance_fcov + + cp_apu_req_valid : coverpoint `COVIF_CB.apu_req { + bins apu_req_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_grant_valid : coverpoint `COVIF_CB.apu_gnt { + bins apu_gnt_valid = {1'b1}; + option.weight = 1; + } + + cp_apu_busy : coverpoint `COVIF_CB.apu_busy { + bins apu_busy_high = {1'b1}; + option.weight = 1; + } + + cp_apu_rvalid : coverpoint `COVIF_CB.apu_rvalid_i { + bins apu_rvalid = {1}; + option.weight = 1; + } + + cp_apu_contention : coverpoint `COVIF_CB.apu_perf_wb_o { + bins no_contention = {0}; + bins has_contention = {1}; + option.weight = 1; + } + + cp_curr_fpu_apu_op : coverpoint cntxt.cov_vif.o_curr_fpu_apu_op_if { + `FPU_OP_BINS + option.weight = 5; + } + + cp_last_fpu_apu_op_at_contention : coverpoint cntxt.cov_vif.o_last_fpu_apu_op_if { + bins curr_apu_op_fmadd = {APU_OP_FMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fnmsub = {APU_OP_FNMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fadd = {APU_OP_FADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmul = {APU_OP_FMUL} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fdiv = {APU_OP_FDIV} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsqrt = {APU_OP_FSQRT} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsgnj = {APU_OP_FSGNJ} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fminmax = {APU_OP_FMINMAX} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fcmp = {APU_OP_FCMP} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fclassify = {APU_OP_FCLASSIFY} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2f = {APU_OP_F2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2i = {APU_OP_F2I} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_i2f = {APU_OP_I2F} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fmsub = {APU_OP_FMSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fnmadd = {APU_OP_FNMADD} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsub = {APU_OP_FSUB} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_fsgnj_se = {APU_OP_FSGNJ_SE} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_f2i_u = {APU_OP_F2I_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + bins curr_apu_op_i2f_u = {APU_OP_I2F_U} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); + option.weight = 5; + } + + // TODO: need to add another cover point for F-inst at ID-EX boundary ? + cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + `ZFINX_INSTR_BINS + option.weight = 5; + } + + // TODO: to add rv32c coverage + cp_id_stage_non_rv32fc_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i[6:0] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + `CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC + option.weight = 5; + } + + cp_id_f_inst_fs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins fs1[] = {[0:31]}; + option.weight = 1; + } + cp_id_f_inst_fs2 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[24:20] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins fs2[] = {[0:31]}; + option.weight = 1; + } + cp_curr_fpu_inst_fd : coverpoint cntxt.cov_vif.curr_fpu_fd { + bins fd[] = {[0:31]}; + option.weight = 1; + } + cp_curr_fpu_inst_rd : coverpoint cntxt.cov_vif.curr_fpu_rd { + bins rd[] = {[0:31]}; + option.weight = 1; + } + cp_curr_fpu_inst_rd_for_0_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd + iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins rd[] = {[0:31]}; + option.weight = 1; + } + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd + iff ( (`COVIF_CB.apu_busy == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins rd[] = {[0:31]}; + option.weight = 1; + } + cp_id_x_inst_rs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + + bins rs1[] = {[0:31]}; + option.weight = 1; + } + + cp_apu_alu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_ex_regfile_wr_contention { + bins rd[] = {[0:31]} with ( (item < 32) & (fpu_latency != 1) ); + illegal_bins rd_addr_32_63 = {[32:63]}; + option.weight = 1; + } + cp_lsu_apu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_wb_regfile_wr_contention { + bins rd[] = {[0:31]} with ( (item < 32) & (fpu_latency == 1) ); + illegal_bins rd_addr_32_63 = {[32:63]}; + option.weight = 1; + } + cp_prev_rd_waddr_contention : coverpoint cntxt.cov_vif.prev_rd_waddr_contention { + bins rd[] = {[0:31]}; + illegal_bins rd_addr_32_63 = {[32:63]}; //for zfinx only 32 gprs available + option.weight = 1; + } + + cp_contention_state : coverpoint cntxt.cov_vif.contention_state { + bins no_contention = {0}; + bins contention_1st_cyc_done = {1}; + bins contention_2nd_cyc_done = {2}; + ignore_bins state3 = {3}; + option.weight = 1; + } + + cp_b2b_contention : coverpoint cntxt.cov_vif.b2b_contention { + bins b2b_contention_true = {1}; + option.weight = 5; + } + + cp_rd_rs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins rd_rs1_equal = {1}; + } + cp_rd_rs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins rd_rs2_equal = {1}; + } + cp_rd_rs3_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[31:27] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + + bins rd_rs3_equal = {1}; + } + cp_contention_rd_rd_eq : coverpoint (cntxt.cov_vif.curr_rd_at_ex_regfile_wr_contention == cntxt.cov_vif.prev_rd_waddr_contention) { + bins contention_rd_rd_equal = {1} with ( (item == 1) & (fpu_latency != 1) ); + } + cp_contention_rd_rd_eq_fpu_lat_1 : coverpoint (cntxt.cov_vif.curr_fpu_rd == cntxt.cov_vif.prev_rd_waddr_contention) { + bins contention_rd_rd_equal = {1} with ( (item == 1) & (fpu_latency == 1) ); + } + + //********************************************************************************************************* + // Cross Cov description for reg-to-reg dependency cases in instr sequence with F-multicycle instr + //********************************************************************************************************* + + //********************************************************************************************************* + // CASES WITH/WITHOUT CONTENTION AT THE TIME OF APU RESULT WRITE TO REGFILE + // WHERE APU WRITE WILL WIN (APU LATENCY = 0,2,3,4) + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with rd to rs1 dependency + // case with APU latency > 0 + cr_rd_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + } + + // cross coverage for F-instr following F-instr with rd to rs2 dependency + // case with APU latency > 0 + cr_rd_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + } + + // cross coverage for F-instr following F-instr with rd to rs3 dependency + // case with APU latency > 0 + cr_rd_rs3_eq_nonzero_lat : cross cp_rd_rs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RS3_ZFINX_INSTR + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency + // case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + } + + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency + // case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + `IGNORE_BINS_ZERO_LAT_FPU_OP + `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + } + + // cross coverage for contention case 2nd cycle with ALU regfile write + cr_waddr_rd_apu_alu_ex_contention : cross cp_apu_alu_contention_wr_rd, + cp_contention_state, + cp_apu_contention { + + bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention + with ( (cp_contention_state <= 3) & (fpu_latency != 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NO_CONTENTION + } + + // cross coverage for RD-RD equal for both contention instructions + cr_contention_rd_rd_eq : cross cp_contention_rd_rd_eq, + cp_contention_state, + cp_apu_contention { + + bins main_cr_bin = cr_contention_rd_rd_eq + with ( (cp_contention_state <= 3) & (fpu_latency != 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NO_CONTENTION + } + + // cross coverage for RD-RD equal for both contention instructions for + // fpu_laterncy=1 + cr_contention_rd_rd_eq_fpu_lat_1 : cross cp_contention_rd_rd_eq_fpu_lat_1, + cp_contention_state, + cp_apu_contention { + + bins main_cr_bin = cr_contention_rd_rd_eq_fpu_lat_1 + with ( (cp_contention_state <= 3) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_NO_CONTENTION + } + + //********************************************************************************************************* + // CASES WITH/WITHOUT CONTENTION AT APU RESULT WRITE TO REGFILE. APU_LATENCY=0 PRIOIRTY APU WRITE WINS + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with rd to rs1 dependency - 0 Latency + cr_rd_rs1_eq_no_lat : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs1_eq_no_lat with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 0) ); + } + + // cross coverage for F-instr following F-instr with rd to rs2 dependency - 0 Latency + cr_rd_rs2_eq_no_lat : cross cp_rd_rs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs2_eq_no_lat with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 0) ); + } + + // cross coverage for F-instr following F-instr with rd to rs3 dependency - 0 Latency + cr_rd_rs3_eq_no_lat : cross cp_rd_rs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs3_eq_no_lat with ( (cp_rd_rs3_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RS3_ZFINX_INSTR + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency - 0 Latency + cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + } + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency - 0 Latency + cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat : cross cp_rd_rs2_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 0) ); + + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + } + + //********************************************************************************************************* + // CONTENTION DURING APU RESULT WRITE TO REGFILE WHERE APU RESULT WRITE STALLS. APU LATENCY = 1 + //********************************************************************************************************* + + // cross coverage for F-instr following F-instr with rd to rs1 dependency + // case with APU latency = 1 and contention with LSU + cr_rd_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs1_eq_nonzero_lat_with_contention + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with rd to rs2 dependency + // case with APU latency = 1 and contention with LSU + cr_rd_rs2_eq_nonzero_lat_with_contention : cross cp_rd_rs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs2_eq_nonzero_lat_with_contention + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for F-instr following F-instr with rd to rs3 dependency + // case with APU latency = 1 and contention with LSU + cr_rd_rs3_eq_nonzero_lat_with_contention : cross cp_rd_rs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rd_rs3_eq_nonzero_lat_with_contention + with ( (cp_rd_rs3_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency + // case with APU latency = 1 and contention with LSU + cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_RS1_CV32E40P_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency + // case with APU latency = 1 and contention with LSU + cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention : cross cp_rd_rs2_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd, + cp_last_fpu_apu_op_at_contention, + cp_contention_state, + cp_apu_contention { + + option.weight = 50; + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NON_RS2_CV32E40P_INSTR + `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE + `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR + } + + // TODO: does it require checking rd to rs1/rs2 equal in this case? + // cross coverage for contention case 1st cycle with LSU regfile write win + cr_waddr_rd_lsu_apu_wb_contention : cross cp_apu_busy, + cp_apu_rvalid, + cp_lsu_apu_contention_wr_rd, + cp_apu_contention { + + bins main_cr_bin = cr_waddr_rd_lsu_apu_wb_contention + with ( (cp_apu_rvalid == 1) & (fpu_latency == 1) ); + + `IGNORE_BINS_NO_CONTENTION_LSU + } + endgroup : cg_zfinx_inst_reg + +endclass : uvme_cv32e40p_zfinx_instr_covg + +function uvme_cv32e40p_zfinx_instr_covg::new(string name = "cv32e40p_zfinx_instr_covg", uvm_component parent = null); + super.new(name, parent); + void'(uvm_config_db#(uvme_cv32e40p_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("cv32e40p_zfinx_instr_covg", "Configuration handle is null") + end + + cg_f_multicycle = new(.fpu_latency(cfg.fpu_latency)); + cg_zfinx_inst_reg = new(.fpu_latency(cfg.fpu_latency)); + +endfunction : new + +function void uvme_cv32e40p_zfinx_instr_covg::build_phase(uvm_phase phase); + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cv32e40p_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("cv32e40p_zfinx_instr_covg", "No cntxt object passed to model"); + end +endfunction : build_phase + +task uvme_cv32e40p_zfinx_instr_covg::run_phase(uvm_phase phase); + super.run_phase(phase); + `uvm_info("cv32e40p_zfinx_instr_covg", "The RV32ZFINX coverage model is running", UVM_LOW); + fork + sample_clk_i(); + join_none +endtask : run_phase + +task uvme_cv32e40p_zfinx_instr_covg::sample_clk_i(); + while (1) begin + @(`COVIF_CB); + cg_f_multicycle.sample(); + cg_zfinx_inst_reg.sample(); + end +endtask : sample_clk_i diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv index ebc3294088..c4940e8678 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv @@ -22,5 +22,115 @@ `define UVME_CV32E40P_MEM_SIZE 22 +`define COVIF_CB cntxt.cov_vif.mon_cb + +`define APU_INSTR_WITH_NO_FD \ + APU_OP_FCMP, APU_OP_FCLASSIFY, APU_OP_F2I, APU_OP_F2I_U + +`define RV32F_INSTR_WITH_NO_FS3 \ + TB_INS_FMADD,TB_INS_FMSUB,TB_INS_FNMSUB,TB_INS_FNMADD + +`define RV32_INSTR_WITH_NO_RS2 \ + TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM + +`define RV32F_INSTR_BINS \ + wildcard bins fadd = {TB_INS_FADD}; \ + wildcard bins fsub = {TB_INS_FSUB}; \ + wildcard bins fmul = {TB_INS_FMUL}; \ + wildcard bins fdiv = {TB_INS_FDIV}; \ + wildcard bins fsqrt = {TB_INS_FSQRT}; \ + wildcard bins fsgnjs = {TB_INS_FSGNJS}; \ + wildcard bins fsgnjns = {TB_INS_FSGNJNS}; \ + wildcard bins fsgnjxs = {TB_INS_FSGNJXS}; \ + wildcard bins fmin = {TB_INS_FMIN}; \ + wildcard bins fmax = {TB_INS_FMAX}; \ + wildcard bins fcvtws = {TB_INS_FCVTWS}; \ + wildcard bins fcvtwus = {TB_INS_FCVTWUS}; \ + wildcard bins fmvxs = {TB_INS_FMVXS}; \ + wildcard bins feqs = {TB_INS_FEQS}; \ + wildcard bins flts = {TB_INS_FLTS}; \ + wildcard bins fles = {TB_INS_FLES}; \ + wildcard bins fclass = {TB_INS_FCLASS}; \ + wildcard bins fcvtsw = {TB_INS_FCVTSW}; \ + wildcard bins fcvtswu = {TB_INS_FCVTSWU}; \ + wildcard bins fmvsw = {TB_INS_FMVSX}; \ + wildcard bins fmadd = {TB_INS_FMADD}; \ + wildcard bins fmsub = {TB_INS_FMSUB}; \ + wildcard bins fnmsub = {TB_INS_FNMSUB}; \ + wildcard bins fnmadd = {TB_INS_FNMADD}; \ + wildcard bins flw = {TB_INS_FLW}; \ + wildcard bins fsw = {TB_INS_FSW}; + +`define ZFINX_INSTR_BINS \ + wildcard bins fadd = {TB_INS_FADD}; \ + wildcard bins fsub = {TB_INS_FSUB}; \ + wildcard bins fmul = {TB_INS_FMUL}; \ + wildcard bins fdiv = {TB_INS_FDIV}; \ + wildcard bins fsqrt = {TB_INS_FSQRT}; \ + wildcard bins fsgnjs = {TB_INS_FSGNJS}; \ + wildcard bins fsgnjns = {TB_INS_FSGNJNS}; \ + wildcard bins fsgnjxs = {TB_INS_FSGNJXS}; \ + wildcard bins fmin = {TB_INS_FMIN}; \ + wildcard bins fmax = {TB_INS_FMAX}; \ + wildcard bins fcvtws = {TB_INS_FCVTWS}; \ + wildcard bins fcvtwus = {TB_INS_FCVTWUS}; \ + wildcard bins fmvxs = {TB_INS_FMVXS}; \ + wildcard bins feqs = {TB_INS_FEQS}; \ + wildcard bins flts = {TB_INS_FLTS}; \ + wildcard bins fles = {TB_INS_FLES}; \ + wildcard bins fclass = {TB_INS_FCLASS}; \ + wildcard bins fcvtsw = {TB_INS_FCVTSW}; \ + wildcard bins fcvtswu = {TB_INS_FCVTSWU}; \ + wildcard bins fmvsw = {TB_INS_FMVSX}; \ + wildcard bins fmadd = {TB_INS_FMADD}; \ + wildcard bins fmsub = {TB_INS_FMSUB}; \ + wildcard bins fnmsub = {TB_INS_FNMSUB}; \ + wildcard bins fnmadd = {TB_INS_FNMADD}; + +`define FPU_OP_BINS \ + bins apu_op_fmadd = {APU_OP_FMADD}; \ + bins apu_op_fnmsub = {APU_OP_FNMSUB}; \ + bins apu_op_fadd = {APU_OP_FADD}; \ + bins apu_op_fmul = {APU_OP_FMUL}; \ + bins apu_op_fdiv = {APU_OP_FDIV}; \ + bins apu_op_fsqrt = {APU_OP_FSQRT}; \ + bins apu_op_fsgnj = {APU_OP_FSGNJ}; \ + bins apu_op_fminmax = {APU_OP_FMINMAX}; \ + bins apu_op_fcmp = {APU_OP_FCMP}; \ + bins apu_op_fclassify = {APU_OP_FCLASSIFY}; \ + bins apu_op_f2f = {APU_OP_F2F}; \ + bins apu_op_f2i = {APU_OP_F2I}; \ + bins apu_op_i2f = {APU_OP_I2F}; \ + bins apu_op_fmsub = {APU_OP_FMSUB}; \ + bins apu_op_fnmadd = {APU_OP_FNMADD}; \ + bins apu_op_fsub = {APU_OP_FSUB}; \ + bins apu_op_fsgnj_se = {APU_OP_FSGNJ_SE}; \ + bins apu_op_f2i_u = {APU_OP_F2I_U}; \ + bins apu_op_i2f_u = {APU_OP_I2F_U}; + +`define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC \ + bins system_opcode = {TB_OPCODE_SYSTEM}; \ + bins fence_opcode = {TB_OPCODE_FENCE}; \ + bins op_opcode = {TB_OPCODE_OP}; \ + bins opimm_opcode = {TB_OPCODE_OPIMM}; \ + bins store_opcode = {TB_OPCODE_STORE}; \ + bins load_opcode = {TB_OPCODE_LOAD}; \ + bins branch_opcode = {TB_OPCODE_BRANCH}; \ + bins jalr_opcode = {TB_OPCODE_JALR}; \ + bins jal_opcode = {TB_OPCODE_JAL}; \ + bins auipc_opcode = {TB_OPCODE_AUIPC}; \ + bins lui_opcode = {TB_OPCODE_LUI}; \ + bins fpu_fp_opcode = {TB_OPCODE_OP_FP}; \ + bins fpu_fmadd_opcode = {TB_OPCODE_OP_FMADD}; \ + bins fpu_fnmadd_opcode = {TB_OPCODE_OP_FNMADD}; \ + bins fpu_fmsub_opcode = {TB_OPCODE_OP_FMSUB}; \ + bins fpu_fnmsub_opcode = {TB_OPCODE_OP_FNMSUB}; \ + bins fpu_str_opcode = {TB_OPCODE_STORE_FP}; \ + bins fpu_ld_opcode = {TB_OPCODE_LOAD_FP}; \ + bins xpulp_custom_0 = {OPCODE_CUSTOM_0}; \ + bins xpulp_custom_1 = {OPCODE_CUSTOM_1}; \ + bins xpulp_custom_2 = {OPCODE_CUSTOM_2}; \ + bins xpulp_custom_3 = {OPCODE_CUSTOM_3}; + `endif // __UVME_CV32E40P_MACROS_SV__ diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv index baa1c59f5c..5bca471003 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv @@ -88,6 +88,8 @@ package uvme_cv32e40p_pkg; `include "uvme_interrupt_covg.sv" `include "uvme_debug_covg.sv" `include "uvme_rv32isa_covg.sv" + `include "uvme_cv32e40p_fp_instr_covg.sv" + `include "uvme_cv32e40p_zfinx_instr_covg.sv" `include "uvme_cv32e40p_cov_model.sv" `include "uvme_cv32e40p_sb.sv" `include "uvme_cv32e40p_vsqr.sv" From b5813284b3097896c73f3cfde31b75aafa1af5b0 Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 1 Dec 2023 13:05:31 +0800 Subject: [PATCH 05/97] Enhance coverage to capture locations within hwloop for specific events Signed-off-by: bsm --- .../env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 640 ++++++++++++++---- 1 file changed, 512 insertions(+), 128 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index c9844c1132..5da622bcd2 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -23,6 +23,7 @@ // 2) It uses uvmt_cv32e40p_rvvi_if // 3) Has covergroup for hwloops csr setup registers // 4) Has covergroup for hwloops features and events within hwloops such as exception, irq and debug entry (debug covers haltreq, trigger, ebreakm, step) +// 5) Improvement[Optional]: hwloop_stat_sub for handle (irq/debug) implementation `ifndef UVME_RV32X_HWLOOP_COVG `define UVME_RV32X_HWLOOP_COVG @@ -37,12 +38,18 @@ class uvme_rv32x_hwloop_covg # ( localparam CSR_LPSTART0_ADDR = 32'hCC0; localparam CSR_LPEND0_ADDR = 32'hCC1; localparam CSR_LPCOUNT0_ADDR = 32'hCC2; - localparam INSN_CEBREAK = 32'h00009002; // compress ebreak localparam INSN_ILLEGAL = 32'hFFFFFFFF; // user-defined for any illegal insn that leads to illegal exception localparam INSN_EBREAKM = 32'hFFFFFFFE; // user-defined - typedef enum bit [1:0] {NULL_TYPE=0, SINGLE, NESTED} hwloop_type_t; - typedef enum bit [1:0] {NULL_SETUP=0, SHORT, LONG} hwloop_setup_t; + typedef enum bit [1:0] {NULL_TYPE=0, SINGLE, NESTED} hwloop_type_t; + typedef enum bit [1:0] {NULL_SETUP=0, SHORT, LONG} hwloop_setup_t; + typedef enum int {EXCP_EBREAK=0, EXCP_ECALL, EXCP_ILLEGAL, + IS_IRQ, DBG_HALTREQ, DBG_EBREAKM, DBG_TRIG, + DBG_STEP, MC_INSN, TOTAL_EVENT=9} hwloop_evt_t; + typedef enum int {LOC_LPSTART=0, LOC_LPSTART_P4, + LOC_LPEND, LOC_LPEND_M4, + LOC_OTHERS, TOTAL_LOC=5} hwloop_evt_loc_t; + typedef struct { bit [31:0] lp_start [HWLOOP_NB]; bit [31:0] lp_end [HWLOOP_NB]; @@ -52,36 +59,57 @@ class uvme_rv32x_hwloop_covg # ( bit lp_count_wb [HWLOOP_NB]; } s_csr_hwloop; typedef struct { - hwloop_type_t hwloop_type; - hwloop_setup_t hwloop_setup [HWLOOP_NB]; - s_csr_hwloop hwloop_csr; - bit sample_hwloop_csr_done [HWLOOP_NB]; - bit execute_instr_in_hwloop [HWLOOP_NB]; - int track_lp_count [HWLOOP_NB]; + hwloop_type_t hwloop_type; + hwloop_setup_t hwloop_setup [HWLOOP_NB]; + s_csr_hwloop hwloop_csr; + bit sample_hwloop_csr_done [HWLOOP_NB]; + bit execute_instr_in_hwloop [HWLOOP_NB]; + int track_lp_cnt [HWLOOP_NB]; + int unsigned dbg_haltreq_cnt [HWLOOP_NB]; + int unsigned dbg_ebreakm_cnt [HWLOOP_NB]; + int unsigned dbg_trigger_cnt [HWLOOP_NB]; + int unsigned dbg_step_cnt [HWLOOP_NB]; + int unsigned excp_ebreak_cnt [HWLOOP_NB]; + int unsigned excp_ecall_cnt [HWLOOP_NB]; + int unsigned excp_illegal_cnt [HWLOOP_NB]; } s_hwloop_stat; + typedef struct { + bit en_cov_irq ; + bit en_cov_dbg_haltreq ; + bit en_cov_dbg_ebreakm ; + bit en_cov_dbg_trigger ; + bit en_cov_dbg_step_cnt ; + bit en_cov_dbg_step_cnt_loc ; + bit en_cov_excp_ebreak ; + bit en_cov_excp_ecall ; + bit en_cov_excp_illegal ; + bit en_cov_mc_insn ; + bit en_cov_insn ; + bit en_cov_event_loc ; + } s_hwloop_cov; // PROPERTIES - START - local s_csr_hwloop csr_hwloop_init = '{default:0}; - local s_hwloop_stat hwloop_stat_init = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; `define DEF_LOCAL_VARS(TYPE) \ - local s_csr_hwloop csr_hwloop_``TYPE = '{default:0}; \ - local s_hwloop_stat hwloop_stat_``TYPE = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; \ + local s_csr_hwloop csr_hwloop_``TYPE = '{default:0}; \ + local s_hwloop_stat hwloop_stat_``TYPE = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; \ + local logic [31:0] prev_pc_rdata_``TYPE = '{default:0}; \ + local hwloop_evt_loc_t hwloop_evt_loc_``TYPE [HWLOOP_NB][hwloop_evt_t][$]; \ local bit [(ILEN-1):0] insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ + local bit [(ILEN-1):0] mc_insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ local bit [31:0] irq_vect_``TYPE [HWLOOP_NB][$]; \ - local bit debug_req_``TYPE [HWLOOP_NB] = '{default:0}; \ - local bit dbg_trigger_``TYPE [HWLOOP_NB] = '{default:0}; \ - local int unsigned dbg_step_cnt_``TYPE [HWLOOP_NB] = '{default:0}; \ - local bit done_insn_list_capture_``TYPE [HWLOOP_NB] = '{default:0}; + local bit done_insn_list_capture_``TYPE [HWLOOP_NB] = '{default:0}; \ + local s_hwloop_cov hwloop_cov_``TYPE [HWLOOP_NB] = '{default:0}; `DEF_LOCAL_VARS(main) `DEF_LOCAL_VARS(sub) + `DEF_LOCAL_VARS(init) virtual uvmt_cv32e40p_rvvi_if #( .XLEN(XLEN), .ILEN(ILEN)) cv32e40p_rvvi_vif; string _header = "XPULPV2_HWLOOP_COV"; bit en_cvg_sampling = 1; - bit in_nested_loop0 = 0; - bit is_ebreak = 0, is_ebreakm, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0; + bit in_nested_loop0 = 0, in_nested_loop0_d1 = 0; + bit is_ebreak = 0, is_ebreakm = 0, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0, is_mc_insn = 0;; bit enter_hwloop_sub = 0; dcsr_cause_t dcsr_cause; @@ -137,7 +165,7 @@ class uvme_rv32x_hwloop_covg # ( `define CG_FEATURES_OF_HWLOOP(LOOP_IDX) cg_features_of_hwloop_``LOOP_IDX`` `define DEF_CG_FEATURES_OF_HWLOOP(LOOP_IDX) covergroup cg_features_of_hwloop_``LOOP_IDX with function \ - sample(s_hwloop_stat hwloop_stat, bit [31:0] insn, bit [31:0] irq, bit dbg_haltreq, bit dbg_trigger, int unsigned dbg_step_cnt); \ + sample(int lp_idx, s_hwloop_stat hwloop_stat, s_hwloop_cov hwloop_cov, bit [31:0] insn=32'b0, bit [31:0] irq=32'b0, hwloop_evt_loc_t evt_loc=TOTAL_LOC); \ option.per_instance = 1; \ `ifdef MODEL_TECH \ option.get_inst_coverage = 1; \ @@ -153,7 +181,7 @@ class uvme_rv32x_hwloop_covg # ( bins long_hwloop_setup = {LONG}; \ illegal_bins invalid = default; \ } \ - cp_hwloop_irq : coverpoint (irq) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + cp_hwloop_irq : coverpoint (irq) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_irq) { \ // priority order (high->low) : irq[31]...irq[16], irq[11], irq[3], irq[7] \ bins vec_irq_1hot_priority[] = {32'h0000_0008, \ 32'h0000_0080, \ @@ -163,20 +191,79 @@ class uvme_rv32x_hwloop_covg # ( 32'h0100_0000, 32'h0200_0000, 32'h0400_0000, 32'h0800_0000, \ 32'h1000_0000, 32'h2000_0000, 32'h4000_0000, 32'h8000_0000}; \ } \ - cp_hwloop_dbg_haltreq : coverpoint (dbg_haltreq) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ - bins dbg_haltreq = {1}; \ + cp_hwloop_dbg_haltreq : coverpoint (hwloop_stat.dbg_haltreq_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_haltreq) { \ + bins dbg_haltreq = {[1:$]}; \ + } \ + cp_hwloop_dbg_ebreakm : coverpoint (hwloop_stat.dbg_ebreakm_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_ebreakm) { \ + bins dbg_ebreakm = {[1:$]}; \ + } \ + cp_hwloop_dbg_trigger : coverpoint (hwloop_stat.dbg_trigger_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_trigger) { \ + bins dbg_trigger = {[1:$]}; \ + } \ + cp_hwloop_dbg_step_cnt : coverpoint (hwloop_stat.dbg_step_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_step_cnt) { \ + bins dbg_step_range_1 = {[1:4]}; \ + bins dbg_step_range_2 = {[5:20]}; \ + bins dbg_step_range_3 = {[20:50]}; \ + bins dbg_step_range_4 = {[51:$]}; \ + } \ + cp_hwloop_dbg_step_cnt_loc : coverpoint (hwloop_stat.dbg_step_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_dbg_step_cnt_loc) { \ + bins dbg_step_cnt_loc = {[1:$]}; \ + } \ + cp_hwloop_excp_ebreak : coverpoint (hwloop_stat.excp_ebreak_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_excp_ebreak) { \ + bins excp_ebreak = {[1:$]}; \ + } \ + cp_hwloop_excp_ecall : coverpoint (hwloop_stat.excp_ecall_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_excp_ecall) { \ + bins excp_ecall = {[1:$]}; \ + } \ + cp_hwloop_excp_illegal : coverpoint (hwloop_stat.excp_illegal_cnt[lp_idx]) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_excp_illegal) { \ + bins excp_illegal = {[1:$]}; \ } \ - cp_hwloop_dbg_trigger : coverpoint (dbg_trigger) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ - bins dbg_trigger = {1}; \ + cp_hwloop_mc_insn : coverpoint (insn) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_mc_insn) { \ + // RV32F \ + wildcard bins instr_fmadd = {INSTR_FMADD}; \ + wildcard bins instr_fmsub = {INSTR_FMSUB}; \ + wildcard bins instr_fnmsub = {INSTR_FNMSUB}; \ + wildcard bins instr_fnmadd = {INSTR_FNMADD}; \ + wildcard bins instr_fadd = {INSTR_FADD}; \ + wildcard bins instr_fsub = {INSTR_FSUB}; \ + wildcard bins instr_fmul = {INSTR_FMUL}; \ + wildcard bins instr_fdiv = {INSTR_FDIV}; \ + wildcard bins instr_fsqrt = {INSTR_FSQRT}; \ + wildcard bins instr_fsgnjs = {INSTR_FSGNJS}; \ + wildcard bins instr_fsgnjns = {INSTR_FSGNJNS}; \ + wildcard bins instr_fsgnjxs = {INSTR_FSGNJXS}; \ + wildcard bins instr_fmin = {INSTR_FMIN}; \ + wildcard bins instr_fmax = {INSTR_FMAX}; \ + wildcard bins instr_fcvtws = {INSTR_FCVTWS}; \ + wildcard bins instr_fcvtwus = {INSTR_FCVTWUS}; \ + wildcard bins instr_fmvxs = {INSTR_FMVXS}; \ + wildcard bins instr_feqs = {INSTR_FEQS}; \ + wildcard bins instr_flts = {INSTR_FLTS}; \ + wildcard bins instr_fles = {INSTR_FLES}; \ + wildcard bins instr_fclass = {INSTR_FCLASS}; \ + wildcard bins instr_fcvtsw = {INSTR_FCVTSW}; \ + wildcard bins instr_fcvtswu = {INSTR_FCVTSWU}; \ + wildcard bins instr_fmvsx = {INSTR_FMVSX}; \ + wildcard bins instr_flw = {INSTR_FLW}; \ + wildcard bins instr_fsw = {INSTR_FSW}; \ + // RV32M \ + wildcard bins instr_div = {INSTR_DIV}; \ + wildcard bins instr_divu = {INSTR_DIVU}; \ + wildcard bins instr_rem = {INSTR_REM}; \ + wildcard bins instr_remu = {INSTR_REMU}; \ + wildcard bins instr_pmuh = {INSTR_PMUH}; \ + wildcard bins instr_pmulhsu = {INSTR_PMULHSU}; \ + wildcard bins instr_pmulhu = {INSTR_PMULHU}; \ } \ - cp_hwloop_dbg_step_cnt : coverpoint (dbg_step_cnt) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ - bins dbg_step_range_1 = {[1:4]}; \ - bins dbg_step_range_2 = {[5:20]}; \ - bins dbg_step_range_3 = {[20:50]}; \ - bins dbg_step_range_4 = {[51:$]}; \ + cp_hwloop_loc : coverpoint (evt_loc) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_event_loc) { \ + bins loc_lpstart = {LOC_LPSTART}; \ + bins loc_lpstart_plus4 = {LOC_LPSTART_P4}; \ + bins loc_lpend = {LOC_LPEND}; \ + bins loc_lpend_minus4 = {LOC_LPEND_M4}; \ + bins loc_others = {LOC_OTHERS}; \ } \ // note: hwloop setup custom instructions are not allow in hwloop_0 (manual exclusion needed) \ - cp_insn_list_in_hwloop : coverpoint (insn) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``]) { \ + cp_insn_list_in_hwloop : coverpoint (insn) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_insn) { \ wildcard bins instr_lui = {INSTR_LUI}; \ wildcard bins instr_auipc = {INSTR_AUIPC}; \ // OPIMM \ @@ -604,20 +691,17 @@ class uvme_rv32x_hwloop_covg # ( // Others \ illegal_bins other_instr = default; \ } \ - ccp_hwloop_type_setup_insn_list : cross cp_hwloop_type, cp_hwloop_setup, cp_insn_list_in_hwloop; \ - ccp_hwloop_type_irq : cross cp_hwloop_type, cp_hwloop_irq; \ - ccp_hwloop_type_dbg_mode : cross cp_hwloop_type, cp_hwloop_dbg_haltreq; \ - ccp_hwloop_type_dbg_trigger : cross cp_hwloop_type, cp_hwloop_dbg_trigger; \ - ccp_hwloop_type_dbg_step_cnt : cross cp_hwloop_type, cp_hwloop_dbg_step_cnt { \ - bins ccp_single_dbg_step_range_1 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_1) && binsof (cp_hwloop_type.single_hwloop); \ - bins ccp_single_dbg_step_range_2 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_2) && binsof (cp_hwloop_type.single_hwloop); \ - bins ccp_single_dbg_step_range_3 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_3) && binsof (cp_hwloop_type.single_hwloop); \ - bins ccp_single_dbg_step_range_4 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_4) && binsof (cp_hwloop_type.single_hwloop); \ - bins ccp_nested_dbg_step_range_1 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_1) && binsof (cp_hwloop_type.nested_hwloop); \ - bins ccp_nested_dbg_step_range_2 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_2) && binsof (cp_hwloop_type.nested_hwloop); \ - bins ccp_nested_dbg_step_range_3 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_3) && binsof (cp_hwloop_type.nested_hwloop); \ - bins ccp_nested_dbg_step_range_4 = binsof (cp_hwloop_dbg_step_cnt.dbg_step_range_4) && binsof (cp_hwloop_type.nested_hwloop); \ - } /* todo: x with lpcount */ \ + ccp_hwloop_type_setup_insn_list : cross cp_hwloop_type, cp_hwloop_setup, cp_insn_list_in_hwloop; \ + ccp_hwloop_type_irq_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_irq; \ + ccp_hwloop_type_dbg_haltreq_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_dbg_haltreq; \ + ccp_hwloop_type_dbg_ebreakm_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_dbg_ebreakm; \ + ccp_hwloop_type_dbg_trigger_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_dbg_trigger; \ + ccp_hwloop_type_dbg_step_cnt : cross cp_hwloop_type, cp_hwloop_dbg_step_cnt; /* todo: x with lpcount */ \ + ccp_hwloop_type_dbg_step_cnt_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_dbg_step_cnt_loc; \ + ccp_hwloop_type_excp_ebreak_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_excp_ebreak; \ + ccp_hwloop_type_excp_ecall_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_excp_ecall; \ + ccp_hwloop_type_excp_illegal_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_excp_illegal; \ + ccp_hwloop_type_excp_mc_insn_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_mc_insn; \ endgroup : cg_features_of_hwloop_``LOOP_IDX`` `DEF_CG_CSR_HWLOOP(0) @@ -644,6 +728,91 @@ class uvme_rv32x_hwloop_covg # ( end endfunction : build_phase + + // conditions to collect location for different locations + `define CHECK_PC_EQUAL_LPSTART(IN1, IN2, IN3, IN4) is_pc_equal_lpstart(``IN1, ``IN2, ``IN3, ``IN4) + `define CHECK_PC_EQUAL_LPEND(IN1, IN2, IN3, IN4) is_pc_equal_lpend(``IN1, ``IN2, ``IN3, ``IN4) + `define CHECK_PC_WITHIN_LP(IN1, IN2, IN3) is_pc_within_lp(``IN1, ``IN2, ``IN3) + `define IF_CURRENT_IS_MAIN_HWLOOP(LOOP_IDX, EVT) \ + if (``LOOP_IDX`` == 0 || ``LOOP_IDX`` == 1) begin \ + bit temp_in_nested_loop0 = (``LOOP_IDX`` == 0) ? 0 : in_nested_loop0; \ + if (hwloop_stat_main.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_stat_main.track_lp_cnt[``LOOP_IDX``] >= 0 && !temp_in_nested_loop0) begin \ + unique case (``EVT``) \ + EXCP_EBREAK: begin \ + hwloop_stat_main.excp_ebreak_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_OTHERS); \ + end \ + EXCP_ECALL : begin \ + hwloop_stat_main.excp_ecall_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_OTHERS); \ + end \ + EXCP_ILLEGAL : begin \ + hwloop_stat_main.excp_illegal_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_OTHERS); \ + end \ + IS_IRQ : begin \ + is_irq = 1; irq_vect_main[``LOOP_IDX``].push_back(cv32e40p_rvvi_vif.irq_onehot_priority); \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_OTHERS); \ + end \ + DBG_HALTREQ : begin \ + is_dbg_mode = 1; hwloop_stat_main.dbg_haltreq_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_OTHERS); \ + end \ + DBG_TRIG : begin \ + is_dbg_mode = 1; hwloop_stat_main.dbg_trigger_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_OTHERS); \ + end \ + DBG_STEP : begin \ + is_dbg_mode = 1; hwloop_stat_main.dbg_step_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_OTHERS); \ + end \ + DBG_EBREAKM : begin \ + hwloop_stat_main.dbg_ebreakm_cnt[``LOOP_IDX``]++; \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][DBG_EBREAKM].push_back(LOC_OTHERS); \ + end \ + MC_INSN : begin \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_LPEND_M4); \ + else hwloop_evt_loc_main[``LOOP_IDX``][MC_INSN].push_back(LOC_OTHERS); \ + end \ + endcase \ + end \ + end + // task to sample cg_csr_hwloop `define CHECK_N_SAMPLE_CSR_HWLOOP(TYPE) check_n_sample_csr_hwloop_``TYPE``(); `define DEF_CHECK_N_SAMPLE_CSR_HWLOOP(TYPE) task check_n_sample_csr_hwloop_``TYPE``(); \ @@ -697,16 +866,17 @@ class uvme_rv32x_hwloop_covg # ( endtask : check_n_sample_csr_hwloop_``TYPE`` `DEF_CHECK_N_SAMPLE_CSR_HWLOOP(main) - `DEF_CHECK_N_SAMPLE_CSR_HWLOOP(sub) + // `DEF_CHECK_N_SAMPLE_CSR_HWLOOP(sub) // task to sample cg_features_of_hwloop + `define MC_INSN_OP_CODE {OPCODE_OP, OPCODE_OP_FP, OPCODE_OP_FMADD, OPCODE_OP_FNMADD, OPCODE_OP_FMSUB, OPCODE_OP_FNMSUB, OPCODE_LOAD_FP, OPCODE_STORE_FP} `define CHECK_N_SAMPLE_HWLOOP(TYPE) check_n_sample_hwloop_``TYPE``(); `define DEF_CHECK_N_SAMPLE_HWLOOP(TYPE) task check_n_sample_hwloop_``TYPE``(); \ for (int i=0; i= 0); \ + assert(hwloop_stat_``TYPE``.track_lp_cnt[i] >= 0); \ end \ end \ 1 : begin // in nested, skip when executing hwloop0 \ - if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_count[0] != 0) begin \ + in_nested_loop0_d1 = in_nested_loop0; \ + if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_cnt[0] != 0) begin \ in_nested_loop0 = 1; continue; \ end \ - else if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_count[0] == 0 && in_nested_loop0) begin \ + else if (hwloop_stat_``TYPE``.hwloop_type == NESTED && hwloop_stat_``TYPE``.track_lp_cnt[0] == 0 && in_nested_loop0) begin \ in_nested_loop0 = 0; continue; \ end \ if (!done_insn_list_capture_``TYPE``[i]) begin \ if (is_illegal) insn_list_in_hwloop_``TYPE``[i].push_back(INSN_ILLEGAL); \ else if (is_ebreakm) insn_list_in_hwloop_``TYPE``[i].push_back(INSN_EBREAKM); \ else insn_list_in_hwloop_``TYPE``[i].push_back(cv32e40p_rvvi_vif.insn); \ + if (cv32e40p_rvvi_vif.insn[6:0] inside `MC_INSN_OP_CODE) begin \ + if ((cv32e40p_rvvi_vif.insn[6:0] == OPCODE_OP && cv32e40p_rvvi_vif.insn[31:25] != 7'b0000001) || \ + (cv32e40p_rvvi_vif.insn[6:0] == OPCODE_OP && cv32e40p_rvvi_vif.insn[14:12] == 3'b000) \ + ) is_mc_insn = 0; \ + else begin \ + is_mc_insn = 1; mc_insn_list_in_hwloop_``TYPE``[i].push_back(cv32e40p_rvvi_vif.insn); \ + `IF_CURRENT_IS_MAIN_HWLOOP(i, MC_INSN) \ + end \ + end \ + else is_mc_insn = 0; \ + check_exception_entry(i); \ end \ else if (is_ebreakm) begin \ insn_list_in_hwloop_``TYPE``[i].push_back(INSN_EBREAKM); \ + check_exception_entry(i); \ end \ - if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i) && hwloop_stat_``TYPE``.track_lp_count[i] != 0) begin \ - hwloop_stat_``TYPE``.track_lp_count[i]--; \ + if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i, 0, cv32e40p_rvvi_vif.pc_rdata) && hwloop_stat_``TYPE``.track_lp_cnt[i] != 0) begin \ + hwloop_stat_``TYPE``.track_lp_cnt[i]--; \ done_insn_list_capture_``TYPE``[i] = 1; \ - assert(hwloop_stat_``TYPE``.track_lp_count[i] >= 0); \ + assert(hwloop_stat_``TYPE``.track_lp_cnt[i] >= 0); \ end \ end \ endcase \ end \ end // COLLECT_INSTR \ if ( \ - (hwloop_stat_``TYPE``.hwloop_type == NESTED && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_count[1] == 0) || \ - (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_count[1] == 0) || \ - (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[0] && hwloop_stat_``TYPE``.track_lp_count[0] == 0) \ + (hwloop_stat_``TYPE``.hwloop_type == NESTED && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_cnt[1] == 0) || \ + (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[1] && hwloop_stat_``TYPE``.track_lp_cnt[1] == 0) || \ + (hwloop_stat_``TYPE``.hwloop_type == SINGLE && done_insn_list_capture_``TYPE``[0] && hwloop_stat_``TYPE``.track_lp_cnt[0] == 0) \ ) begin : SAMPLE_END_OF_HWLOOPS \ for (int i=0; i 0) begin \ + `uvm_info(_header, $sformatf("DEBUG - FOR_CP_HWLOOP_DBG_STEP_CNT - LOOP_%0d - dbg_step_cnt %0d", i, hwloop_stat_``TYPE``.dbg_step_cnt[i]), UVM_DEBUG); \ + unique case (i) \ + 0: begin \ + `CG_FEATURES_OF_HWLOOP(0).sample(.lp_idx(i), .hwloop_stat(hwloop_stat_``TYPE``), .hwloop_cov(hwloop_cov_``TYPE``[i])); \ + end \ + 1: begin \ + `CG_FEATURES_OF_HWLOOP(1).sample(.lp_idx(i), .hwloop_stat(hwloop_stat_``TYPE``), .hwloop_cov(hwloop_cov_``TYPE``[i])); \ + end \ + endcase \ + end \ + hwloop_cov_``TYPE``[i].en_cov_dbg_step_cnt = 0; \ + // FOR_CP_HWLOOP_DBG_STEP_CNT_LOC \ + hwloop_cov_``TYPE``[i].en_cov_dbg_step_cnt_loc = 1; hwloop_cov_``TYPE``[i].en_cov_event_loc = 1; \ + for (int j=0; jdbg); currently commented out due to pending for implementation // `CHECK_N_SAMPLE_CSR_HWLOOP(sub); // `CHECK_N_SAMPLE_HWLOOP(sub); + check_exception_exit(); if (!(is_ebreak || is_ecall || is_illegal)) enter_hwloop_sub = 0; end else begin : MAIN - if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == INSTR_EBREAK) is_ebreakm = 1; if (is_irq && cv32e40p_rvvi_vif.insn[6:0] == OPCODE_JAL) begin wait (!is_irq); continue; end if (is_dbg_mode) begin wait (!is_dbg_mode); continue; end + if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == INSTR_EBREAK) is_ebreakm = 1; else is_ebreakm = 0; `CHECK_N_SAMPLE_CSR_HWLOOP(main); `CHECK_N_SAMPLE_HWLOOP(main); if (is_ebreak || is_ecall || is_illegal) enter_hwloop_sub = 1; + prev_pc_rdata_main = cv32e40p_rvvi_vif.pc_rdata; end end // VALID_DETECTED end // forever @@ -901,7 +1285,7 @@ class uvme_rv32x_hwloop_covg # ( function void final_phase(uvm_phase phase); super.final_phase(phase); - if (hwloop_stat_main == hwloop_stat_init && hwloop_stat_sub == hwloop_stat_init) begin + if (hwloop_stat_main == hwloop_stat_init) begin `uvm_info(_header, $sformatf("DEBUG - No prematured hwloops when test done"), UVM_DEBUG); end else begin @@ -909,18 +1293,18 @@ class uvme_rv32x_hwloop_covg # ( end endfunction : final_phase - function bit is_pc_equal_lpstart(s_csr_hwloop csr_hwloop, int idx=0); - if (cv32e40p_rvvi_vif.pc_rdata == csr_hwloop.lp_start[idx]) return 1; + function bit is_pc_equal_lpstart(s_csr_hwloop csr_hwloop, int csr_idx=0, int fwd_offset=0, logic [31:0] pc_rdata); + if (pc_rdata == csr_hwloop.lp_start[csr_idx]+(fwd_offset*4)) return 1; else return 0; endfunction: is_pc_equal_lpstart - function bit is_pc_equal_lpend(s_csr_hwloop csr_hwloop, int idx=0); - if (cv32e40p_rvvi_vif.pc_rdata == csr_hwloop.lp_end[idx]-4) return 1; + function bit is_pc_equal_lpend(s_csr_hwloop csr_hwloop, int csr_idx=0, int rvs_offset=0, logic [31:0] pc_rdata); + if (pc_rdata == csr_hwloop.lp_end[csr_idx]-4-(rvs_offset*4)) return 1; else return 0; endfunction: is_pc_equal_lpend - function bit is_pc_within_lp(s_csr_hwloop csr_hwloop, int idx=0); - if (cv32e40p_rvvi_vif.pc_rdata >= csr_hwloop.lp_start[idx] && cv32e40p_rvvi_vif.pc_rdata <= csr_hwloop.lp_end[idx]-4) return 1; + function bit is_pc_within_lp(s_csr_hwloop csr_hwloop, int csr_idx=0, logic [31:0] pc_rdata); + if (pc_rdata >= csr_hwloop.lp_start[csr_idx] && cv32e40p_rvvi_vif.pc_rdata <= csr_hwloop.lp_end[csr_idx]-4) return 1; else return 0; endfunction : is_pc_within_lp From ea125c36c8285ce489abb3288f41b20bfe4fe918 Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 1 Dec 2023 15:54:58 +0800 Subject: [PATCH 06/97] Update multicycle latency Signed-off-by: bsm --- .../instr_lib/cv32e40p_float_instr_lib.sv | 35 ++++++++++++++----- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index 77a1dea937..cfab603035 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -1172,7 +1172,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i FADD_S, FSUB_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end FMUL_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end FMIN_S, FMAX_S: begin mc_instr_latency = 1 + fpu_addmul_lat; end - FDIV_S, FSQRT_S: begin mc_instr_latency = $urandom_range(1,12); end // table 12.1 + FDIV_S, FSQRT_S: begin mc_instr_latency = $urandom_range(1,19); end // table 12.1 FSGNJ_S,FSGNJN_S, FSGNJX_S: begin mc_instr_latency = 1 + fpu_others_lat; end // table 12.1 FCVT_W_S, FCVT_WU_S: begin mc_instr_latency = 1 + fpu_others_lat; end FEQ_S, FLT_S, FLE_S: begin mc_instr_latency = 1 + fpu_others_lat; end @@ -1201,7 +1201,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i while (!(loop_cnt == 100) && rand_mc_latency > 0) begin int p_rand_mc_latency = rand_mc_latency; - bit skip = 0; + bit skip = 0, is_csr = 0; unique case ($urandom_range(0,1)) 0: begin : INSERT_INTEGER_COMPUTATION_INSTR rand_instr = new riscv_instr::get_rand_instr( @@ -1215,10 +1215,29 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i .include_instr(`RV32M_MULH_INSTR_LIST), .include_group({RV32M}) ); - if ((rand_mc_latency - 5) < 0) - skip = 1; - else - rand_mc_latency = rand_mc_latency - 5; // determistic + if ((rand_mc_latency - 5) < 0) skip = 1; + else rand_mc_latency = rand_mc_latency - 5; // determistic + end + 2: begin : INSERT_CSR_ACCCESS // exclude this option because csr access get stalled after mult apu insn + bit is_4mc = $urandom_range(1); + logic [11:0] addr_csr = (is_4mc) ? 12'h305 : 12'h340; // mtvec(4) : mscratch(1) + is_csr = 1; + rand_instr = new riscv_instr::get_rand_instr( + .include_instr({CSRRW}) + ); + rand_instr.set_rand_mode(); + rand_instr.csr_c.constraint_mode(0); + `DV_CHECK_RANDOMIZE_WITH_FATAL(rand_instr, + if (has_rs1) { + rs1 == local::gp_reg_scratch; + } + if (has_rd) { + rd == ZERO; + } + csr == local::addr_csr; + ) + if ((rand_mc_latency - 1 - is_4mc*3) < 0) skip = 1; + else rand_mc_latency = rand_mc_latency - 1 - is_4mc*3; end endcase if (!skip) begin @@ -1240,7 +1259,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i if (instr_f.has_rs2) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_f.rs2}); end if (instr_f.has_rd) begin reserved_rd = new[reserved_rd.size() + 1] ({reserved_rd, instr_f.rd}); end end - randomize_gpr(rand_instr); + if (!is_csr) randomize_gpr(rand_instr); instr_list.push_back(rand_instr); instr_list[$].comment = {instr_list[$].comment, $sformatf(" [rand_fill_mc_latency_w_instrs - %0d cycles] ", p_rand_mc_latency)}; reserved_rd.delete(); @@ -1851,7 +1870,7 @@ endclass: cv32e40p_fp_op_fwd_instr_w_loadstore_stream // // extended class that clce through all the fp instructions that change // fs state from Initial->Dirty and Clean->Dirty - // fixme: assess and consider the feedback in https://github.com/XavierAubert/core-v-verif/pull/70 + // todo: assess and consider the feedback in https://github.com/XavierAubert/core-v-verif/pull/70 - custom ctest class cv32e40p_mstatus_fs_stream extends cv32e40p_float_zfinx_base_instr_stream; localparam LOOP_CNT_LIMIT = 2; // init->dirty, clean->dirty From 4ccad4b56e9376e9789ee3926f7e1c5c9b094161 Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 1 Dec 2023 16:14:24 +0800 Subject: [PATCH 07/97] Update core-dv test for fp mstatus fs Signed-off-by: bsm --- .../instr_lib/cv32e40p_float_instr_lib.sv | 33 ++++++++-------- cv32e40p/regress/cv32e40pv2_fpu_instr.yaml | 10 ++--- .../corev_fp_mstatus_fs_test/corev-dv.yaml | 39 +++++++++++++++++++ .../corev_fp_mstatus_fs_test/test.yaml | 22 +++++++++++ .../corev-dv.yaml | 2 +- 5 files changed, 84 insertions(+), 22 deletions(-) create mode 100644 cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/corev-dv.yaml create mode 100644 cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/test.yaml diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index cfab603035..059ded8baa 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -1868,19 +1868,22 @@ endclass: cv32e40p_fp_op_fwd_instr_w_loadstore_stream // - // extended class that clce through all the fp instructions that change - // fs state from Initial->Dirty and Clean->Dirty - // todo: assess and consider the feedback in https://github.com/XavierAubert/core-v-verif/pull/70 - custom ctest + // extended class that cycle through all the fp instructions that change fs state from Initial->Dirty and Clean->Dirty + // note: + // 1) transistion only valid for F but not ZFINX extension (During ZFINX, FS always in OFF state) + // 2) this test is similar to custom fpu_mstatus_test but is generated by corev-dv and have certain constraint randomizations + // todo: assess and consider the feedback in https://github.com/XavierAubert/core-v-verif/pull/70 class cv32e40p_mstatus_fs_stream extends cv32e40p_float_zfinx_base_instr_stream; - localparam LOOP_CNT_LIMIT = 2; // init->dirty, clean->dirty + int unsigned loop_cnt_limit = (is_zfinx) ? 1 : 2; int unsigned loop_cnt = 0; + int unsigned total_instr = (is_zfinx) ? TOTAL_INSTR_ZFINX_TYPE : (TOTAL_INSTR_F_TYPE+TOTAL_INSTR_FC_TYPE); `uvm_object_utils(cv32e40p_mstatus_fs_stream) `uvm_object_new constraint ovr_c_others { - num_of_instr_per_stream == (TOTAL_INSTR_F_TYPE+TOTAL_INSTR_FC_TYPE) * LOOP_CNT_LIMIT; + num_of_instr_per_stream == total_instr * loop_cnt_limit; } function void pre_randomize(); @@ -1889,7 +1892,7 @@ class cv32e40p_mstatus_fs_stream extends cv32e40p_float_zfinx_base_instr_stream; use_no_repetitive_instr_per_stream = 1; include_load_store_base_sp = 1; clr_csr_option = 0; // uses CSRRW - en_clr_fstate = (!is_zfinx & en_clr_fflags_af_instr & !clr_csr_option); + en_clr_fstate = (en_clr_fflags_af_instr & !clr_csr_option); csr_mstatus_fs = 32'd1; // Initial endfunction: pre_randomize @@ -1900,21 +1903,19 @@ class cv32e40p_mstatus_fs_stream extends cv32e40p_float_zfinx_base_instr_stream; endfunction : initialize_regs virtual function void update_current_instr_arg_list(int idx=0); - include_group = new[2] ({RV32F, RV32FC}); + + if (!is_zfinx) include_group = new[2] ({RV32F, RV32FC}); + else include_group = new[2] ({RV32ZFINX, RV32FC}); + if (idx == 0) loop_cnt++; - else if (idx != 0 && idx%(TOTAL_INSTR_F_TYPE+TOTAL_INSTR_FC_TYPE) == 0) begin + else if (idx != 0 && idx%total_instr == 0) begin loop_cnt++; - assert (loop_cnt <= LOOP_CNT_LIMIT); + assert (loop_cnt <= loop_cnt_limit); exclude_instr.delete(); csr_mstatus_fs = 32'd2; // Clean + clr_csr_init_done = 0; // Update csrrw_val end - // fixme : refine after https://github.com/Imperas/private-dolphindesigns-riscv/issues/15 is resolved - case (idx) - 0: include_instr = new[1] ({FLW}); - 1: include_instr = new[1] ({C_FLW}); - 2: include_instr = new[1] ({C_FLWSP}); - default: include_instr.delete(); - endcase + endfunction: update_current_instr_arg_list virtual function void add_instr_prior_directed_instr(riscv_instr instr, int idx=0); diff --git a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml index 29971116e8..ef65b64231 100644 --- a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml @@ -34,11 +34,6 @@ tests: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_sanity_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" - num: 1 - skip_sim: - - pulp_fpu_zfinx - - pulp_fpu_zfinx_1cyclat - - pulp_fpu_zfinx_2cyclat corev_rand_fp_instr_test: build: uvmt_cv32e40p @@ -50,6 +45,11 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_w_special_ops_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + corev_fp_mstatus_fs_test: + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_fp_mstatus_fs_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + fpu_bugs_test: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt diff --git a/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/corev-dv.yaml new file mode 100644 index 0000000000..732c15ba62 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/corev-dv.yaml @@ -0,0 +1,39 @@ +# +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Test definition YAML for corev-dv test generator + +name: corev_fp_mstatus_fs_test +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated to test on mstatus fs +plusargs: > + +instr_cnt=1000 + +num_of_sub_program=0 + +test_override_riscv_instr_stream=1 + +no_branch_jump=1 + +directed_instr_0=cv32e40p_mstatus_fs_stream,1 + +# note: + # 1) example yaml template for fp test with f_extension + # 2) above setting running streams with rand instrs; +directed_instr_=, + # 3) runcmd: make gen_corev-dv test TEST=corev_sanity_fp_instr_test USE_ISS=no CFG=pulp_fpu CFG_PLUSARGS="+UVM_VERBOSITY=UVM_DEBUG" + # 4) [Must have plusarg] enable_floating_point for extension f + # 5) [Must have plusarg] test_override_riscv_instr_stream=1 + # - ==1: is to tune the streams not to overlap with other streams during streams placement + # 6) [recomendation] for single directed_instr_, try not to use apply too many streams else it might lead to placement issue + # 7) [recomendation] no branch/jump for non-directed streams + # 8) Must use together with test_cfg = floating_pt_instr_en OR floating_pt_zfinx_instr_en diff --git a/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/test.yaml new file mode 100644 index 0000000000..36bbf8dd57 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_fp_mstatus_fs_test/test.yaml @@ -0,0 +1,22 @@ +# +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Test definition YAML for generated corev arithmetic base test + +name: corev_fp_mstatus_fs_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Math test generated by corev-dv diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml index 34b73c2b94..ac245087aa 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_sanity_test/corev-dv.yaml @@ -33,7 +33,7 @@ plusargs: > +directed_instr_5=cv32e40p_constraint_mc_fp_instr_stream,1 +directed_instr_6=cv32e40p_fp_op_fwd_instr_stream,1 +directed_instr_7=cv32e40p_fp_op_fwd_instr_w_loadstore_stream,1 - +directed_instr_8=cv32e40p_mstatus_fs_stream,1 + # +directed_instr_8=cv32e40p_mstatus_fs_stream,1 # note: # 1) example yaml template for fp test with f_extension From 590d89729248f44074e474273d8e0f67c808b2e1 Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 1 Dec 2023 16:16:12 +0800 Subject: [PATCH 08/97] minor update Signed-off-by: bsm --- cv32e40p/regress/cv32e40pv2_fpu_instr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml index ef65b64231..5c385a26dd 100644 --- a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml @@ -49,6 +49,7 @@ tests: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_fp_mstatus_fs_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + num: 1 fpu_bugs_test: build: uvmt_cv32e40p From 03a57e18721e1e6e76f2e43eafff07e88e11924a Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 1 Dec 2023 17:34:01 +0800 Subject: [PATCH 09/97] F/Zfinx custom fcov update removing redundant cp, optimize crosses with more iff and minor improvement for code structure Signed-off-by: Vaibhav Jain --- .../uvme/cov/uvme_cv32e40p_fp_instr_covg.sv | 330 +++++++++++------- .../cov/uvme_cv32e40p_zfinx_instr_covg.sv | 92 +++-- cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 4 + 3 files changed, 251 insertions(+), 175 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv index 525d156f99..8692889f61 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv @@ -35,16 +35,13 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; extern task run_phase(uvm_phase phase); extern task sample_clk_i(); - `define FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND \ - (cp_is_mulh_ex == 0) & (cp_is_misaligned_data_req_ex == 0) & (cp_is_post_inc_ld_st_inst_ex == 0) & (cp_ex_apu_valid_memorised == 0) - `define FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES \ illegal_bins clk_2_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1}) ) \ - with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 0) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 0) ); \ illegal_bins clk_3_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2}) ) \ - with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 1) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 1) ); \ illegal_bins clk_4_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2, 3}) ) \ - with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 2) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 2) ); `define FPU_ZERO_LATENCY_ILLEGAL_BUSY \ illegal_bins apu_busy_curr_apu_op_not_div_sqrt = ( !binsof(cp_curr_fpu_apu_op_multicycle) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ @@ -94,9 +91,6 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `define IGNORE_BINS_NO_CONTENTION_LSU \ ignore_bins no_contention_lsu_wr = binsof(cp_apu_contention) intersect {0}; - `define CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES \ - cp_is_mulh_ex, cp_is_misaligned_data_req_ex, cp_is_post_inc_ld_st_inst_ex, cp_ex_apu_valid_memorised - /* * Covergroups */ @@ -120,7 +114,10 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; option.weight = 5; } - cp_f_multicycle_clk_window : coverpoint cntxt.cov_vif.if_clk_cycle_window { + cp_f_multicycle_clk_window : coverpoint cntxt.cov_vif.if_clk_cycle_window iff ((`COVIF_CB.is_mulh_ex == 0) && + (`COVIF_CB.is_misaligned_data_req_ex == 0) && + (`COVIF_CB.is_post_inc_ld_st_inst_ex == 0) && + (`COVIF_CB.ex_apu_valid_memorised == 0)) { bins clk1 = {1}; bins clk2 = {2}; bins clk3 = {3}; @@ -193,23 +190,12 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; option.weight = 5; } - cp_is_mulh_ex : coverpoint cntxt.cov_vif.is_mulh_ex { - bins not_mulh = {1'b0}; - option.weight = 1; - } + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall : coverpoint ((cntxt.cov_vif.is_mulh_ex == 0) && + (cntxt.cov_vif.is_misaligned_data_req_ex == 0) && + (cntxt.cov_vif.is_post_inc_ld_st_inst_ex == 0) && + (cntxt.cov_vif.ex_apu_valid_memorised == 0)) { - cp_is_misaligned_data_req_ex : coverpoint cntxt.cov_vif.is_misaligned_data_req_ex { - bins not_misaligned_data_req_ex = {1'b0}; - option.weight = 1; - } - - cp_is_post_inc_ld_st_inst_ex : coverpoint cntxt.cov_vif.is_post_inc_ld_st_inst_ex { - bins not_post_inc_ld_st_inst_ex = {1'b0}; - option.weight = 1; - } - - cp_ex_apu_valid_memorised : coverpoint cntxt.cov_vif.ex_apu_valid_memorised { - bins not_apu_valid_mem = {1'b0}; + bins no_alu_wr_stall = {1}; option.weight = 1; } @@ -232,7 +218,7 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cr_f_inst_at_id_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_f_inst, cp_f_multicycle_clk_window, cp_curr_fpu_apu_op, - `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { option.weight = 50; `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES } @@ -240,9 +226,9 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // cross coverage for F-inst at ID-stage output with preceeding F-multicycle instr // Note: Added 2 separate similar cross coverages ID stage because of different // arrival times of next instruction w.r.t APU Req - cr_f_inst_at_id_stage_out_with_fpu_multicycle_req : cross cp_id_stage_apu_op_ex_o, - cp_curr_fpu_apu_op_at_apu_req - {option.weight = 50;} + //cr_f_inst_at_id_stage_out_with_fpu_multicycle_req : cross cp_id_stage_apu_op_ex_o, + // cp_curr_fpu_apu_op_at_apu_req + //{option.weight = 50;} // cross coverage for F-inst at ID-stage output with preceeding F-multicycle // case with apu_busy or APU needing more than 1 clock cycle @@ -261,7 +247,7 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cr_f_inst_at_id_stage_out_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_apu_op_ex_o, cp_f_multicycle_clk_window, cp_curr_fpu_apu_op, - `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { option.weight = 50; `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES @@ -285,7 +271,7 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cr_f_inst_at_if_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_if_stage_f_inst, cp_f_multicycle_clk_window, cp_curr_fpu_apu_op, - `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { option.weight = 50; `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES @@ -312,11 +298,6 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; option.weight = 1; } - cp_id_inst_valid : coverpoint `COVIF_CB.id_stage_instr_valid_i { - bins id_stage_instr_valid = {1}; - option.weight = 1; - } - cp_apu_rvalid : coverpoint `COVIF_CB.apu_rvalid_i { bins apu_rvalid = {1}; option.weight = 1; @@ -357,47 +338,91 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; } // TODO: need to add another cover point for F-inst at ID-EX boundary ? - cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i { + cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + `RV32F_INSTR_BINS option.weight = 5; } // TODO: to add rv32c coverage - cp_id_stage_non_rv32fc_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i[6:0] { + cp_id_stage_non_rv32fc_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i[6:0] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + `CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC option.weight = 5; } - cp_id_f_inst_fs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] { + cp_id_f_inst_fs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + bins fs1[] = {[0:31]}; option.weight = 1; } - cp_id_f_inst_fs2 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[24:20] { + + cp_id_f_inst_fs2 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[24:20] + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + bins fs2[] = {[0:31]}; option.weight = 1; } + cp_curr_fpu_inst_fd : coverpoint cntxt.cov_vif.curr_fpu_fd { bins fd[] = {[0:31]}; option.weight = 1; } + + cp_curr_fpu_inst_fd_for_0_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_fd + iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins fd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_fd_for_multicyc_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_fd + iff ( (`COVIF_CB.apu_busy == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins fd[] = {[0:31]}; + option.weight = 1; + } + cp_curr_fpu_inst_rd : coverpoint cntxt.cov_vif.curr_fpu_rd { bins rd[] = {[0:31]}; option.weight = 1; } - cp_id_x_inst_rs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] { - bins rs1[] = {[0:31]}; + + cp_curr_fpu_inst_rd_for_0_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd + iff ( (`COVIF_CB.apu_req == 1) && + (`COVIF_CB.apu_gnt == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins rd[] = {[0:31]}; + option.weight = 1; + } + + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd + iff ( (`COVIF_CB.apu_busy == 1) && + (`COVIF_CB.apu_rvalid_i == 1) ) { + + bins rd[] = {[0:31]}; option.weight = 1; } + cp_apu_alu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_ex_regfile_wr_contention { bins rd[] = {[0:31]} with ( ((item + 1) * (fpu_latency != 1)) != 0 ); illegal_bins rd_addr_32_63 = {[32:63]} with ( ((item + 1) * (fpu_latency != 1)) != 0 ); option.weight = 1; } + cp_lsu_apu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_wb_regfile_wr_contention { bins rd[] = {[0:31]} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); illegal_bins rd_addr_32_63 = {[32:63]} with ( ((item + 1) * (fpu_latency == 1)) != 0 ); option.weight = 1; } + cp_prev_rd_waddr_contention : coverpoint cntxt.cov_vif.prev_rd_waddr_contention { bins rd[] = {[0:63]}; option.weight = 1; @@ -416,19 +441,33 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; option.weight = 5; } - cp_fd_fs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_fd) { + cp_fd_fs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_fd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + bins fd_fs1_equal = {1}; } - cp_fd_fs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_fd) { + + cp_fd_fs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_fd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + bins fd_fs2_equal = {1}; } - cp_fd_fs3_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[31:27] == cntxt.cov_vif.curr_fpu_fd) { + + cp_fd_fs3_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[31:27] == cntxt.cov_vif.curr_fpu_fd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + bins fd_fs3_equal = {1}; } - cp_rd_rs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_rd) { + + cp_rd_rs1_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[19:15] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + bins rd_rs1_equal = {1}; } - cp_rd_rs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_rd) { + + cp_rd_rs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_rd) + iff (`COVIF_CB.id_stage_instr_valid_i == 1) { + bins rd_rs1_equal = {1}; } @@ -447,11 +486,13 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // WHERE APU WRITE WILL WIN (APU LATENCY = 0,2,3,4) //********************************************************************************************************* - // cross coverage for F-instr following F-instr with fd to fs1 dependency - case with APU latency > 0 - cr_fd_fs1_eq_nonzero_lat : cross cp_fd_fs1_eq, cp_id_inst_valid, - cp_id_stage_f_inst, cp_apu_busy, - cp_apu_rvalid, cp_curr_fpu_inst_fd, - cp_curr_fpu_apu_op, cp_apu_contention { + // cross coverage for F-instr following F-instr with fd to fs1 dependency + // case with APU latency > 0 + cr_fd_fs1_eq_nonzero_lat : cross cp_fd_fs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { option.weight = 50; `IGNORE_BINS_NON_FD_F_INSTR @@ -459,11 +500,13 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU } - // cross coverage for F-instr following F-instr with fd to fs2 dependency - case with APU latency > 0 - cr_fd_fs2_eq_nonzero_lat : cross cp_fd_fs2_eq, cp_id_inst_valid, - cp_id_stage_f_inst, cp_apu_busy, - cp_apu_rvalid, cp_curr_fpu_inst_fd, - cp_curr_fpu_apu_op, cp_apu_contention { + // cross coverage for F-instr following F-instr with fd to fs2 dependency + // case with APU latency > 0 + cr_fd_fs2_eq_nonzero_lat : cross cp_fd_fs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { option.weight = 50; `IGNORE_BINS_NON_FD_F_INSTR @@ -471,11 +514,13 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `IGNORE_BINS_CONTENTION_IN_LSU_WITH_APU } - // cross coverage for F-instr following F-instr with fd to fs3 dependency - case with APU latency > 0 - cr_fd_fs3_eq_nonzero_lat : cross cp_fd_fs3_eq, cp_id_inst_valid, - cp_id_stage_f_inst, cp_apu_busy, - cp_apu_rvalid, cp_curr_fpu_inst_fd, - cp_curr_fpu_apu_op, cp_apu_contention { + // cross coverage for F-instr following F-instr with fd to fs3 dependency + // case with APU latency > 0 + cr_fd_fs3_eq_nonzero_lat : cross cp_fd_fs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { option.weight = 50; `IGNORE_BINS_NON_FD_F_INSTR @@ -484,11 +529,13 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `IGNORE_BINS_NON_FS3_F_INSTR } - // cross coverage for F-instr following F-instr with rd to rs1 dependency - case with APU latency > 0 - cr_rd_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, cp_id_inst_valid, - cp_id_stage_f_inst, cp_apu_busy, - cp_apu_rvalid, cp_curr_fpu_inst_rd, - cp_curr_fpu_apu_op, cp_apu_contention { + // cross coverage for F-instr following F-instr with rd to rs1 dependency + // case with APU latency > 0 + cr_rd_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { option.weight = 50; `IGNORE_BINS_ZERO_LAT_FPU_OP @@ -497,11 +544,12 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `IGNORE_BINS_NON_RS_F_INSTR_IN_ID } - // cross coverage for Non F-instr following F-instr with rd to rs1 dependency - case with APU latency > 0 - cr_rv32f_rd_non_rv32f_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, cp_id_inst_valid, + // cross coverage for Non F-instr following F-instr with rd to rs1 dependency + // case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, cp_id_stage_non_rv32fc_inst, - cp_apu_busy, cp_apu_rvalid, - cp_curr_fpu_inst_rd, cp_curr_fpu_apu_op, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, cp_apu_contention { option.weight = 50; @@ -511,11 +559,11 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `IGNORE_BINS_NON_RS1_CV32E40P_INSTR } - // cross coverage for Non F-instr following F-instr with rd to rs2 dependency - case with APU latency > 0 - cr_rv32f_rd_non_rv32f_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, cp_id_inst_valid, + // cross coverage for Non F-instr following F-instr with rd to rs2 dependency + // case with APU latency > 0 + cr_rv32f_rd_non_rv32f_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, cp_id_stage_non_rv32fc_inst, - cp_apu_busy, cp_apu_rvalid, - cp_curr_fpu_inst_rd, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, cp_curr_fpu_apu_op, cp_apu_contention { @@ -530,7 +578,9 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; cr_waddr_rd_apu_alu_ex_contention : cross cp_apu_alu_contention_wr_rd, cp_contention_state, cp_apu_contention { - bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention with ((cp_contention_state <= 3) & (fpu_latency != 1)); + + bins main_cr_bin = cr_waddr_rd_apu_alu_ex_contention + with ( (cp_contention_state <= 3) & (fpu_latency != 1) ); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NO_CONTENTION @@ -542,67 +592,83 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; //********************************************************************************************************* // cross coverage for F-instr following F-instr with fd to fs1 dependency - 0 Latency - cr_fd_fs1_eq_no_lat : cross cp_fd_fs1_eq, cp_apu_req_valid, cp_id_stage_f_inst, - cp_apu_grant_valid, cp_apu_rvalid, cp_curr_fpu_inst_fd, - cp_curr_fpu_apu_op, cp_apu_contention { + cr_fd_fs1_eq_no_lat : cross cp_fd_fs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + option.weight = 50; - bins main_cr_bin = cr_fd_fs1_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + bins main_cr_bin = cr_fd_fs1_eq_no_lat with ( (cp_fd_fs1_eq == 1) & (fpu_latency == 0) ); `IGNORE_BINS_NON_FD_F_INSTR } // cross coverage for F-instr following F-instr with fd to fs2 dependency - 0 Latency - cr_fd_fs2_eq_no_lat : cross cp_fd_fs2_eq, cp_apu_req_valid, cp_id_stage_f_inst, - cp_apu_grant_valid, cp_apu_rvalid, cp_curr_fpu_inst_fd, - cp_curr_fpu_apu_op, cp_apu_contention { + cr_fd_fs2_eq_no_lat : cross cp_fd_fs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + option.weight = 50; - bins main_cr_bin = cr_fd_fs2_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + bins main_cr_bin = cr_fd_fs2_eq_no_lat with ( (cp_fd_fs2_eq == 1) & (fpu_latency == 0) ); `IGNORE_BINS_NON_FD_F_INSTR } // cross coverage for F-instr following F-instr with fd to fs3 dependency - 0 Latency - cr_fd_fs3_eq_no_lat : cross cp_fd_fs3_eq, cp_apu_req_valid, cp_id_stage_f_inst, - cp_apu_grant_valid, cp_apu_rvalid, cp_curr_fpu_inst_fd, - cp_curr_fpu_apu_op, cp_apu_contention { + cr_fd_fs3_eq_no_lat : cross cp_fd_fs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + option.weight = 50; - bins main_cr_bin = cr_fd_fs3_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + bins main_cr_bin = cr_fd_fs3_eq_no_lat with ( (cp_fd_fs3_eq == 1) & (fpu_latency == 0) ); `IGNORE_BINS_NON_FD_F_INSTR `IGNORE_BINS_NON_FS3_F_INSTR } // cross coverage for F-instr following F-instr with rd to rs1 dependency - 0 Latency - cr_rd_rs1_eq_no_lat : cross cp_rd_rs1_eq, cp_id_inst_valid, cp_id_stage_f_inst, - cp_apu_req_valid, cp_apu_grant_valid, cp_apu_rvalid, - cp_curr_fpu_inst_rd, cp_curr_fpu_apu_op, cp_apu_contention { + cr_rd_rs1_eq_no_lat : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + option.weight = 50; - bins main_cr_bin = cr_rd_rs1_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + bins main_cr_bin = cr_rd_rs1_eq_no_lat with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 0) ); `IGNORE_BINS_NON_RD_F_INSTR `IGNORE_BINS_NON_RS_F_INSTR_IN_ID } // cross coverage for Non F-instr following F-instr with rd to rs1 dependency - 0 Latency - cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat : cross cp_rd_rs1_eq, cp_id_inst_valid, - cp_id_stage_non_rv32fc_inst, cp_apu_req_valid, - cp_apu_grant_valid, cp_apu_rvalid, - cp_curr_fpu_inst_rd, cp_curr_fpu_apu_op, + cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat : cross cp_rd_rs1_eq, + cp_id_stage_non_rv32fc_inst, + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, cp_apu_contention { + option.weight = 50; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_no_lat + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 0) ); `IGNORE_BINS_NON_RD_F_INSTR `IGNORE_BINS_NON_RS1_CV32E40P_INSTR } // cross coverage for Non F-instr following F-instr with rd to rs2 dependency - 0 Latency - cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat : cross cp_rd_rs2_eq, cp_id_inst_valid, + cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat : cross cp_rd_rs2_eq, cp_id_stage_non_rv32fc_inst, - cp_apu_req_valid, cp_apu_grant_valid, - cp_apu_rvalid, cp_curr_fpu_inst_rd, - cp_curr_fpu_apu_op, cp_apu_contention { + cp_curr_fpu_inst_rd_for_0_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { + option.weight = 50; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat with ( (cp_apu_rvalid == 1) & (fpu_latency == 0) ); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 0) ); `IGNORE_BINS_NON_RD_F_INSTR `IGNORE_BINS_NON_RS2_CV32E40P_INSTR @@ -617,13 +683,16 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // cross coverage for F-instr following F-instr with fd to fs1 dependency // case with APU latency = 1 and contention with LSU - cr_fd_fs1_eq_nonzero_lat_with_contention : cross cp_fd_fs1_eq, cp_id_inst_valid, - cp_id_stage_f_inst, cp_curr_fpu_inst_fd, + cr_fd_fs1_eq_nonzero_lat_with_contention : cross cp_fd_fs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd, cp_last_fpu_apu_op_at_contention, - cp_contention_state, cp_apu_contention { + cp_contention_state, + cp_apu_contention { + option.weight = 50; bins main_cr_bin = cr_fd_fs1_eq_nonzero_lat_with_contention - with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + with ( (cp_fd_fs1_eq == 1) & (fpu_latency == 1) ); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION @@ -632,13 +701,16 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // cross coverage for F-instr following F-instr with fd to fs2 dependency // case with APU latency = 1 and contention with LSU - cr_fd_fs2_eq_nonzero_lat_with_contention : cross cp_fd_fs2_eq, cp_id_inst_valid, - cp_id_stage_f_inst, cp_curr_fpu_inst_fd, + cr_fd_fs2_eq_nonzero_lat_with_contention : cross cp_fd_fs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd, cp_last_fpu_apu_op_at_contention, - cp_contention_state, cp_apu_contention { + cp_contention_state, + cp_apu_contention { + option.weight = 50; bins main_cr_bin = cr_fd_fs2_eq_nonzero_lat_with_contention - with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + with ( (cp_fd_fs2_eq == 1) & (fpu_latency == 1) ); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_NON_FD_F_INSTR_AT_CONTENTION @@ -647,13 +719,16 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // cross coverage for F-instr following F-instr with fd to fs3 dependency // case with APU latency = 1 and contention with LSU - cr_fd_fs3_eq_nonzero_lat_with_contention : cross cp_fd_fs3_eq, cp_id_inst_valid, - cp_id_stage_f_inst, cp_curr_fpu_inst_fd, + cr_fd_fs3_eq_nonzero_lat_with_contention : cross cp_fd_fs3_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_fd, cp_last_fpu_apu_op_at_contention, - cp_contention_state, cp_apu_contention { + cp_contention_state, + cp_apu_contention { + option.weight = 50; bins main_cr_bin = cr_fd_fs3_eq_nonzero_lat_with_contention - with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + with ( (cp_fd_fs3_eq == 1) & (fpu_latency == 1) ); `IGNORE_BINS_NON_FS3_F_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE @@ -663,13 +738,16 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // cross coverage for F-instr following F-instr with rd to rs1 dependency // case with APU latency = 1 and contention with LSU - cr_rd_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, cp_id_inst_valid, - cp_id_stage_f_inst, cp_curr_fpu_inst_rd, + cr_rd_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd, cp_last_fpu_apu_op_at_contention, - cp_contention_state, cp_apu_contention { + cp_contention_state, + cp_apu_contention { + option.weight = 50; bins main_cr_bin = cr_rd_rs1_eq_nonzero_lat_with_contention - with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 1) ); `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE `IGNORE_BINS_CONTENTION_AT_LSU_REGFILE_WR @@ -678,15 +756,16 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // cross coverage for Non F-instr following F-instr with rd to rs1 dependency // case with APU latency = 1 and contention with LSU - cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, cp_id_inst_valid, + cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention : cross cp_rd_rs1_eq, cp_id_stage_non_rv32fc_inst, cp_curr_fpu_inst_rd, cp_last_fpu_apu_op_at_contention, cp_contention_state, cp_apu_contention { + option.weight = 50; bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs1_eq_nonzero_lat_with_contention - with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + with ( (cp_rd_rs1_eq == 1) & (fpu_latency == 1) ); `IGNORE_BINS_NON_RS1_CV32E40P_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE @@ -696,15 +775,16 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // cross coverage for Non F-instr following F-instr with rd to rs2 dependency // case with APU latency = 1 and contention with LSU - cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention : cross cp_rd_rs2_eq, cp_id_inst_valid, + cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention : cross cp_rd_rs2_eq, cp_id_stage_non_rv32fc_inst, cp_curr_fpu_inst_rd, cp_last_fpu_apu_op_at_contention, cp_contention_state, cp_apu_contention { + option.weight = 50; bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_nonzero_lat_with_contention - with ( (cp_id_inst_valid == 1) & (fpu_latency == 1) ); + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 1) ); `IGNORE_BINS_NON_RS2_CV32E40P_INSTR `IGNORE_BINS_NON_STALLED_CONTENTION_WR_STATE @@ -714,9 +794,11 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; // TODO: does it require checking rd to rs1/rs2 equal in this case? // cross coverage for contention case 1st cycle with LSU regfile write win - cr_waddr_rd_lsu_apu_wb_contention : cross cp_apu_busy, cp_apu_rvalid, + cr_waddr_rd_lsu_apu_wb_contention : cross cp_apu_busy, + cp_apu_rvalid, cp_lsu_apu_contention_wr_rd, cp_apu_contention { + bins main_cr_bin = cr_waddr_rd_lsu_apu_wb_contention with ( (cp_apu_rvalid == 1) & (fpu_latency == 1) ); diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv index 52a1c6395e..4d2c43739e 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv @@ -35,16 +35,13 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; extern task run_phase(uvm_phase phase); extern task sample_clk_i(); - `define FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND \ - (cp_is_mulh_ex == 0) & (cp_is_misaligned_data_req_ex == 0) & (cp_is_post_inc_ld_st_inst_ex == 0) & (cp_ex_apu_valid_memorised == 0) - `define FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES \ illegal_bins clk_2_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1}) ) \ - with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 0) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 0) ); \ illegal_bins clk_3_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2}) ) \ - with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 1) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); \ + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 1) ); \ illegal_bins clk_4_19_group_NON_DIVSQRT = ( (!binsof(cp_curr_fpu_apu_op) intersect {APU_OP_FDIV, APU_OP_FSQRT}) && (!binsof(cp_f_multicycle_clk_window) intersect {1, 2, 3}) ) \ - with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 2) & `FPU_LAT_0_2_EX_REGFILE_ALU_WR_NO_STALL_COND ); + with ( (cp_f_multicycle_clk_window != 0) & (fpu_latency == 2) ); `define FPU_ZERO_LATENCY_ILLEGAL_BUSY \ illegal_bins apu_busy_curr_apu_op_not_div_sqrt = ( !binsof(cp_curr_fpu_apu_op_multicycle) intersect {APU_OP_FDIV, APU_OP_FSQRT} ) \ @@ -79,9 +76,6 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; `define IGNORE_BINS_NO_CONTENTION_LSU \ ignore_bins no_contention_lsu_wr = binsof(cp_apu_contention) intersect {0}; - `define CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES \ - cp_is_mulh_ex, cp_is_misaligned_data_req_ex, cp_is_post_inc_ld_st_inst_ex, cp_ex_apu_valid_memorised - /* * Covergroups */ @@ -105,7 +99,10 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; option.weight = 5; } - cp_f_multicycle_clk_window : coverpoint cntxt.cov_vif.if_clk_cycle_window { + cp_f_multicycle_clk_window : coverpoint cntxt.cov_vif.if_clk_cycle_window iff ((`COVIF_CB.is_mulh_ex == 0) && + (`COVIF_CB.is_misaligned_data_req_ex == 0) && + (`COVIF_CB.is_post_inc_ld_st_inst_ex == 0) && + (`COVIF_CB.ex_apu_valid_memorised == 0)) { bins clk1 = {1}; bins clk2 = {2}; bins clk3 = {3}; @@ -178,23 +175,12 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; option.weight = 5; } - cp_is_mulh_ex : coverpoint cntxt.cov_vif.is_mulh_ex { - bins not_mulh = {1'b0}; - option.weight = 1; - } - - cp_is_misaligned_data_req_ex : coverpoint cntxt.cov_vif.is_misaligned_data_req_ex { - bins not_misaligned_data_req_ex = {1'b0}; - option.weight = 1; - } - - cp_is_post_inc_ld_st_inst_ex : coverpoint cntxt.cov_vif.is_post_inc_ld_st_inst_ex { - bins not_post_inc_ld_st_inst_ex = {1'b0}; - option.weight = 1; - } + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall : coverpoint ((cntxt.cov_vif.is_mulh_ex == 0) && + (cntxt.cov_vif.is_misaligned_data_req_ex == 0) && + (cntxt.cov_vif.is_post_inc_ld_st_inst_ex == 0) && + (cntxt.cov_vif.ex_apu_valid_memorised == 0)) { - cp_ex_apu_valid_memorised : coverpoint cntxt.cov_vif.ex_apu_valid_memorised { - bins not_apu_valid_mem = {1'b0}; + bins no_alu_wr_stall = {1}; option.weight = 1; } @@ -217,7 +203,7 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cr_f_inst_at_id_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_f_inst, cp_f_multicycle_clk_window, cp_curr_fpu_apu_op, - `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { option.weight = 50; `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES } @@ -225,9 +211,9 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; // cross coverage for F-inst at ID-stage output with preceeding F-multicycle instr // Note: Added 2 separate similar cross coverages ID stage because of different // arrival times of next instruction w.r.t APU Req - cr_f_inst_at_id_stage_out_with_fpu_multicycle_req : cross cp_id_stage_apu_op_ex_o, - cp_curr_fpu_apu_op_at_apu_req - {option.weight = 50;} + //cr_f_inst_at_id_stage_out_with_fpu_multicycle_req : cross cp_id_stage_apu_op_ex_o, + // cp_curr_fpu_apu_op_at_apu_req + //{option.weight = 50;} // cross coverage for F-inst at ID-stage output with preceeding F-multicycle // case with apu_busy or APU needing more than 1 clock cycle @@ -246,7 +232,7 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cr_f_inst_at_id_stage_out_with_cyc_window_of_ongoing_fpu_calc : cross cp_id_stage_apu_op_ex_o, cp_f_multicycle_clk_window, cp_curr_fpu_apu_op, - `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { option.weight = 50; `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES @@ -270,7 +256,7 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cr_f_inst_at_if_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_if_stage_f_inst, cp_f_multicycle_clk_window, cp_curr_fpu_apu_op, - `CP_FOR_USE_WITH_WITH_CONSTRUCT_EXCLUDING_SPECIAL_CASES { + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { option.weight = 50; `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES @@ -358,20 +344,24 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; bins fs1[] = {[0:31]}; option.weight = 1; } + cp_id_f_inst_fs2 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[24:20] iff (`COVIF_CB.id_stage_instr_valid_i == 1) { bins fs2[] = {[0:31]}; option.weight = 1; } + cp_curr_fpu_inst_fd : coverpoint cntxt.cov_vif.curr_fpu_fd { bins fd[] = {[0:31]}; option.weight = 1; } + cp_curr_fpu_inst_rd : coverpoint cntxt.cov_vif.curr_fpu_rd { bins rd[] = {[0:31]}; option.weight = 1; } + cp_curr_fpu_inst_rd_for_0_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd iff ( (`COVIF_CB.apu_req == 1) && (`COVIF_CB.apu_gnt == 1) && @@ -380,6 +370,7 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; bins rd[] = {[0:31]}; option.weight = 1; } + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result : coverpoint cntxt.cov_vif.curr_fpu_rd iff ( (`COVIF_CB.apu_busy == 1) && (`COVIF_CB.apu_rvalid_i == 1) ) { @@ -387,24 +378,19 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; bins rd[] = {[0:31]}; option.weight = 1; } - cp_id_x_inst_rs1 : coverpoint `COVIF_CB.id_stage_instr_rdata_i[19:15] - iff (`COVIF_CB.id_stage_instr_valid_i == 1) { - - - bins rs1[] = {[0:31]}; - option.weight = 1; - } cp_apu_alu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_ex_regfile_wr_contention { bins rd[] = {[0:31]} with ( (item < 32) & (fpu_latency != 1) ); illegal_bins rd_addr_32_63 = {[32:63]}; option.weight = 1; } + cp_lsu_apu_contention_wr_rd : coverpoint cntxt.cov_vif.curr_rd_at_wb_regfile_wr_contention { bins rd[] = {[0:31]} with ( (item < 32) & (fpu_latency == 1) ); illegal_bins rd_addr_32_63 = {[32:63]}; option.weight = 1; } + cp_prev_rd_waddr_contention : coverpoint cntxt.cov_vif.prev_rd_waddr_contention { bins rd[] = {[0:31]}; illegal_bins rd_addr_32_63 = {[32:63]}; //for zfinx only 32 gprs available @@ -429,19 +415,23 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; bins rd_rs1_equal = {1}; } + cp_rd_rs2_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[24:20] == cntxt.cov_vif.curr_fpu_rd) iff (`COVIF_CB.id_stage_instr_valid_i == 1) { bins rd_rs2_equal = {1}; } + cp_rd_rs3_eq : coverpoint (`COVIF_CB.id_stage_instr_rdata_i[31:27] == cntxt.cov_vif.curr_fpu_rd) iff (`COVIF_CB.id_stage_instr_valid_i == 1) { bins rd_rs3_equal = {1}; } + cp_contention_rd_rd_eq : coverpoint (cntxt.cov_vif.curr_rd_at_ex_regfile_wr_contention == cntxt.cov_vif.prev_rd_waddr_contention) { bins contention_rd_rd_equal = {1} with ( (item == 1) & (fpu_latency != 1) ); } + cp_contention_rd_rd_eq_fpu_lat_1 : coverpoint (cntxt.cov_vif.curr_fpu_rd == cntxt.cov_vif.prev_rd_waddr_contention) { bins contention_rd_rd_equal = {1} with ( (item == 1) & (fpu_latency == 1) ); } @@ -457,11 +447,11 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; // cross coverage for F-instr following F-instr with rd to rs1 dependency // case with APU latency > 0 - cr_rd_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, - cp_id_stage_f_inst, - cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, - cp_curr_fpu_apu_op, - cp_apu_contention { + cr_rd_rs1_eq_nonzero_lat : cross cp_rd_rs1_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { option.weight = 50; `IGNORE_BINS_ZERO_LAT_FPU_OP @@ -470,11 +460,11 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; // cross coverage for F-instr following F-instr with rd to rs2 dependency // case with APU latency > 0 - cr_rd_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, - cp_id_stage_f_inst, - cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, - cp_curr_fpu_apu_op, - cp_apu_contention { + cr_rd_rs2_eq_nonzero_lat : cross cp_rd_rs2_eq, + cp_id_stage_f_inst, + cp_curr_fpu_inst_rd_for_multicyc_lat_apu_result, + cp_curr_fpu_apu_op, + cp_apu_contention { option.weight = 50; `IGNORE_BINS_ZERO_LAT_FPU_OP @@ -621,8 +611,8 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; cp_apu_contention { option.weight = 50; - bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat - with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 0) ); + bins main_cr_bin = cr_rv32f_rd_non_rv32fc_rs2_eq_no_lat + with ( (cp_rd_rs2_eq == 1) & (fpu_latency == 0) ); `IGNORE_BINS_NON_RS2_CV32E40P_INSTR } diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 3019553ca4..b87ae3767d 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -552,6 +552,10 @@ interface uvmt_cv32e40p_cov_if input apu_perf_wb_o; input id_stage_apu_op_ex_o; input id_stage_apu_en_ex_o; + output is_mulh_ex; + output is_misaligned_data_req_ex; + output is_post_inc_ld_st_inst_ex; + output ex_apu_valid_memorised; endclocking : mon_cb //calculate each APU operation's current clock cycle number during execution for functional coverage use From 44647b9a6cbcb23519c534ce6177b5c22879123a Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 1 Dec 2023 17:46:28 +0800 Subject: [PATCH 10/97] Replace and rework COMMON_HWLOOP_EXC_HANDLING_CODE to make it more generic to be used for both traps and debug Signed-off-by: Vaibhav Jain --- .../env/corev-dv/cv32e40p_asm_program_gen.sv | 24 ++++-- .../env/corev-dv/cv32e40p_debug_rom_gen.sv | 32 ++++++++ .../env/corev-dv/cv32e40p_instr_test_pkg.sv | 82 ++++++++++--------- 3 files changed, 90 insertions(+), 48 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv index 299874fbaa..0745dbc5cb 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv @@ -527,8 +527,10 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack // With RV32X enabled, check for ecall instr on the last instr of hwloop // If true, then - // (a) Set MEPC to first instr of hwloop body - // (b) Add logic to decrement the LPCOUNT + // (a) Set MEPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment MEPC by 4 virtual function void gen_ecall_handler(int hart); string instr[$]; cv32e40p_instr_gen_config corev_cfg; @@ -537,7 +539,7 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin instr = {instr, - `COMMON_HWLOOP_EXC_HANDLING_CODE + `COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(cfg.gpr[0],cfg.gpr[1],MEPC) }; end else begin instr = {instr, @@ -555,8 +557,10 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack // With RV32X enabled, check for ebreak instr on the last instr of hwloop // If true, then - // (a) Set MEPC to first instr of hwloop body - // (b) Add logic to decrement the LPCOUNT + // (a) Set MEPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment MEPC by 4 virtual function void gen_ebreak_handler(int hart); string instr[$]; cv32e40p_instr_gen_config corev_cfg; @@ -567,7 +571,7 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin instr = {instr, - `COMMON_HWLOOP_EXC_HANDLING_CODE + `COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(cfg.gpr[0],cfg.gpr[1],MEPC) }; end else begin instr = {instr, @@ -586,8 +590,10 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack // With RV32X enabled, check for illegal instr on the last instr of hwloop // If true, then - // (a) Set MEPC to first instr of hwloop body - // (b) Add logic to decrement the LPCOUNT + // (a) Set MEPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment MEPC by 4 virtual function void gen_illegal_instr_handler(int hart); string instr[$]; cv32e40p_instr_gen_config corev_cfg; @@ -598,7 +604,7 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin instr = {instr, - `COMMON_HWLOOP_EXC_HANDLING_CODE + `COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(cfg.gpr[0],cfg.gpr[1],MEPC) }; end else begin instr = {instr, diff --git a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv index c828b7395b..c4c8a20153 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv @@ -342,5 +342,37 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; gen_signature_handshake(.instr(debug_main), .signature_type(WRITE_CSR), .csr(DSCRATCH0)); endfunction + // Override base class gen_dpc_update() + // Check dcsr.cause, for ebreak as debug entry cause. + // With RV32X enabled, check for ebreak instr on the last instr of hwloop + // If true, then + // (a) Set DPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment DPC by 4 + // as ebreak will set set dpc to its own address, which will cause an + // infinite loop. + virtual function void gen_dpc_update(); + str = {$sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DCSR), + $sformatf("slli x%0d, x%0d, 0x17", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("srli x%0d, x%0d, 0x1d", cfg.scratch_reg, cfg.scratch_reg), + $sformatf("li x%0d, 0x1", cfg.gpr[0]), + $sformatf("bne x%0d, x%0d, 8f", cfg.scratch_reg, cfg.gpr[0])}; + debug_main = {debug_main, str}; + + if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin + str = { + `COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(cfg.gpr[0], cfg.scratch_reg, DPC) + }; + debug_main = {debug_main, str}; + str = {"8: nop"}; + debug_main = {debug_main, str}; + end else begin + increment_csr(DPC, 4, debug_main); + str = {"8: nop"}; + debug_main = {debug_main, str}; + end + endfunction + endclass : cv32e40p_debug_rom_gen diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv index eef1415f43..023ee982b0 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv @@ -28,68 +28,72 @@ package cv32e40p_instr_test_pkg; import corev_instr_test_pkg::*; - // MACRO for Common HWLOOP handling code for all the exception handlers + // MACRO for Common Exception Handling/Debug_Rom code for xEPC CSR management + // Including hwloop CSR management. (Used only with XPULP ISA support) + // // Common handler code to ensure all handlers use same code. // Description: // Check for expection (ecall/ebreak/illegal) on the last hwloop body instr // If true, then - // (a) Set MEPC to first instr of hwloop body - // (b) Add logic to decrement the LPCOUNT - `define COMMON_HWLOOP_EXC_HANDLING_CODE \ + // (a) Set xEPC to first instr of hwloop body if LPCOUNTx >= 2 + // (b) Decrement the LPCOUNTx if LPCOUNTx >= 1 + // Else + // By Default for all other cases increment xEPC by 4 + `define COMMON_EXCEPTION_XEPC_HANDLING_CODE_WITH_HWLOOP_CHECK(SCRATCH_REG0,SCRATCH_REG1,XEPC) \ /* Check LPCOUNT1 >= 1 */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT1), \ - $sformatf("li x%0d, 1", cfg.gpr[1]), \ - $sformatf("bge x%0d, x%0d, 1f", cfg.gpr[0], cfg.gpr[1]), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG0, LPCOUNT1), \ + $sformatf("li x%0d, 1", ``SCRATCH_REG1), \ + $sformatf("bge x%0d, x%0d, 1f", ``SCRATCH_REG0, ``SCRATCH_REG1), \ /* Check LPCOUNT0 >= 1 */ \ - $sformatf("2: csrr x%0d, 0x%0x", cfg.gpr[0], LPCOUNT0), \ - $sformatf("li x%0d, 1", cfg.gpr[1]), \ - $sformatf("bge x%0d, x%0d, 3f", cfg.gpr[0], cfg.gpr[1]), \ + $sformatf("2: csrr x%0d, 0x%0x", ``SCRATCH_REG0, LPCOUNT0), \ + $sformatf("li x%0d, 1", ``SCRATCH_REG1), \ + $sformatf("bge x%0d, x%0d, 3f", ``SCRATCH_REG0, ``SCRATCH_REG1), \ /* Since both LPCOUNT0 & LPCOUNT1 equals 0 */ \ /* Nothing needs to be done for HWLOOPs and its CSRs */ \ $sformatf("beqz x0, 4f"), \ /* HWLOOP1 Handling */ \ /* Check for ILLEGAL being the LAST HWLOOP Body instr */ \ - $sformatf("1: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND1), \ - $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), \ - $sformatf("bne x%0d, x%0d, 2b", cfg.gpr[0], cfg.gpr[1]), \ + $sformatf("1: csrr x%0d, 0x%0x", ``SCRATCH_REG0, ``XEPC), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPEND1), \ + $sformatf("addi x%0d, x%0d, -4", ``SCRATCH_REG1, ``SCRATCH_REG1), \ + $sformatf("bne x%0d, x%0d, 2b", ``SCRATCH_REG0, ``SCRATCH_REG1), \ /* Else, If equal this means the illegal instr was the last */ \ /* hwloop body instr, thus we handle the HWLOOP manually here */ \ /* First decrement lpcount CSR manually as CSR not updated in HW */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT1), \ - $sformatf("addi x%0d, x%0d, -1", cfg.gpr[1], cfg.gpr[1]), \ - $sformatf("cv.count 1, x%0d", cfg.gpr[1]), \ - /* Check if the current LPCOUNT1 value == 0, if so, then MEPC=MEPC+4 */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT1), \ - $sformatf("beqz x%0d, 4f", cfg.gpr[1]), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPCOUNT1), \ + $sformatf("addi x%0d, x%0d, -1", ``SCRATCH_REG1, ``SCRATCH_REG1), \ + $sformatf("cv.count 1, x%0d", ``SCRATCH_REG1), \ + /* Check if the current LPCOUNT1 value == 0, if so, then xEPC=xEPC+4 */ \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPCOUNT1), \ + $sformatf("beqz x%0d, 4f", ``SCRATCH_REG1), \ /* Else LPCOUNT1 still >=1 and thus next, */ \ - /* Set the next MEPC to LPSTART1 for next HWLOOP iteration */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART1), \ + /* Set the next xEPC to LPSTART1 for next HWLOOP iteration */ \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG0, LPSTART1), \ $sformatf("beqz x0, 5f"), \ /* HWLOOP0 Handling */ \ /* Check for ILLEGAL being the LAST HWLOOP Body instr */ \ - $sformatf("3: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPEND0), \ - $sformatf("addi x%0d, x%0d, -4", cfg.gpr[1], cfg.gpr[1]), \ - $sformatf("bne x%0d, x%0d, 4f", cfg.gpr[0], cfg.gpr[1]), \ + $sformatf("3: csrr x%0d, 0x%0x", ``SCRATCH_REG0, ``XEPC), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPEND0), \ + $sformatf("addi x%0d, x%0d, -4", ``SCRATCH_REG1, ``SCRATCH_REG1), \ + $sformatf("bne x%0d, x%0d, 4f", ``SCRATCH_REG0, ``SCRATCH_REG1), \ /* Else, If equal this means the illegal instr was the last */ \ /* hwloop body instr, thus we handle the HWLOOP manually here */ \ /* First decrement lpcount CSR manually as CSR not updated in HW */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT0), \ - $sformatf("addi x%0d, x%0d, -1", cfg.gpr[1], cfg.gpr[1]), \ - $sformatf("cv.count 0, x%0d", cfg.gpr[1]), \ - /* Check if the current LPCOUNT0 value == 0, if so, then MEPC=MEPC+4 */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[1], LPCOUNT0), \ - $sformatf("beqz x%0d, 4f", cfg.gpr[1]), \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPCOUNT0), \ + $sformatf("addi x%0d, x%0d, -1", ``SCRATCH_REG1, ``SCRATCH_REG1), \ + $sformatf("cv.count 0, x%0d", ``SCRATCH_REG1), \ + /* Check if the current LPCOUNT0 value == 0, if so, then xEPC=xEPC+4 */ \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG1, LPCOUNT0), \ + $sformatf("beqz x%0d, 4f", ``SCRATCH_REG1), \ /* Else LPCOUNT0 still >=1 and thus next, */ \ - /* Set the next MEPC to LPSTART0 for next HWLOOP iteration */ \ - $sformatf("csrr x%0d, 0x%0x", cfg.gpr[0], LPSTART0), \ + /* Set the next xEPC to LPSTART0 for next HWLOOP iteration */ \ + $sformatf("csrr x%0d, 0x%0x", ``SCRATCH_REG0, LPSTART0), \ $sformatf("beqz x0, 5f"), \ - /* Default increment for MEPC by 4 */ \ - $sformatf("4: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), \ - $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), \ - /* Write MEPC */ \ - $sformatf("5: csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]) + /* Default increment for xEPC by 4 */ \ + $sformatf("4: csrr x%0d, 0x%0x", ``SCRATCH_REG0, ``XEPC), \ + $sformatf("addi x%0d, x%0d, 4", ``SCRATCH_REG0, ``SCRATCH_REG0), \ + /* Write xEPC */ \ + $sformatf("5: csrw 0x%0x, x%0d", ``XEPC, ``SCRATCH_REG0) `include "cv32e40p_instr_gen_config.sv" From e444fa76e436c183f6aa2f3d017ea51fe4d45bbd Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 1 Dec 2023 17:47:50 +0800 Subject: [PATCH 11/97] Re-enable ImperasDV isacov, keeping PULP coverage disabled temporarily Signed-off-by: Vaibhav Jain --- cv32e40p/tb/uvmt/imperas_dv.flist | 2 +- ...cv32e40p_imperas_riscv_coverage_config.svh | 24 +++++++++---------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/cv32e40p/tb/uvmt/imperas_dv.flist b/cv32e40p/tb/uvmt/imperas_dv.flist index 735e764513..ea7f2cd08c 100644 --- a/cv32e40p/tb/uvmt/imperas_dv.flist +++ b/cv32e40p/tb/uvmt/imperas_dv.flist @@ -25,7 +25,7 @@ +incdir+${IMPERAS_HOME}/ImpProprietary/include/host +incdir+${IMPERAS_HOME}/ImpProprietary/source/host/CV32E40Pv2_riscvISACOV/source -//${TBSRC_HOME}/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh +${TBSRC_HOME}/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh -f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f -f ${IMPERAS_HOME}/ImpProprietary/source/host/idv/idv.f diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh index b82a2c2ddd..dbdf843906 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh @@ -6,7 +6,7 @@ `define IDV_INCLUDE_TRACE2COV `define COVER_BASE_RV32I `define COVER_LEVEL_COMPL_BAS - `define COVER_LEVEL_COMPL_EXT + //`define COVER_LEVEL_COMPL_EXT `define COVER_LEVEL_DV_UP_BAS `define COVER_LEVEL_DV_UP_EXT `define COVER_LEVEL_DV_PR_BAS @@ -31,15 +31,15 @@ `define COVER_RV32ZCF_ILLEGAL `endif - `ifdef PULP - `define COVER_XPULPV2 - `ifdef CLUSTER - `define COVER_XPULPV2C - `else - `define COVER_XPULPV2C_ILLEGAL - `endif - `else - `define COVER_XPULPV2_ILLEGAL - `define COVER_XPULPV2C_ILLEGAL - `endif + //`ifdef PULP + // `define COVER_XPULPV2 + // `ifdef CLUSTER + // `define COVER_XPULPV2C + // `else + // `define COVER_XPULPV2C_ILLEGAL + // `endif + //`else + // `define COVER_XPULPV2_ILLEGAL + // `define COVER_XPULPV2C_ILLEGAL + //`endif `endif From 6754aeb4033f2b6f2d56593b3a268b9b2f4dfeb0 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 1 Dec 2023 17:48:17 +0800 Subject: [PATCH 12/97] Update cv32e40p core hash Signed-off-by: Vaibhav Jain --- cv32e40p/sim/ExternalRepos.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index e4f22c4d8b..789b05c660 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= 1d0ec8d83091bda8e65c36c48614a41065f5fc10 +CV_CORE_HASH ?= 6b34db2a91d0e208b2a4571b7531d7630d886df4 CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. From 13f5a602e2fd7b8f0cfab534121b0ef632548f12 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 1 Dec 2023 20:34:07 +0800 Subject: [PATCH 13/97] Resolve issue of avail_regs of riscv_rand_instr_stream not getting randomized Signed-off-by: Vaibhav Jain --- .../corev-dv/cv32e40p_rand_instr_stream.sv | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv index 4d3b573608..cc6ae8fe16 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv @@ -27,6 +27,17 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; protected int idx_end[$]; protected int idx_min = 0; cv32e40p_instr_gen_config cv32e40p_cfg; + rand int unsigned default_avail_reg; + + constraint def_avail_reg_c { + if ((cfg.enable_fp_in_x_regs == 1) && (RV32ZFINX inside {riscv_instr_pkg::supported_isa})) { + default_avail_reg >= 8; + default_avail_reg <= (22 - cv32e40p_cfg.num_zfinx_reserved_reg); + } else { + default_avail_reg >= 8; + default_avail_reg <= 22; + } + } `uvm_object_utils(cv32e40p_rand_instr_stream) //`uvm_object_new @@ -155,12 +166,50 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; endfunction + // Override base class randomize_avail_regs function + // Add randomization for number of registers to be randomized + virtual function void randomize_avail_regs(); + std::randomize(default_avail_reg) with { if ((cfg.enable_fp_in_x_regs == 1) && (RV32ZFINX inside {riscv_instr_pkg::supported_isa})) { + default_avail_reg >= 8; + default_avail_reg <= (22 - cv32e40p_cfg.num_zfinx_reserved_reg); + } else { + default_avail_reg >= 8; + default_avail_reg <= 22; + } + }; + + avail_regs = new[default_avail_reg]; + if(avail_regs.size() > 0) begin + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(avail_regs, + unique{avail_regs}; + //avail_regs[0] inside {[S0 : A5]}; + foreach(avail_regs[i]) { + !(avail_regs[i] inside {cfg.reserved_regs, reserved_rd, cfg.gpr[0], cfg.gpr[1], cfg.gpr[2]}); + }, + "Cannot randomize avail_regs") + end + endfunction + + //Function: cv32e40p_rand_instr_stream::gen_instr() //override the parent class gen_instr() inside cv32e40p_rand_instr_stream virtual function void gen_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1, bit is_debug_program = 1'b0); setup_allowed_instr(no_branch, no_load_store); + // Need to randomize avail_regs[] to ensure the randomize_gpr() call + // actually randomize the registers for each instruction. + // And this also ensures the randomization is done separately for each + // program section. + // This also ensures reserved_regs get removed from gpr randomization + // for each instruction. + randomize_avail_regs(); + + `uvm_info("cv32e40p_rand_instr_stream", $sformatf("Randomized default_avail_reg = %d", default_avail_reg), UVM_DEBUG) + foreach(avail_regs[i]) begin + `uvm_info("cv32e40p_rand_instr_stream", $sformatf("Randomized avail_regs[%d] = %s", i, avail_regs[i]), UVM_DEBUG) + end + //Use this plusarg - include_xpulp_instr_in_debug_rom to include xpulp instr //In random debug_rom instructions. Added for v2 debug tests with xpulp. if (cv32e40p_cfg.xpulp_instr_in_debug_rom && is_debug_program && $test$plusargs("include_xpulp_instr_in_debug_rom")) begin From 2fba3157f3b83b9c2da2b06e459b15cea7e56acb Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Sat, 2 Dec 2023 10:19:08 +0800 Subject: [PATCH 14/97] update randomize_avail_regs again to solve issues with compress instr randomization Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv index cc6ae8fe16..de3f2bfb96 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv @@ -182,9 +182,9 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; if(avail_regs.size() > 0) begin `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(avail_regs, unique{avail_regs}; - //avail_regs[0] inside {[S0 : A5]}; + avail_regs[0] inside {[S0 : A5]}; foreach(avail_regs[i]) { - !(avail_regs[i] inside {cfg.reserved_regs, reserved_rd, cfg.gpr[0], cfg.gpr[1], cfg.gpr[2]}); + !(avail_regs[i] inside {cfg.reserved_regs, reserved_rd}); }, "Cannot randomize avail_regs") end From e559c799250aa203e833b0c58eaa6f33a6882068 Mon Sep 17 00:00:00 2001 From: bsm Date: Mon, 4 Dec 2023 16:17:54 +0800 Subject: [PATCH 15/97] Increase limit to fix regression issue Signed-off-by: bsm --- cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index 059ded8baa..ff02f09941 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -1450,7 +1450,7 @@ class cv32e40p_fp_op_fwd_instr_stream extends cv32e40p_float_zfinx_base_instr_st riscv_fp_in_x_regs_instr instr_zfinx; riscv_floating_point_instr instr_f; bit has_rd, has_rs1, has_rs2, has_rs3; - int unsigned loop_cnt, loop_limit = 50; + int unsigned loop_cnt, loop_limit = 100; if (!(i % num_of_instr_per_block)) begin : RESET_PRIOR_START_OF_BLOCK i_instr_list.delete(); From e8fef3e59399c5d9245216020de0fded155e5af2 Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 8 Dec 2023 14:26:14 +0800 Subject: [PATCH 16/97] Fix ucdb merge issue Signed-off-by: bsm --- mk/uvmt/vsim.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk index d7a6370ddb..d6c718c623 100644 --- a/mk/uvmt/vsim.mk +++ b/mk/uvmt/vsim.mk @@ -259,7 +259,7 @@ endif COV_FLAGS = COV_REPORT = cov_report COV_MERGE_TARGET = -COV_MERGE_FIND = find $(SIM_CFG_RESULTS) -type f -name "*.ucdb" -exec echo {} > $(VSIM_COV_MERGE_DIR)/ucdb.list \; +COV_MERGE_FIND = find $(SIM_CFG_RESULTS) -type f -name "*.ucdb" | grep -v corev-dv > $(VSIM_COV_MERGE_DIR)/ucdb.list COV_MERGE_FLAGS = merge -testassociated -verbose -64 -out merged.ucdb -inputs ucdb.list ifeq ($(call IS_YES,$(MERGE)),YES) From 3eeb856736957fd7be3059d4bce34118db2e512e Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Dec 2023 11:34:29 +0800 Subject: [PATCH 17/97] add func store_instr_gpr_handling to use reserved reg from cfg for str instr in debug program Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv index de3f2bfb96..1cc876d7dd 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv @@ -219,6 +219,7 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; 1: randomize_debug_rom_instr(.instr(instr_list[i]), .is_in_debug(is_debug_program), .disable_dist()); 2: randomize_instr(instr_list[i], is_debug_program); endcase + store_instr_gpr_handling(instr_list[i]); end end else begin @@ -266,5 +267,14 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; randomize_gpr(instr); endfunction + // Function to assign reserved reg for store instr from cfg to avoid random + // reg operands for stores which may result in corruption of instr memory + function void store_instr_gpr_handling(riscv_instr instr); + if (instr.instr_name inside {SB, SH, SW, C_SW, C_FSW, FSW, CV_SB, CV_SH, CV_SW}) begin + instr.rs1 = cv32e40p_cfg.str_rs1; + instr.rd = cv32e40p_cfg.str_rs3; + end + endfunction + endclass From 664debdd1bdad5fd505fa33bb3dcbf9203d73e2b Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Dec 2023 11:47:00 +0800 Subject: [PATCH 18/97] add init for str instr's reserved source registers rs1/rs3 for debug program Signed-off-by: Vaibhav Jain --- .../env/corev-dv/cv32e40p_debug_rom_gen.sv | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv index c4c8a20153..804a5d236e 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv @@ -107,6 +107,8 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; gen_single_step_logic(); end gen_dpc_update(); + init_dbg_rom_str_reserved_gpr(); + // write DCSR to the testbench for any analysis gen_signature_handshake(.instr(debug_main), .signature_type(WRITE_CSR), .csr(DCSR)); if (cfg.enable_ebreak_in_debug_rom || cfg.set_dcsr_ebreak) begin @@ -374,5 +376,24 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; end endfunction + // Function to initialize GPR reserved for stores + virtual function void init_dbg_rom_str_reserved_gpr(); + string reg_name; + bit [31:0] reg_val; + + // Initialize reserved registers for store instr + if (!cfg_corev.no_load_store) begin + reg_name = cfg_corev.str_rs1.name(); + reg_val = 32'h88000000; // FIXME : Remove hardcoded value to allow configuration based on linker + str = {$sformatf("li %0s, 0x%0x", reg_name.tolower(), reg_val)}; + debug_main = {debug_main, str}; + + reg_name = cfg_corev.str_rs3.name(); + reg_val = $urandom_range(0,255); // FIXME : include negative also + str = {$sformatf("li %0s, 0x%0x", reg_name.tolower(), reg_val)}; + debug_main = {debug_main, str}; + end + endfunction + endclass : cv32e40p_debug_rom_gen From 89adbba1cfe33c0cac3502668d4d471f9f59b331 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Dec 2023 12:27:19 +0800 Subject: [PATCH 19/97] add override for gen_init_section to initialize str instr reserved reg before other reg initialization Signed-off-by: Vaibhav Jain --- .../env/corev-dv/cv32e40p_asm_program_gen.sv | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv index 0745dbc5cb..3f4b3c6fa8 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv @@ -682,4 +682,54 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; gen_section(get_label("store_fault_handler", hart), instr); endfunction + // Function to initialize GPR reserved for stores + virtual function void init_str_reserved_gpr(); + string str; + string reg_name; + bit [DATA_WIDTH-1:0] reg_val; + cv32e40p_instr_gen_config corev_cfg; + + `DV_CHECK($cast(corev_cfg, cfg)) + // Initialize reserved registers for store instr + if (!corev_cfg.no_load_store) begin + reg_name = corev_cfg.str_rs1.name(); + reg_val = 32'h80000000; // FIXME : Remove hardcoded value to allow configuration based on linker + str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), reg_val); + instr_stream.push_back(str); + + reg_name = corev_cfg.str_rs3.name(); + reg_val = $urandom_range(0,255); // FIXME : include negative also + str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), reg_val); + instr_stream.push_back(str); + end + endfunction + + // Override gen_init_section + // Add init_str_reserved_gpr() before other fpr/gpr initialization + virtual function void gen_init_section(int hart); + string str; + str = format_string(get_label("init:", hart), LABEL_STR_LEN); + instr_stream.push_back(str); + + // First initialize the store reserved register to minimize issues due to random stores + init_str_reserved_gpr(); + + if (cfg.enable_floating_point) begin + init_floating_point_gpr(); + end + init_gpr(); + // Init stack pointer to point to the end of the user stack + str = {indent, $sformatf("la x%0d, %0suser_stack_end", cfg.sp, hart_prefix(hart))}; + instr_stream.push_back(str); + if (cfg.enable_vector_extension) begin + randomize_vec_gpr_and_csr(); + end + core_is_initialized(); + gen_dummy_csr_write(); // TODO add a way to disable xStatus read + if (riscv_instr_pkg::support_pmp) begin + str = {indent, "j main"}; + instr_stream.push_back(str); + end + endfunction + endclass : cv32e40p_asm_program_gen From 6d71cd7ec7b4da778bbe478f752c970cf57d0b6c Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Dec 2023 12:31:13 +0800 Subject: [PATCH 20/97] add cv32e40p_instr_gen_config object for the class and remove all other instances Signed-off-by: Vaibhav Jain --- .../env/corev-dv/cv32e40p_asm_program_gen.sv | 54 +++++-------------- 1 file changed, 13 insertions(+), 41 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv index 3f4b3c6fa8..f0283a00c0 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_asm_program_gen.sv @@ -33,14 +33,20 @@ // - gen_instr_fault_handler() // - gen_load_fault_handler() // - gen_store_fault_handler() +// - gen_init_section() //----------------------------------------------------------------------------------------- class cv32e40p_asm_program_gen extends corev_asm_program_gen; + cv32e40p_instr_gen_config corev_cfg; + `uvm_object_utils(cv32e40p_asm_program_gen) function new (string name = ""); super.new(name); + if(!uvm_config_db#(cv32e40p_instr_gen_config)::get(null,get_full_name(),"cv32e40p_instr_cfg", corev_cfg)) begin + `uvm_fatal(get_full_name(), "Cannot get cv32e40p_instr_gen_config") + end endfunction // Override the gen_trap_handler_section function from riscv_asm_program_gen.sv @@ -54,9 +60,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; bit is_interrupt = 'b1; string tvec_name; string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") if (cfg.mtvec_mode == VECTORED) begin gen_interrupt_vector_table(hart, mode, status, cause, ie, ip, scratch, instr); @@ -166,8 +169,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // software interrupts, are vectored to the same location as synchronous exceptions. This // ambiguity does not arise in practice, since user-mode software interrupts are either // disabled or delegated - cv32e40p_instr_gen_config corev_cfg; - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") instr = {instr, ".option norvc;", $sformatf("j %0s%0smode_exception_handler", hart_prefix(hart), mode)}; @@ -250,9 +251,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; privileged_reg_t status, ip, ie, scratch; string interrupt_handler_instr[$]; - cv32e40p_instr_gen_config corev_cfg; - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") - ls_unit = (XLEN == 32) ? "w" : "d"; if (mode < cfg.init_privileged_mode) return; if (mode == USER_MODE && !riscv_instr_pkg::support_umode_trap) return; @@ -406,14 +404,12 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; string str; string reg_name; bit [DATA_WIDTH-1:0] reg_val; - cv32e40p_instr_gen_config cfg_corev; bit [31:0] imm; - `DV_CHECK($cast(cfg_corev, cfg)) // Init general purpose registers with random values for(int i = 0; i < NUM_GPR; i++) begin if (i inside {cfg.sp, cfg.tp}) continue; - if (cfg.gen_debug_section && (i inside {cfg_corev.dp})) continue; + if (cfg.gen_debug_section && (i inside {corev_cfg.dp})) continue; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(reg_val, reg_val dist { @@ -429,23 +425,23 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; //after initializing all gprs, for zfinx extention tests again initialize //gprs for floating point instructions if(RV32ZFINX inside {supported_isa}) begin - foreach(cfg_corev.zfinx_reserved_gpr[i]) begin - if (cfg_corev.zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP}) continue; + foreach(corev_cfg.zfinx_reserved_gpr[i]) begin + if (corev_cfg.zfinx_reserved_gpr[i] inside {ZERO, RA, SP, GP, TP}) continue; imm = get_rand_spf_value(); - reg_name = cfg_corev.zfinx_reserved_gpr[i].name(); + reg_name = corev_cfg.zfinx_reserved_gpr[i].name(); str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), imm); instr_stream.push_back(str); end end // Initialize reserved registers for store instr - if (!cfg_corev.no_load_store) begin - reg_name = cfg_corev.str_rs1.name(); + if (!corev_cfg.no_load_store) begin + reg_name = corev_cfg.str_rs1.name(); reg_val = 32'h80000000; // FIXME : Remove hardcoded value to allow configuration based on linker str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), reg_val); instr_stream.push_back(str); - reg_name = cfg_corev.str_rs3.name(); + reg_name = corev_cfg.str_rs3.name(); reg_val = $urandom_range(0,255); // FIXME : include negative also str = $sformatf("%0sli%0s %0s, 0x%0x", indent, indent, reg_name.tolower(), reg_val); instr_stream.push_back(str); @@ -464,9 +460,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; string opts[$]; int dir_stream_id = 0; - cv32e40p_instr_gen_config corev_cfg; - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") - if(corev_cfg.insert_rand_directed_instr_stream) begin //test_rand_directed_instr_stream_num specify the total num of rand_* streams to select from dir_stream_id = $urandom_range(0,corev_cfg.test_rand_directed_instr_stream_num-1); @@ -533,9 +526,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // By Default for all other cases increment MEPC by 4 virtual function void gen_ecall_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") if (riscv_instr_pkg::RV32X inside {riscv_instr_pkg::supported_isa}) begin instr = {instr, @@ -563,9 +553,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // By Default for all other cases increment MEPC by 4 virtual function void gen_ebreak_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, EBREAK_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); @@ -596,9 +583,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // By Default for all other cases increment MEPC by 4 virtual function void gen_illegal_instr_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, ILLEGAL_INSTR_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); @@ -623,9 +607,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack virtual function void gen_instr_fault_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, INSTR_FAULT_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); @@ -644,9 +625,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack virtual function void gen_load_fault_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, LOAD_FAULT_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); @@ -665,9 +643,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; // Replace pop_gpr_from_kernel_stack with pop_regfile_from_kernel_stack virtual function void gen_store_fault_handler(int hart); string instr[$]; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") gen_signature_handshake(instr, CORE_STATUS, STORE_FAULT_EXCEPTION); gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); @@ -687,9 +662,6 @@ class cv32e40p_asm_program_gen extends corev_asm_program_gen; string str; string reg_name; bit [DATA_WIDTH-1:0] reg_val; - cv32e40p_instr_gen_config corev_cfg; - - `DV_CHECK($cast(corev_cfg, cfg)) // Initialize reserved registers for store instr if (!corev_cfg.no_load_store) begin reg_name = corev_cfg.str_rs1.name(); From 8bdfa16cd090df639dd77caa273f07b6982f5b9d Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Dec 2023 12:32:23 +0800 Subject: [PATCH 21/97] remove workaround which was excluding pulp store instr in debug program Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv | 6 ------ 1 file changed, 6 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv index a22508508b..3756295b06 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv @@ -175,12 +175,6 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence; instr_stream.instr_list[i].has_label = 1'b0; end end - // Remove all pulp store instructions inside debug_program - if(is_debug_program == 1) begin - if (instr_stream.instr_list[i].instr_name inside {CV_SB, CV_SH, CV_SW} ) begin - instr_stream.instr_list.delete(i); - end - end i++; end // while `uvm_info(get_full_name(), "Finished post-processing instructions", UVM_HIGH) From 7ad565b361921d87ed03f9216fd875a0a794fbf0 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Dec 2023 12:50:00 +0800 Subject: [PATCH 22/97] update cv32e40p core hash Signed-off-by: Vaibhav Jain --- cv32e40p/sim/ExternalRepos.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index 789b05c660..42405b0b43 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= 6b34db2a91d0e208b2a4571b7531d7630d886df4 +CV_CORE_HASH ?= 61423d98758a0b61835bd7dcb382e8a33159cddb CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. From fbae748231050b905c46ced48058b75fc784ad08 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Dec 2023 17:44:05 +0800 Subject: [PATCH 23/97] temporarily remove cluster tests and build until cluster tb ready Signed-off-by: Vaibhav Jain --- cv32e40p/regress/cv32e40pv2_ci_check.yaml | 81 +++++++++++------------ 1 file changed, 37 insertions(+), 44 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_ci_check.yaml b/cv32e40p/regress/cv32e40pv2_ci_check.yaml index 04227a5d4c..d06a3289a9 100644 --- a/cv32e40p/regress/cv32e40pv2_ci_check.yaml +++ b/cv32e40p/regress/cv32e40pv2_ci_check.yaml @@ -48,40 +48,40 @@ builds: cfg: pulp_fpu_zfinx_2cyclat dir: cv32e40p/sim/uvmt - uvmt_cv32e40p_pulp_cluster: - cmd: make comp comp_corev-dv - cfg: pulp_cluster - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_1cyclat: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_1cyclat - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_2cyclat: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_2cyclat - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_zfinx - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx_1cyclat: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_zfinx_1cyclat - dir: cv32e40p/sim/uvmt - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx_2cyclat: - cmd: make comp comp_corev-dv - cfg: pulp_cluster_fpu_zfinx_2cyclat - dir: cv32e40p/sim/uvmt +# uvmt_cv32e40p_pulp_cluster: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_1cyclat: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_1cyclat +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_2cyclat: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_2cyclat +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_zfinx: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_zfinx +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_zfinx_1cyclat: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_zfinx_1cyclat +# dir: cv32e40p/sim/uvmt +# +# uvmt_cv32e40p_pulp_cluster_fpu_zfinx_2cyclat: +# cmd: make comp comp_corev-dv +# cfg: pulp_cluster_fpu_zfinx_2cyclat +# dir: cv32e40p/sim/uvmt tests: hello-world: @@ -95,13 +95,6 @@ tests: - uvmt_cv32e40p_pulp_fpu_zfinx - uvmt_cv32e40p_pulp_fpu_zfinx_1cyclat - uvmt_cv32e40p_pulp_fpu_zfinx_2cyclat - - uvmt_cv32e40p_pulp_cluster - - uvmt_cv32e40p_pulp_cluster_fpu - - uvmt_cv32e40p_pulp_cluster_fpu_1cyclat - - uvmt_cv32e40p_pulp_cluster_fpu_2cyclat - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx_1cyclat - - uvmt_cv32e40p_pulp_cluster_fpu_zfinx_2cyclat description: UVM Hello World Test dir: cv32e40p/sim/uvmt cmd: make test COREV=YES TEST=hello-world CFG_PLUSARGS="+UVM_TIMEOUT=1000000" @@ -111,13 +104,13 @@ tests: build: uvmt_cv32e40p_pulp_fpu description: Interrupt directed on PULP+FPU HW dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + cmd: make test COREV=YES TEST=interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 debug_test: build: uvmt_cv32e40p_pulp_fpu dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + cmd: make test COREV=YES TEST=debug_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 corev_rand_fp_instr_sanity_test: @@ -147,4 +140,4 @@ tests: corev_rand_pulp_hwloop_test: build: uvmt_cv32e40p_pulp dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" From 8f50e970af933ece30ef845a99fbdb5e1562b98c Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Dec 2023 17:44:50 +0800 Subject: [PATCH 24/97] move corev_rand_pulp_hwloop_exception_with_int_debug_trigger to long list Signed-off-by: Vaibhav Jain --- cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml | 8 ++++++++ cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml | 8 -------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml index e401209091..8a3bd04753 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml @@ -119,3 +119,11 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_single_step_en + corev_rand_pulp_hwloop_exception_with_int_debug_trigger: + testname: corev_rand_pulp_hwloop_exception + description: hwloop exception test with interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + test_cfg: gen_rand_int,debug_trigger_basic + diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 215d5c1d3a..7cb1b5abac 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -115,14 +115,6 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" test_cfg: debug_trigger_basic - corev_rand_pulp_hwloop_exception_with_int_debug_trigger: - testname: corev_rand_pulp_hwloop_exception - description: hwloop exception test with interrupt and debug trigger - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: gen_rand_int,debug_trigger_basic - debug_test: build: uvmt_cv32e40p description: debug_test (adapted from v1) From 1fd49ef3aca85a95abf84f81e8e5ccf3400b098d Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 12 Dec 2023 17:45:08 +0800 Subject: [PATCH 25/97] update cv32e40p core hash Signed-off-by: Vaibhav Jain --- cv32e40p/sim/ExternalRepos.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index 42405b0b43..fdbcc027d5 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= 61423d98758a0b61835bd7dcb382e8a33159cddb +CV_CORE_HASH ?= 11e24901f5a6c8e265250d26d211c3ddfd3a502d CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. From a58a0a25730ddc8dd4f583bd61358e82abe6f88f Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 12 Dec 2023 17:18:52 +0100 Subject: [PATCH 26/97] Increased a bit Embench test compilation timeout. Signed-off-by: Pascal Gouedo --- bin/run_embench.py | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/run_embench.py b/bin/run_embench.py index 6523552922..8f92ff436c 100755 --- a/bin/run_embench.py +++ b/bin/run_embench.py @@ -190,6 +190,7 @@ def main(): f'--ldflags=-T{paths["bsp"]}/link.ld', f'--builddir={args.builddir}', f'--logdir={args.logdir}', + f'--timeout=15', '--clean'] logger.info(f"Calling build script: {' '.join(cmd)}") try: From b4558c51aeab97a218197dd790b9a89a9457ec48 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 12 Dec 2023 17:19:48 +0100 Subject: [PATCH 27/97] Corrected Coremark compilation options and added context save/restore switch. Signed-off-by: Pascal Gouedo --- cv32e40p/tests/programs/custom/coremark/test.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tests/programs/custom/coremark/test.yaml b/cv32e40p/tests/programs/custom/coremark/test.yaml index c59b6eadcc..64b6f00651 100644 --- a/cv32e40p/tests/programs/custom/coremark/test.yaml +++ b/cv32e40p/tests/programs/custom/coremark/test.yaml @@ -3,7 +3,8 @@ uvm_test: uvmt_cv32e40p_firmware_test_c default_cflags: > -O3 -mabi=ilp32 - -march=rv32im + -march=$(RISCV_MARCH) + -msave-restore -falign-functions=16 -funroll-all-loops -falign-jumps=4 @@ -14,6 +15,6 @@ default_cflags: > -DPERFORMANCE_RUN=1 -DITERATIONS=30 -DHAS_STDIO=1 -DHAS_PRINTF=1 -DHAS_FLOAT=1 - -DFLAGS_STR=\""-mabi=ilp32 -march=rv32im -O3 -falign-functions=16 -funroll-all-loops -falign-jumps=4 -finline-functions -Wall -pedantic -nostartfiles -static -DPERFORMANCE_RUN=1 -DITERATIONS=30 -DHAS_STDIO=1 -DHAS_PRINTF=1 -DHAS_FLOAT=1"\" + -DFLAGS_STR=\""-O3 -mabi=ilp32 -march=$(RISCV_MARCH) -msave-restore -falign-functions=16 -funroll-all-loops -falign-jumps=4 -finline-functions -Wall -static -pedantic -nostartfiles -DPERFORMANCE_RUN=1 -DITERATIONS=30 -DHAS_STDIO=1 -DHAS_PRINTF=1 -DHAS_FLOAT=1"\" description: > Runs the CoreMark benchmark From 9f9f0314ad938ae6a2208047eddc5bb22436fe61 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 12 Dec 2023 17:21:29 +0100 Subject: [PATCH 28/97] Inverted csr writes in floating point enable function to have a clean status after its execution. Signed-off-by: Pascal Gouedo --- cv32e40p/tests/programs/custom/fpu_bugs_test/test.c | 7 ++++--- .../tests/programs/custom/interrupt_test/interrupt_test.c | 4 ++-- cv32e40p/tests/programs/custom/matmul_32b_float/test.c | 5 +++-- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c index 9b2687e115..22e3b036c8 100644 --- a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c +++ b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c @@ -26,9 +26,10 @@ void fp_enable () { unsigned int fs = MSTATUS_FS_INITIAL; - __asm__ volatile("csrs mstatus, %0;" - "csrwi fcsr, 0;" - : : "r"(fs)); + + asm volatile("csrwi fcsr, 0;" + "csrs mstatus, %0;" + : : "r"(fs)); } const long int INPUT[10] __attribute__ ((aligned (4))) = { diff --git a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c index df241ce98e..55c8d9bf7f 100644 --- a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c +++ b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c @@ -46,8 +46,8 @@ void fp_enable () { unsigned int fs = MSTATUS_FS_INITIAL; - asm volatile("csrs mstatus, %0;" - "csrwi fcsr, 0;" + asm volatile("csrwi fcsr, 0;" + "csrs mstatus, %0;" : : "r"(fs)); } #endif diff --git a/cv32e40p/tests/programs/custom/matmul_32b_float/test.c b/cv32e40p/tests/programs/custom/matmul_32b_float/test.c index 13ac3b2a46..dec8c307d2 100644 --- a/cv32e40p/tests/programs/custom/matmul_32b_float/test.c +++ b/cv32e40p/tests/programs/custom/matmul_32b_float/test.c @@ -47,8 +47,9 @@ int checkInt (long int *B, long int *A, long int n) void fp_enable () { unsigned int fs = MSTATUS_FS_INITIAL; - __asm__ volatile("csrs mstatus, %0;" - "csrwi fcsr, 0;" + + __asm__ volatile("csrwi fcsr, 0;" + "csrs mstatus, %0;" : : "r"(fs)); } #endif From f428792f17e622d4e10fe8a60542c58b374cc92b Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 12 Dec 2023 17:22:57 +0100 Subject: [PATCH 29/97] Better/global correction of debug assertion. Signed-off-by: Pascal Gouedo --- .../tb/uvmt/uvmt_cv32e40p_debug_assert.sv | 39 +++++++++++-------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv index 3ffab6661a..41bdca2a7e 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv @@ -39,6 +39,7 @@ module uvmt_cv32e40p_debug_assert logic exception_addr_at_entry_flag; logic [31:0] tdata2_at_entry; // Locally track which debug cause should be used + logic is_decoding_v1; logic [2:0] debug_cause_pri; logic [31:0] boot_addr_at_entry; @@ -51,21 +52,26 @@ module uvmt_cv32e40p_debug_assert // Clocking blocks // --------------------------------------------------------------------------- + assign is_decoding_v1 = cov_assert_if.is_decoding || + ((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE || cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP) && + (cov_assert_if.debug_req_i || cov_assert_if.trigger_match_i) && !cov_assert_if.debug_mode_q + ); + // Single clock, single reset design, use default clocking default clocking @(posedge cov_assert_if.clk_i); endclocking default disable iff !(cov_assert_if.rst_ni); - assign cov_assert_if.is_ebreak = cov_assert_if.is_decoding & + assign cov_assert_if.is_ebreak = is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i & (cov_assert_if.id_stage_instr_rdata_i == 32'h00100073) & cov_assert_if.id_stage_is_compressed == 1'b0; - assign cov_assert_if.is_cebreak = cov_assert_if.is_decoding & + assign cov_assert_if.is_cebreak = is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i & (cov_assert_if.id_stage_instr_rdata_i == 32'h00100073) & cov_assert_if.id_stage_is_compressed == 1'b1; - assign cov_assert_if.is_mulhsu = cov_assert_if.is_decoding & + assign cov_assert_if.is_mulhsu = is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i & cov_assert_if.id_stage_instr_rdata_i[31:25] == 7'h1 & cov_assert_if.id_stage_instr_rdata_i[14:12] == 3'b010 & @@ -120,7 +126,7 @@ module uvmt_cv32e40p_debug_assert // Exclude single stepping as the sequence gets very complicated property p_cebreak_exception; disable iff(cov_assert_if.debug_req_i | !cov_assert_if.rst_ni) - $rose(cov_assert_if.is_cebreak) && cov_assert_if.dcsr_q[15] == 1'b0 && !cov_assert_if.debug_mode_q && cov_assert_if.is_decoding && cov_assert_if.id_valid && + $rose(cov_assert_if.is_cebreak) && cov_assert_if.dcsr_q[15] == 1'b0 && !cov_assert_if.debug_mode_q && is_decoding_v1 && cov_assert_if.id_valid && !cov_assert_if.debug_req_i && !cov_assert_if.dcsr_q[2] |-> (decode_valid) [->1:2] ##0 !cov_assert_if.debug_mode_q && (cov_assert_if.mcause_q[5:0] === cv32e40p_pkg::EXC_CAUSE_BREAKPOINT) && (cov_assert_if.mepc_q == pc_at_ebreak) && @@ -135,7 +141,7 @@ module uvmt_cv32e40p_debug_assert // Exclude single stepping as the sequence gets very complicated property p_ebreak_exception; disable iff(cov_assert_if.debug_req_i | !cov_assert_if.rst_ni) - $rose(cov_assert_if.is_ebreak) && cov_assert_if.dcsr_q[15] == 1'b0 && !cov_assert_if.debug_mode_q && cov_assert_if.is_decoding && cov_assert_if.id_valid && + $rose(cov_assert_if.is_ebreak) && cov_assert_if.dcsr_q[15] == 1'b0 && !cov_assert_if.debug_mode_q && is_decoding_v1 && cov_assert_if.id_valid && !cov_assert_if.debug_req_i && !cov_assert_if.dcsr_q[2] |-> (decode_valid) [->1:2] ##0 !cov_assert_if.debug_mode_q && (cov_assert_if.mcause_q[5:0] === cv32e40p_pkg::EXC_CAUSE_BREAKPOINT) && (cov_assert_if.mepc_q == pc_at_ebreak) && @@ -169,7 +175,7 @@ module uvmt_cv32e40p_debug_assert // Trigger match results in debug mode property p_trigger_match; - cov_assert_if.trigger_match_i ##0 cov_assert_if.tdata1[2] ##0 !cov_assert_if.debug_mode_q ##0 cov_assert_if.id_stage_instr_valid_i + cov_assert_if.trigger_match_i ##0 cov_assert_if.tdata1[2] ##0 !cov_assert_if.debug_mode_q ##0 cov_assert_if.id_stage_instr_valid_i ##0 is_decoding_v1 |-> decode_valid [->2] ##0 (cov_assert_if.debug_mode_q && (cov_assert_if.dcsr_q[8:6]=== cv32e40p_pkg::DBG_CAUSE_TRIGGER) && (cov_assert_if.depc_q == tdata2_at_entry)) && (cov_assert_if.id_stage_pc == halt_addr_at_entry); @@ -190,7 +196,7 @@ module uvmt_cv32e40p_debug_assert // Exception in debug mode results in pc->dm_exception_addr_i property p_debug_mode_exception; - $rose(cov_assert_if.illegal_insn_i) && cov_assert_if.debug_mode_q && cov_assert_if.is_decoding |-> (decode_valid & cov_assert_if.id_valid) [->2] ##0 cov_assert_if.debug_mode_q && (cov_assert_if.id_stage_pc == exception_addr_at_entry); + $rose(cov_assert_if.illegal_insn_i) && cov_assert_if.debug_mode_q && is_decoding_v1 |-> (decode_valid & cov_assert_if.id_valid) [->2] ##0 cov_assert_if.debug_mode_q && (cov_assert_if.id_stage_pc == exception_addr_at_entry); endproperty a_debug_mode_exception : assert property(p_debug_mode_exception) @@ -199,7 +205,7 @@ module uvmt_cv32e40p_debug_assert // ECALL in debug mode results in pc->dm_exception_addr_i property p_debug_mode_ecall; - $rose(cov_assert_if.ecall_insn_i) && cov_assert_if.debug_mode_q && cov_assert_if.is_decoding && cov_assert_if.id_stage_instr_valid_i + $rose(cov_assert_if.ecall_insn_i) && cov_assert_if.debug_mode_q && is_decoding_v1 && cov_assert_if.id_stage_instr_valid_i |-> (decode_valid & cov_assert_if.id_valid) [->1:3] ##0 cov_assert_if.debug_mode_q && (cov_assert_if.id_stage_pc == exception_addr_at_entry); endproperty @@ -411,7 +417,7 @@ module uvmt_cv32e40p_debug_assert else begin // Enter wfi if we have a valid instruction, not in debug mode and not // single stepping - if (cov_assert_if.is_wfi && !cov_assert_if.debug_mode_q && cov_assert_if.is_decoding && cov_assert_if.id_stage_instr_valid_i & !cov_assert_if.dcsr_q[2]) begin + if (cov_assert_if.is_wfi && !cov_assert_if.debug_mode_q && is_decoding_v1 && cov_assert_if.id_stage_instr_valid_i & !cov_assert_if.dcsr_q[2]) begin cov_assert_if.in_wfi <= 1'b1; end else if (cov_assert_if.pending_enabled_irq || cov_assert_if.debug_req_i) @@ -452,7 +458,7 @@ module uvmt_cv32e40p_debug_assert assign cov_assert_if.is_wfi = cov_assert_if.id_stage_instr_valid_i & cov_assert_if.id_valid & ((cov_assert_if.id_stage_instr_rdata_i & WFI_INSTR_MASK) == WFI_INSTR_DATA); assign cov_assert_if.pending_enabled_irq = |(cov_assert_if.irq_i & cov_assert_if.mie_q); - assign cov_assert_if.is_dret = cov_assert_if.id_valid & cov_assert_if.id_stage_instr_valid_i & cov_assert_if.is_decoding & (cov_assert_if.id_stage_instr_rdata_i == 32'h7B200073); + assign cov_assert_if.is_dret = cov_assert_if.id_valid & cov_assert_if.id_stage_instr_valid_i & is_decoding_v1 & (cov_assert_if.id_stage_instr_rdata_i == 32'h7B200073); // Track which debug cause should be expected always@ (posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin @@ -460,17 +466,18 @@ module uvmt_cv32e40p_debug_assert debug_cause_pri <= 3'b000; end else begin // Debug evaluated in decode state with valid instructions only - if((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE || cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP) & !cov_assert_if.debug_mode_q) begin - if(cov_assert_if.id_stage_instr_valid_i) begin + //if(cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE & !cov_assert_if.debug_mode_q) begin + if((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE || cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP)) begin + if(is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i) begin if(cov_assert_if.trigger_match_i) debug_cause_pri <= 3'b010; - else if(cov_assert_if.is_decoding & (cov_assert_if.dcsr_q[15]) & (cov_assert_if.is_ebreak | cov_assert_if.is_cebreak)) + else if((cov_assert_if.dcsr_q[15]) & (cov_assert_if.is_ebreak | cov_assert_if.is_cebreak)) debug_cause_pri <= 3'b001; else if(cov_assert_if.debug_req_i) debug_cause_pri <= 3'b011; - else if(cov_assert_if.is_decoding & cov_assert_if.dcsr_q[2]) + else if(cov_assert_if.dcsr_q[2]) debug_cause_pri <= 3'b100; - else if(cov_assert_if.is_decoding) + else debug_cause_pri <= 3'b000; end @@ -496,7 +503,7 @@ module uvmt_cv32e40p_debug_assert first_debug_ins <= 1'b0; if(cov_assert_if.debug_mode_q) begin if(!first_debug_ins_flag) begin - if(cov_assert_if.is_decoding & cov_assert_if.id_stage_instr_valid_i) begin + if(is_decoding_v1 & cov_assert_if.id_stage_instr_valid_i) begin first_debug_ins_flag <= 1'b1; first_debug_ins <= 1'b1; end From 66521ba70fe0e00aec7f8d131b440de4eb75e744 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 12 Dec 2023 17:49:56 +0100 Subject: [PATCH 30/97] Updated CORE hash. Signed-off-by: Pascal Gouedo --- cv32e40p/sim/ExternalRepos.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index fdbcc027d5..e51bb24e6f 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= 11e24901f5a6c8e265250d26d211c3ddfd3a502d +CV_CORE_HASH ?= d658f650c072bc429ef95aa631dfc186f56b7d4b CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. From 2c533f53fc9f33c190d55553cee4933fc4b7849a Mon Sep 17 00:00:00 2001 From: bsm Date: Wed, 13 Dec 2023 14:17:17 +0800 Subject: [PATCH 31/97] Fix ucdb merge issue which related to rtl path references Signed-off-by: bsm --- mk/uvmt/vsim.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk index d6c718c623..f4d651b318 100644 --- a/mk/uvmt/vsim.mk +++ b/mk/uvmt/vsim.mk @@ -150,6 +150,9 @@ ifeq ($(call IS_YES,$(COV)),YES) VLOG_FLAGS += +define+IMPERAS_COV endif endif +ifeq ($(call IS_YES,$(COV)),YES) +VLOG_FLAGS += -covermultiuserenv +endif ############################################################################### # VOPT (Optimization) From 59d8bde0a6014b1c39df476de9e4572f145e6134 Mon Sep 17 00:00:00 2001 From: bsm Date: Wed, 13 Dec 2023 16:32:21 +0800 Subject: [PATCH 32/97] Fix hwloop cvg issue for mix events with irq Signed-off-by: bsm --- .../env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 211 ++++++++++++------ cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv | 3 + cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 16 +- 3 files changed, 158 insertions(+), 72 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 5da622bcd2..95cd8da7e1 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -91,26 +91,29 @@ class uvme_rv32x_hwloop_covg # ( // PROPERTIES - START `define DEF_LOCAL_VARS(TYPE) \ - local s_csr_hwloop csr_hwloop_``TYPE = '{default:0}; \ - local s_hwloop_stat hwloop_stat_``TYPE = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; \ - local logic [31:0] prev_pc_rdata_``TYPE = '{default:0}; \ - local hwloop_evt_loc_t hwloop_evt_loc_``TYPE [HWLOOP_NB][hwloop_evt_t][$]; \ - local bit [(ILEN-1):0] insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ - local bit [(ILEN-1):0] mc_insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ - local bit [31:0] irq_vect_``TYPE [HWLOOP_NB][$]; \ - local bit done_insn_list_capture_``TYPE [HWLOOP_NB] = '{default:0}; \ - local s_hwloop_cov hwloop_cov_``TYPE [HWLOOP_NB] = '{default:0}; + local s_csr_hwloop csr_hwloop_``TYPE = '{default:0}; \ + local s_hwloop_stat hwloop_stat_``TYPE = '{default:0, hwloop_type:NULL_TYPE, hwloop_setup:'{default:NULL_SETUP}}; \ + local logic [31:0] prev_pc_rdata_``TYPE = '{default:0}; \ + local hwloop_evt_loc_t hwloop_evt_loc_``TYPE [HWLOOP_NB][hwloop_evt_t][$]; \ + local bit [(ILEN-1):0] insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ + local bit [(ILEN-1):0] mc_insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ + local bit [31:0] irq_vect_``TYPE [HWLOOP_NB][$]; \ + local bit done_insn_list_capture_``TYPE [HWLOOP_NB] = '{default:0}; \ + local bit done_insn_list_capture_d1_``TYPE [HWLOOP_NB] = '{default:0}; \ + local s_hwloop_cov hwloop_cov_``TYPE [HWLOOP_NB] = '{default:0}; `DEF_LOCAL_VARS(main) `DEF_LOCAL_VARS(sub) `DEF_LOCAL_VARS(init) - virtual uvmt_cv32e40p_rvvi_if #( .XLEN(XLEN), .ILEN(ILEN)) cv32e40p_rvvi_vif; - string _header = "XPULPV2_HWLOOP_COV"; - bit en_cvg_sampling = 1; - bit in_nested_loop0 = 0, in_nested_loop0_d1 = 0; - bit is_ebreak = 0, is_ebreakm = 0, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0, is_mc_insn = 0;; - bit enter_hwloop_sub = 0; + virtual uvmt_cv32e40p_rvvi_if #( .XLEN(XLEN), .ILEN(ILEN)) cv32e40p_rvvi_vif; + string _header = "XPULPV2_HWLOOP_COV"; + bit en_cvg_sampling = 1; + bit in_nested_loop0 = 0, in_nested_loop0_d1 = 0; + bit is_ebreak = 0, is_ebreakm = 0, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0, is_mc_insn = 0; + bit enter_hwloop_sub = 0; + bit pending_irq = 0; + logic [31:0] prev_irq_onehot_priority = 0, prev_irq_onehot_priority_always = 0; dcsr_cause_t dcsr_cause; exception_code_t exception_code; @@ -740,35 +743,35 @@ class uvme_rv32x_hwloop_covg # ( unique case (``EVT``) \ EXCP_EBREAK: begin \ hwloop_stat_main.excp_ebreak_cnt[``LOOP_IDX``]++; \ - if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPSTART); \ - else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPSTART_P4); \ - else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPEND); \ - else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPEND_M4); \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_LPEND_M4); \ else hwloop_evt_loc_main[``LOOP_IDX``][EXCP_EBREAK].push_back(LOC_OTHERS); \ end \ EXCP_ECALL : begin \ hwloop_stat_main.excp_ecall_cnt[``LOOP_IDX``]++; \ - if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPSTART); \ - else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPSTART_P4); \ - else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPEND); \ - else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPEND_M4); \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_LPEND_M4); \ else hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ECALL].push_back(LOC_OTHERS); \ end \ EXCP_ILLEGAL : begin \ hwloop_stat_main.excp_illegal_cnt[``LOOP_IDX``]++; \ - if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPSTART); \ - else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPSTART_P4); \ - else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPEND); \ - else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, cv32e40p_rvvi_vif.pc_rdata)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPEND_M4); \ + if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPSTART); \ + else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPSTART_P4); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPEND); \ + else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_LPEND_M4); \ else hwloop_evt_loc_main[``LOOP_IDX``][EXCP_ILLEGAL].push_back(LOC_OTHERS); \ end \ IS_IRQ : begin \ - is_irq = 1; irq_vect_main[``LOOP_IDX``].push_back(cv32e40p_rvvi_vif.irq_onehot_priority); \ if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPSTART); \ else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPSTART_P4); \ else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPEND); \ else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_LPEND_M4); \ else hwloop_evt_loc_main[``LOOP_IDX``][IS_IRQ].push_back(LOC_OTHERS); \ + irq_vect_main[``LOOP_IDX``].push_back(prev_irq_onehot_priority); \ end \ DBG_HALTREQ : begin \ is_dbg_mode = 1; hwloop_stat_main.dbg_haltreq_cnt[``LOOP_IDX``]++; \ @@ -885,6 +888,7 @@ class uvme_rv32x_hwloop_covg # ( end // UPDATE_HWLOOP_STAT \ for (int i=0; idbg); currently commented out due to pending for implementation + if (pc_is_mtvec_base_addr() && !is_mcause_irq()) begin : EXCEPTION_ENTRY + for (int i=0; idbg); currently commented out due to pending for implementation // `CHECK_N_SAMPLE_CSR_HWLOOP(sub); // `CHECK_N_SAMPLE_HWLOOP(sub); + // [optional] todo: mie has effect on irq during exception. Current hwloop tests do not exercise nested irq with mie enabled + check_exception_exit(); if (!(is_ebreak || is_ecall || is_illegal)) enter_hwloop_sub = 0; end + else begin : MAIN - if (is_irq && cv32e40p_rvvi_vif.insn[6:0] == OPCODE_JAL) begin wait (!is_irq); continue; end - if (is_dbg_mode) begin wait (!is_dbg_mode); continue; end + if (pc_is_mtvec_base_addr() && is_mcause_irq()) begin : IRQ_ENTRY + if (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]) begin + pending_irq = 0; + `IF_CURRENT_IS_MAIN_HWLOOP(0, IS_IRQ) + `IF_CURRENT_IS_MAIN_HWLOOP(1, IS_IRQ) + update_prev_irq_onehot_priority(); + is_irq = 1; wait (!is_irq); continue; + end // IRQ_ENTRY + end + if (is_dbg_mode) begin wait (!is_dbg_mode); continue; end if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == INSTR_EBREAK) is_ebreakm = 1; else is_ebreakm = 0; `CHECK_N_SAMPLE_CSR_HWLOOP(main); `CHECK_N_SAMPLE_HWLOOP(main); if (is_ebreak || is_ecall || is_illegal) enter_hwloop_sub = 1; prev_pc_rdata_main = cv32e40p_rvvi_vif.pc_rdata; end + end // VALID_DETECTED end // forever diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index 4d0e52d0ee..85caa2183b 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -548,13 +548,16 @@ module uvmt_cv32e40p_tb; .pc_rdata (dut_wrap.cv32e40p_tb_wrapper_i.rvfi_i.rvfi_pc_rdata), .interrupt_if (interrupt_if), .debug_if (debug_if), + .wa_csr_mip (dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mip), `PORTMAP_CSR_RVFI_2_RVVI(lpstart0) `PORTMAP_CSR_RVFI_2_RVVI(lpend0) `PORTMAP_CSR_RVFI_2_RVVI(lpcount0) `PORTMAP_CSR_RVFI_2_RVVI(lpstart1) `PORTMAP_CSR_RVFI_2_RVVI(lpend1) `PORTMAP_CSR_RVFI_2_RVVI(lpcount1) + `PORTMAP_CSR_RVFI_2_RVVI(mstatus) `PORTMAP_CSR_RVFI_2_RVVI(mie) + `PORTMAP_CSR_RVFI_2_RVVI(mtvec) `PORTMAP_CSR_RVFI_2_RVVI(mcause) `PORTMAP_CSR_RVFI_2_RVVI(mip) `PORTMAP_CSR_RVFI_2_RVVI(dcsr) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index b87ae3767d..d1e4e05524 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -390,6 +390,7 @@ interface uvmt_cv32e40p_rvvi_if #( input logic [(ILEN-1):0] insn, input trap, input logic [31:0] pc_rdata, + input logic [31:0] wa_csr_mip, uvma_interrupt_if interrupt_if, uvma_debug_if debug_if, @@ -401,7 +402,9 @@ interface uvmt_cv32e40p_rvvi_if #( `DEF_CSR_PORTS(lpstart1) `DEF_CSR_PORTS(lpend1) `DEF_CSR_PORTS(lpcount1) + `DEF_CSR_PORTS(mstatus) `DEF_CSR_PORTS(mie) + `DEF_CSR_PORTS(mtvec) `DEF_CSR_PORTS(mcause) `DEF_CSR_PORTS(mip) `DEF_CSR_PORTS(dcsr) @@ -419,9 +422,14 @@ interface uvmt_cv32e40p_rvvi_if #( wire [31:0] csr_trig_pc; logic [31:0] irq_onehot_priority; + logic [31:0] mtvec_base_addr; + logic [31:0] mip; - assign valid_irq = csr[`CSR_MIP_ADDR] & csr[`CSR_MIE_ADDR]; // fixme: rvfi misses mip (pending for resolution) + // assign valid_irq = csr[`CSR_MIP_ADDR] & csr[`CSR_MIE_ADDR]; // fixme: rvfi misses mip (pending rvfi fixes; workaround probe rtl signals - wa_csr_mip) + assign valid_irq = wa_csr_mip & csr[`CSR_MIE_ADDR]; assign dbg_req = debug_if.debug_req; + assign mie = csr[`CSR_MSTATUS_ADDR][3]; + assign mip = csr[`CSR_MIP_ADDR]; assign csr_mcause_irq = csr[`CSR_MCAUSE_ADDR][31]; assign csr_mcause_ecp_code = csr[`CSR_MCAUSE_ADDR][4:0]; @@ -432,6 +440,8 @@ interface uvmt_cv32e40p_rvvi_if #( assign csr_trig_execute = csr[`CSR_TDATA1_ADDR][2]; assign csr_trig_pc = csr[`CSR_TDATA2_ADDR]; + assign mtvec_base_addr = {csr[`CSR_MTVEC_ADDR][31:8], 8'h0}; + // can be expanded. Currently only define for current usage `ASSIGN_CSR_N_WB(`CSR_LPSTART0_ADDR, lpstart0) `ASSIGN_CSR_N_WB(`CSR_LPEND0_ADDR, lpend0) @@ -439,14 +449,16 @@ interface uvmt_cv32e40p_rvvi_if #( `ASSIGN_CSR_N_WB(`CSR_LPSTART1_ADDR, lpstart1) `ASSIGN_CSR_N_WB(`CSR_LPEND1_ADDR, lpend1) `ASSIGN_CSR_N_WB(`CSR_LPCOUNT1_ADDR, lpcount1) + `ASSIGN_CSR_N_WB(`CSR_MSTATUS_ADDR, mstatus) `ASSIGN_CSR_N_WB(`CSR_MIE_ADDR, mie) + `ASSIGN_CSR_N_WB(`CSR_MTVEC_ADDR, mtvec) `ASSIGN_CSR_N_WB(`CSR_MCAUSE_ADDR, mcause) `ASSIGN_CSR_N_WB(`CSR_MIP_ADDR, mip) `ASSIGN_CSR_N_WB(`CSR_DCSR_ADDR, dcsr) `ASSIGN_CSR_N_WB_VEC(`CSR_TDATA1_ADDR, tdata, 1); `ASSIGN_CSR_N_WB_VEC(`CSR_TDATA2_ADDR, tdata, 2); - // irq_onehot_priority assignment + // irq_onehot_priority assignment (refer cv32e40p user manual, section 10.2) // priority order (high->low) is irq[31]...irq[16], irq[11], irq[3], irq[7] always @(valid_irq) begin irq_onehot_priority = 0; From e7c96e3ed2adf61531b8d1431f745de178d3045b Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Wed, 13 Dec 2023 13:42:49 +0100 Subject: [PATCH 33/97] Added mstatus.fs write to initial state before fcsr clear. Signed-off-by: Pascal Gouedo --- cv32e40p/tests/programs/custom/fpu_bugs_test/test.c | 6 ++++-- .../tests/programs/custom/interrupt_test/interrupt_test.c | 7 +++++-- cv32e40p/tests/programs/custom/matmul_32b_float/test.c | 8 +++++--- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c index 22e3b036c8..94a994e431 100644 --- a/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c +++ b/cv32e40p/tests/programs/custom/fpu_bugs_test/test.c @@ -27,9 +27,11 @@ void fp_enable () { unsigned int fs = MSTATUS_FS_INITIAL; - asm volatile("csrwi fcsr, 0;" + asm volatile("csrs mstatus, %0;" + "csrwi fcsr, 0;" "csrs mstatus, %0;" - : : "r"(fs)); + : : "r"(fs) + ); } const long int INPUT[10] __attribute__ ((aligned (4))) = { diff --git a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c index 55c8d9bf7f..7192b1ba36 100644 --- a/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c +++ b/cv32e40p/tests/programs/custom/interrupt_test/interrupt_test.c @@ -46,9 +46,12 @@ void fp_enable () { unsigned int fs = MSTATUS_FS_INITIAL; - asm volatile("csrwi fcsr, 0;" + asm volatile("csrs mstatus, %0;" + "csrwi fcsr, 0;" "csrs mstatus, %0;" - : : "r"(fs)); + : : "r"(fs) + ); + } #endif diff --git a/cv32e40p/tests/programs/custom/matmul_32b_float/test.c b/cv32e40p/tests/programs/custom/matmul_32b_float/test.c index dec8c307d2..0bdbd3e3fb 100644 --- a/cv32e40p/tests/programs/custom/matmul_32b_float/test.c +++ b/cv32e40p/tests/programs/custom/matmul_32b_float/test.c @@ -48,9 +48,11 @@ void fp_enable () { unsigned int fs = MSTATUS_FS_INITIAL; - __asm__ volatile("csrwi fcsr, 0;" - "csrs mstatus, %0;" - : : "r"(fs)); + asm volatile("csrs mstatus, %0;" + "csrwi fcsr, 0;" + "csrs mstatus, %0;" + : : "r"(fs) + ); } #endif From 5a761c6a98fd26bd72803a55ba1f38afad82e035 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 14 Dec 2023 19:18:22 +0100 Subject: [PATCH 34/97] Another fix for debug assertion (trigger match and branch). Signed-off-by: Pascal Gouedo --- cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv | 5 ++++- cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv | 3 +++ cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 7 +++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv index 41bdca2a7e..81443d3820 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_debug_assert.sv @@ -53,7 +53,10 @@ module uvmt_cv32e40p_debug_assert // --------------------------------------------------------------------------- assign is_decoding_v1 = cov_assert_if.is_decoding || - ((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE || cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP) && + (((cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE && !cov_assert_if.branch_taken_ex_i && + !cov_assert_if.data_err_i && !cov_assert_if.is_fetch_failed_i) || + cov_assert_if.ctrl_fsm_cs == cv32e40p_pkg::DECODE_HWLOOP + ) && cov_assert_if.id_stage_instr_valid_i && (cov_assert_if.debug_req_i || cov_assert_if.trigger_match_i) && !cov_assert_if.debug_mode_q ); diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index 85caa2183b..1eadb26c26 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -441,6 +441,9 @@ module uvmt_cv32e40p_tb; .id_stage_is_compressed(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.is_compressed_i), .id_valid(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.id_valid_i), .is_decoding(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.is_decoding_o), + .branch_taken_ex_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.branch_taken_ex_i), + .data_err_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.data_err_i), + .is_fetch_failed_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.is_fetch_failed_i), .id_stage_pc(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.pc_id_i), .if_stage_pc(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.if_stage_i.pc_if_o), .mie_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.mie_q), diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index d1e4e05524..95f6f301ce 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -207,6 +207,9 @@ interface uvmt_cv32e40p_debug_cov_assert_if input [31:0] id_stage_pc, // Program counter in decode input [31:0] if_stage_pc, // Program counter in fetch input is_decoding, + input branch_taken_ex_i, + input data_err_i, + input is_fetch_failed_i, input id_valid, input wire ctrl_state_e ctrl_fsm_cs, // Controller FSM states with debug_req input illegal_insn_i, @@ -283,6 +286,10 @@ interface uvmt_cv32e40p_debug_cov_assert_if id_stage_is_compressed, id_stage_pc, if_stage_pc, + is_decoding, + branch_taken_ex_i, + is_fetch_failed_i, + id_valid, ctrl_fsm_cs, illegal_insn_i, illegal_insn_q, From 3dbad3a87e920ded02907d2c558c23ec6b4e6907 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 16:11:46 +0800 Subject: [PATCH 35/97] remove coverpoint and crosses related to if_stage Signed-off-by: Vaibhav Jain --- .../uvme/cov/uvme_cv32e40p_fp_instr_covg.sv | 34 ------------------- 1 file changed, 34 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv index 8692889f61..4e17406034 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv @@ -99,11 +99,6 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `per_instance_fcov option.at_least = 10; - cp_if_stage_f_inst : coverpoint `COVIF_CB.if_stage_instr_rdata_i iff (`COVIF_CB.if_stage_instr_rvalid_i == 1) { - `RV32F_INSTR_BINS - option.weight = 5; - } - cp_id_stage_f_inst : coverpoint `COVIF_CB.id_stage_instr_rdata_i iff (`COVIF_CB.id_stage_instr_valid_i == 1) { `RV32F_INSTR_BINS option.weight = 5; @@ -146,11 +141,6 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; option.weight = 1; } - cp_if_stage_inst_valid : coverpoint `COVIF_CB.if_stage_instr_rvalid_i { - bins if_stage_instr_valid = {1}; - option.weight = 1; - } - cp_id_stage_apu_en_ex_o : coverpoint `COVIF_CB.id_stage_apu_en_ex_o { bins id_stage_apu_en_ex_1 = {1}; bins id_stage_apu_en_ex_0_to_1 = (0 => 1); @@ -253,30 +243,6 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES } - // cross coverage for F-inst at IF-stage with preceeding F-multicycle instr - cr_f_inst_at_if_stage_inp_with_fpu_multicycle_req : cross cp_if_stage_f_inst, - cp_curr_fpu_apu_op_at_apu_req - {option.weight = 50;} - - // cross coverage for F-inst at IF-stage with preceeding F-multicycle - // case with apu_busy or APU needing more than 1 clock cycle - cr_f_inst_at_if_stage_inp_while_fpu_busy : cross cp_if_stage_f_inst, - cp_curr_fpu_apu_op_multicycle { - option.weight = 50; - `FPU_ZERO_LATENCY_ILLEGAL_BUSY - } - - // cross coverage for F-inst arriving at IF-stage output at various stages of - // APU latency clk-cycles of the ongoing/preceeding F-multicycle instr - cr_f_inst_at_if_stage_inp_with_cyc_window_of_ongoing_fpu_calc : cross cp_if_stage_f_inst, - cp_f_multicycle_clk_window, - cp_curr_fpu_apu_op, - cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall { - - option.weight = 50; - `FPU_MULTICYCLE_WINDOW_ILLEGAL_CASES - } - endgroup : cg_f_multicycle From b5d0b683c3170e867e11a91dcc7d0f25ce1ab864 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 16:15:20 +0800 Subject: [PATCH 36/97] checked for coverage sampling excluded for debug mode and debug scenarios Signed-off-by: Vaibhav Jain --- .../env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv | 15 +++++++++------ cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv | 6 +++++- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv index 4e17406034..05fb95ee2e 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv @@ -180,10 +180,10 @@ class uvme_cv32e40p_fp_instr_covg extends uvm_component; option.weight = 5; } - cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall : coverpoint ((cntxt.cov_vif.is_mulh_ex == 0) && - (cntxt.cov_vif.is_misaligned_data_req_ex == 0) && - (cntxt.cov_vif.is_post_inc_ld_st_inst_ex == 0) && - (cntxt.cov_vif.ex_apu_valid_memorised == 0)) { + cp_fpu_lat_0_and_2_ex_regfile_alu_wr_no_stall : coverpoint ((`COVIF_CB.is_mulh_ex == 0) && + (`COVIF_CB.is_misaligned_data_req_ex == 0) && + (`COVIF_CB.is_post_inc_ld_st_inst_ex == 0) && + (`COVIF_CB.ex_apu_valid_memorised == 0)) { bins no_alu_wr_stall = {1}; option.weight = 1; @@ -808,7 +808,10 @@ endtask : run_phase task uvme_cv32e40p_fp_instr_covg::sample_clk_i(); while (1) begin @(`COVIF_CB); - cg_f_multicycle.sample(); - cg_f_inst_reg.sample(); + if ((`COVIF_CB.debug_req_i == 0) && (`COVIF_CB.debug_mode_q == 0) && + (`COVIF_CB.trigger_match_i == 0) && (cntxt.debug_cov_vif.mon_cb.dcsr_q[2] == 0)) begin // Only sample in M-mode without debug entry cases + cg_f_multicycle.sample(); + cg_f_inst_reg.sample(); + end end endtask : sample_clk_i diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv index 1eadb26c26..16c8fd73ae 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb.sv @@ -535,7 +535,11 @@ module uvmt_cv32e40p_tb; .ex_data_rvalid_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.data_rvalid_i), .ex_regfile_alu_we_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.regfile_alu_we_i), .ex_apu_valid(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_valid), - .ex_apu_rvalid_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_rvalid_q) + .ex_apu_rvalid_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.ex_stage_i.apu_rvalid_q), + .debug_req_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.debug_req_pending), + .debug_mode_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.debug_mode_q), + .dcsr_q(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.cs_registers_i.dcsr_q), + .trigger_match_i(dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i.id_stage_i.controller_i.trigger_match_i) ); // Instantiate debug assertions From bd6630fdfe47ea19020b95f1fdf99802a1679d93 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 16:17:26 +0800 Subject: [PATCH 37/97] split hwloop instr for 0 and 1 and cv_sle cv_sleu update Signed-off-by: Vaibhav Jain --- cv32e40p/env/uvme/uvme_cv32e40p_constants.sv | 28 +++++++++++++------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv b/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv index 1815475bcc..9c089cfbee 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv @@ -148,14 +148,22 @@ parameter INSTR_CV_SB_RR = {7'b0010100, 5'b?, 5'b?, 3'b011, 5'b?, parameter INSTR_CV_SH_RR = {7'b0010101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_SW_RR = {7'b0010110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_STARTI = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_START = {12'b0, 5'b?????, 3'b100, 4'b0001, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_ENDI = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_END = {12'b0, 5'b?????, 3'b100, 4'b0011, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_COUNTI = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_COUNT = {12'b0, 5'b?????, 3'b100, 4'b0101, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_SETUPI = {12'b?, 5'b?????, 3'b100, 4'b0110, 1'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_SETUP = {12'b?, 5'b?????, 3'b100, 4'b0111, 1'b?, OPCODE_CUSTOM_1}; +parameter INSTR_CV_STARTI_0 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_START_0 = {12'b0, 5'b?????, 3'b100, 4'b0001, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_ENDI_0 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_END_0 = {12'b0, 5'b?????, 3'b100, 4'b0011, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_COUNTI_0 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_COUNT_0 = {12'b0, 5'b?????, 3'b100, 4'b0101, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SETUPI_0 = {12'b?, 5'b?????, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SETUP_0 = {12'b?, 5'b?????, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1}; +parameter INSTR_CV_STARTI_1 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_START_1 = {12'b0, 5'b?????, 3'b100, 4'b0001, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_ENDI_1 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_END_1 = {12'b0, 5'b?????, 3'b100, 4'b0011, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_COUNTI_1 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_COUNT_1 = {12'b0, 5'b?????, 3'b100, 4'b0101, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SETUPI_1 = {12'b?, 5'b?????, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SETUP_1 = {12'b?, 5'b?????, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1}; parameter INSTR_CV_EXTRACTR = {7'b0011000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_EXTRACTUR = {7'b0011001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; @@ -169,8 +177,8 @@ parameter INSTR_CV_CLB = {7'b0100011, 5'b0, 5'b?, 3'b011, 5'b?, parameter INSTR_CV_CNT = {7'b0100100, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_ABS = {7'b0101000, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_SLET = {7'b0101001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; -parameter INSTR_CV_SLETU = {7'b0101010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SLE = {7'b0101001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; +parameter INSTR_CV_SLEU = {7'b0101010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_MIN = {7'b0101011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_MINU = {7'b0101100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; parameter INSTR_CV_MAX = {7'b0101101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; From 1903163ec08882b7eee1c9519f280866ddab88c6 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 16:28:36 +0800 Subject: [PATCH 38/97] replace instr wildcard bins with macros Signed-off-by: Vaibhav Jain --- cv32e40p/env/uvme/cov/uvme_debug_covg.sv | 361 +--------------------- cv32e40p/env/uvme/uvme_cv32e40p_macros.sv | 329 ++++++++++++++++++++ 2 files changed, 342 insertions(+), 348 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv index a1701d3822..2f36153387 100644 --- a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv @@ -428,61 +428,42 @@ class uvme_debug_covg extends uvm_component; covergroup cg_debug_with_f_inst; `per_instance_fcov + dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { bins dbg_req_active = {1'b1}; bins dbg_req_0_to_1 = (0 => 1); } + step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins debug_step_mode_set = {1'b1}; } + ebreak: coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { bins ebreak_ex = {1}; } + cebreak : coverpoint cntxt.debug_cov_vif.mon_cb.is_cebreak { bins cebreak_ex= {1'b1}; } + ebreakm_set: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[15] { bins ebreakm_is_set = {1}; } + dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins in_debug_mode = {1}; } + irq : coverpoint |cntxt.debug_cov_vif.mon_cb.irq_i { bins irq_trans_0_to_1 = (1'b0 => 1'b1); } + ill : coverpoint cntxt.debug_cov_vif.mon_cb.illegal_insn_i { bins ill_inst_hit = {1}; } f_inst : coverpoint cntxt.debug_cov_vif.mon_cb.rvfi_insn { - wildcard bins fadd = {cv32e40p_tracer_pkg::INSTR_FADD}; - wildcard bins fsub = {cv32e40p_tracer_pkg::INSTR_FSUB}; - wildcard bins fmul = {cv32e40p_tracer_pkg::INSTR_FMUL}; - wildcard bins fdiv = {cv32e40p_tracer_pkg::INSTR_FDIV}; - wildcard bins fsqrt = {cv32e40p_tracer_pkg::INSTR_FSQRT}; - wildcard bins fsgnjs = {cv32e40p_tracer_pkg::INSTR_FSGNJS}; - wildcard bins fsgnjns = {cv32e40p_tracer_pkg::INSTR_FSGNJNS}; - wildcard bins fsgnjxs = {cv32e40p_tracer_pkg::INSTR_FSGNJXS}; - wildcard bins fmin = {cv32e40p_tracer_pkg::INSTR_FMIN}; - wildcard bins fmax = {cv32e40p_tracer_pkg::INSTR_FMAX}; - wildcard bins fcvtws = {cv32e40p_tracer_pkg::INSTR_FCVTWS}; - wildcard bins fcvtwus = {cv32e40p_tracer_pkg::INSTR_FCVTWUS}; - wildcard bins fmvxs = {cv32e40p_tracer_pkg::INSTR_FMVXS}; - wildcard bins feqs = {cv32e40p_tracer_pkg::INSTR_FEQS}; - wildcard bins flts = {cv32e40p_tracer_pkg::INSTR_FLTS}; - wildcard bins fles = {cv32e40p_tracer_pkg::INSTR_FLES}; - wildcard bins fclass = {cv32e40p_tracer_pkg::INSTR_FCLASS}; - wildcard bins fcvtsw = {cv32e40p_tracer_pkg::INSTR_FCVTSW}; - wildcard bins fcvtswu = {cv32e40p_tracer_pkg::INSTR_FCVTSWU}; - wildcard bins fmvsw = {cv32e40p_tracer_pkg::INSTR_FMVSX}; - wildcard bins fmadd = {cv32e40p_tracer_pkg::INSTR_FMADD}; - wildcard bins fmsub = {cv32e40p_tracer_pkg::INSTR_FMSUB}; - wildcard bins fnmsub = {cv32e40p_tracer_pkg::INSTR_FNMSUB}; - wildcard bins fnmadd = {cv32e40p_tracer_pkg::INSTR_FNMADD}; - } - - rvfi_valid : coverpoint cntxt.debug_cov_vif.mon_cb.rvfi_valid { - bins rvfi_valid = {1}; + `RV32F_INSTR_BINS } apu_req_valid : coverpoint cntxt.debug_cov_vif.mon_cb.apu_req { @@ -529,338 +510,22 @@ class uvme_debug_covg extends uvm_component; covergroup cg_debug_with_xpulp_inst; `per_instance_fcov + dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { bins dbg_req_active = {1'b1}; bins dbg_req_0_to_1 = (0 => 1); } + step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins debug_step_mode_set = {1'b1}; } + dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins in_debug_mode = {1}; } xpulp_instruction : coverpoint cntxt.debug_cov_vif.mon_cb.rvfi_insn { - wildcard bins cv_lb_pi_ri = {INSTR_CV_LB_PI_RI}; - wildcard bins cv_lh_pi_ri = {INSTR_CV_LH_PI_RI}; - wildcard bins cv_lw_pi_ri = {INSTR_CV_LW_PI_RI}; - wildcard bins cv_elw_pi_ri = {INSTR_CV_ELW_PI_RI}; - wildcard bins cv_lbu_pi_ri = {INSTR_CV_LBU_PI_RI}; - wildcard bins cv_lhu_pi_ri = {INSTR_CV_LHU_PI_RI}; - wildcard bins cv_beqimm = {INSTR_CV_BEQIMM}; - wildcard bins cv_bneimm = {INSTR_CV_BNEIMM}; - wildcard bins cv_lb_pi_rr = {INSTR_CV_LB_PI_RR}; - wildcard bins cv_lh_pi_rr = {INSTR_CV_LH_PI_RR}; - wildcard bins cv_lw_pi_rr = {INSTR_CV_LW_PI_RR}; - wildcard bins cv_lbu_pi_rr = {INSTR_CV_LBU_PI_RR}; - wildcard bins cv_lhu_pi_rr = {INSTR_CV_LHU_PI_RR}; - wildcard bins cv_lb_rr = {INSTR_CV_LB_RR}; - wildcard bins cv_lh_rr = {INSTR_CV_LH_RR}; - wildcard bins cv_lw_rr = {INSTR_CV_LW_RR}; - wildcard bins cv_lbu_rr = {INSTR_CV_LBU_RR}; - wildcard bins cv_lhu_rr = {INSTR_CV_LHU_RR}; - wildcard bins cv_sb_pi_ri = {INSTR_CV_SB_PI_RI}; - wildcard bins cv_sh_pi_ri = {INSTR_CV_SH_PI_RI}; - wildcard bins cv_sw_pi_ri = {INSTR_CV_SW_PI_RI}; - wildcard bins cv_sb_pi_rr = {INSTR_CV_SB_PI_RR}; - wildcard bins cv_sh_pi_rr = {INSTR_CV_SH_PI_RR}; - wildcard bins cv_sw_pi_rr = {INSTR_CV_SW_PI_RR}; - wildcard bins cv_sb_rr = {INSTR_CV_SB_RR}; - wildcard bins cv_sh_rr = {INSTR_CV_SH_RR}; - wildcard bins cv_sw_rr = {INSTR_CV_SW_RR}; - wildcard bins cv_starti = {INSTR_CV_STARTI}; - wildcard bins cv_start = {INSTR_CV_START}; - wildcard bins cv_endi = {INSTR_CV_ENDI}; - wildcard bins cv_end = {INSTR_CV_END}; - wildcard bins cv_counti = {INSTR_CV_COUNTI}; - wildcard bins cv_count = {INSTR_CV_COUNT}; - wildcard bins cv_setupi = {INSTR_CV_SETUPI}; - wildcard bins cv_setup = {INSTR_CV_SETUP}; - wildcard bins cv_extractr = {INSTR_CV_EXTRACTR}; - wildcard bins cv_extractur = {INSTR_CV_EXTRACTUR}; - wildcard bins cv_insertr = {INSTR_CV_INSERTR}; - wildcard bins cv_bclrr = {INSTR_CV_BCLRR}; - wildcard bins cv_bsetr = {INSTR_CV_BSETR}; - wildcard bins cv_ror = {INSTR_CV_ROR}; - wildcard bins cv_ff1 = {INSTR_CV_FF1}; - wildcard bins cv_fl1 = {INSTR_CV_FL1}; - wildcard bins cv_clb = {INSTR_CV_CLB}; - wildcard bins cv_cnt = {INSTR_CV_CNT}; - wildcard bins cv_abs = {INSTR_CV_ABS}; - wildcard bins cv_slet = {INSTR_CV_SLET}; - wildcard bins cv_sletu = {INSTR_CV_SLETU}; - wildcard bins cv_min = {INSTR_CV_MIN}; - wildcard bins cv_minu = {INSTR_CV_MINU}; - wildcard bins cv_max = {INSTR_CV_MAX}; - wildcard bins cv_maxu = {INSTR_CV_MAXU}; - wildcard bins cv_exths = {INSTR_CV_EXTHS}; - wildcard bins cv_exthz = {INSTR_CV_EXTHZ}; - wildcard bins cv_extbs = {INSTR_CV_EXTBS}; - wildcard bins cv_extbz = {INSTR_CV_EXTBZ}; - wildcard bins cv_clip = {INSTR_CV_CLIP}; - wildcard bins cv_clipu = {INSTR_CV_CLIPU}; - wildcard bins cv_clipr = {INSTR_CV_CLIPR}; - wildcard bins cv_clipur = {INSTR_CV_CLIPUR}; - wildcard bins cv_addnr = {INSTR_CV_ADDNR}; - wildcard bins cv_addunr = {INSTR_CV_ADDUNR}; - wildcard bins cv_addrnr = {INSTR_CV_ADDRNR}; - wildcard bins cv_addurnr = {INSTR_CV_ADDURNR}; - wildcard bins cv_subnr = {INSTR_CV_SUBNR}; - wildcard bins cv_subunr = {INSTR_CV_SUBUNR}; - wildcard bins cv_subrnr = {INSTR_CV_SUBRNR}; - wildcard bins cv_suburnr = {INSTR_CV_SUBURNR}; - wildcard bins cv_mac = {INSTR_CV_MAC}; - wildcard bins cv_msu = {INSTR_CV_MSU}; - wildcard bins cv_extract = {INSTR_CV_EXTRACT}; - wildcard bins cv_extractu = {INSTR_CV_EXTRACTU}; - wildcard bins cv_insert = {INSTR_CV_INSERT}; - wildcard bins cv_bclr = {INSTR_CV_BCLR}; - wildcard bins cv_bset = {INSTR_CV_BSET}; - wildcard bins cv_bitrev = {INSTR_CV_BITREV}; - wildcard bins cv_addn = {INSTR_CV_ADDN}; - wildcard bins cv_addun = {INSTR_CV_ADDUN}; - wildcard bins cv_addrn = {INSTR_CV_ADDRN}; - wildcard bins cv_addurn = {INSTR_CV_ADDURN}; - wildcard bins cv_subn = {INSTR_CV_SUBN}; - wildcard bins cv_subun = {INSTR_CV_SUBUN}; - wildcard bins cv_subrn = {INSTR_CV_SUBRN}; - wildcard bins cv_suburn = {INSTR_CV_SUBURN}; - wildcard bins cv_mulsn = {INSTR_CV_MULSN}; - wildcard bins cv_mulhhsn = {INSTR_CV_MULHHSN}; - wildcard bins cv_mulsrn = {INSTR_CV_MULSRN}; - wildcard bins cv_mulhhsrn = {INSTR_CV_MULHHSRN}; - wildcard bins cv_mulun = {INSTR_CV_MULUN}; - wildcard bins cv_mulhhun = {INSTR_CV_MULHHUN}; - wildcard bins cv_mulurn = {INSTR_CV_MULURN}; - wildcard bins cv_mulhhurn = {INSTR_CV_MULHHURN}; - wildcard bins cv_macsn = {INSTR_CV_MACSN}; - wildcard bins cv_machhsn = {INSTR_CV_MACHHSN}; - wildcard bins cv_macsrn = {INSTR_CV_MACSRN}; - wildcard bins cv_machhsrn = {INSTR_CV_MACHHSRN}; - wildcard bins cv_macun = {INSTR_CV_MACUN}; - wildcard bins cv_machhun = {INSTR_CV_MACHHUN}; - wildcard bins cv_macurn = {INSTR_CV_MACURN}; - wildcard bins cv_machhurn = {INSTR_CV_MACHHURN}; - wildcard bins cv_add_h = {INSTR_CV_ADD_H}; - wildcard bins cv_add_sc_h = {INSTR_CV_ADD_SC_H}; - wildcard bins cv_add_sci_h = {INSTR_CV_ADD_SCI_H}; - wildcard bins cv_add_b = {INSTR_CV_ADD_B}; - wildcard bins cv_add_sc_b = {INSTR_CV_ADD_SC_B}; - wildcard bins cv_add_sci_b = {INSTR_CV_ADD_SCI_B}; - wildcard bins cv_sub_h = {INSTR_CV_SUB_H}; - wildcard bins cv_sub_sc_h = {INSTR_CV_SUB_SC_H}; - wildcard bins cv_sub_sci_h = {INSTR_CV_SUB_SCI_H}; - wildcard bins cv_sub_b = {INSTR_CV_SUB_B}; - wildcard bins cv_sub_sc_b = {INSTR_CV_SUB_SC_B}; - wildcard bins cv_sub_sci_b = {INSTR_CV_SUB_SCI_B}; - wildcard bins cv_avg_h = {INSTR_CV_AVG_H}; - wildcard bins cv_avg_sc_h = {INSTR_CV_AVG_SC_H}; - wildcard bins cv_avg_sci_h = {INSTR_CV_AVG_SCI_H}; - wildcard bins cv_avg_b = {INSTR_CV_AVG_B}; - wildcard bins cv_avg_sc_b = {INSTR_CV_AVG_SC_B}; - wildcard bins cv_avg_sci_b = {INSTR_CV_AVG_SCI_B}; - wildcard bins cv_avgu_h = {INSTR_CV_AVGU_H}; - wildcard bins cv_avgu_sc_h = {INSTR_CV_AVGU_SC_H}; - wildcard bins cv_avgu_sci_h = {INSTR_CV_AVGU_SCI_H}; - wildcard bins cv_avgu_b = {INSTR_CV_AVGU_B}; - wildcard bins cv_avgu_sc_b = {INSTR_CV_AVGU_SC_B}; - wildcard bins cv_avgu_sci_b = {INSTR_CV_AVGU_SCI_B}; - wildcard bins cv_min_h = {INSTR_CV_MIN_H}; - wildcard bins cv_min_sc_h = {INSTR_CV_MIN_SC_H}; - wildcard bins cv_min_sci_h = {INSTR_CV_MIN_SCI_H}; - wildcard bins cv_min_b = {INSTR_CV_MIN_B}; - wildcard bins cv_min_sc_b = {INSTR_CV_MIN_SC_B}; - wildcard bins cv_min_sci_b = {INSTR_CV_MIN_SCI_B}; - wildcard bins cv_minu_h = {INSTR_CV_MINU_H}; - wildcard bins cv_minu_sc_h = {INSTR_CV_MINU_SC_H}; - wildcard bins cv_minu_sci_h = {INSTR_CV_MINU_SCI_H}; - wildcard bins cv_minu_b = {INSTR_CV_MINU_B}; - wildcard bins cv_minu_sc_b = {INSTR_CV_MINU_SC_B}; - wildcard bins cv_minu_sci_b = {INSTR_CV_MINU_SCI_B}; - wildcard bins cv_max_h = {INSTR_CV_MAX_H}; - wildcard bins cv_max_sc_h = {INSTR_CV_MAX_SC_H}; - wildcard bins cv_max_sci_h = {INSTR_CV_MAX_SCI_H}; - wildcard bins cv_max_b = {INSTR_CV_MAX_B}; - wildcard bins cv_max_sc_b = {INSTR_CV_MAX_SC_B}; - wildcard bins cv_max_sci_b = {INSTR_CV_MAX_SCI_B}; - wildcard bins cv_maxu_h = {INSTR_CV_MAXU_H}; - wildcard bins cv_maxu_sc_h = {INSTR_CV_MAXU_SC_H}; - wildcard bins cv_maxu_sci_h = {INSTR_CV_MAXU_SCI_H}; - wildcard bins cv_maxu_b = {INSTR_CV_MAXU_B}; - wildcard bins cv_maxu_sc_b = {INSTR_CV_MAXU_SC_B}; - wildcard bins cv_maxu_sci_b = {INSTR_CV_MAXU_SCI_B}; - wildcard bins cv_srl_h = {INSTR_CV_SRL_H}; - wildcard bins cv_srl_sc_h = {INSTR_CV_SRL_SC_H}; - wildcard bins cv_srl_sci_h = {INSTR_CV_SRL_SCI_H}; - wildcard bins cv_srl_b = {INSTR_CV_SRL_B}; - wildcard bins cv_srl_sc_b = {INSTR_CV_SRL_SC_B}; - wildcard bins cv_srl_sci_b = {INSTR_CV_SRL_SCI_B}; - wildcard bins cv_sra_h = {INSTR_CV_SRA_H}; - wildcard bins cv_sra_sc_h = {INSTR_CV_SRA_SC_H}; - wildcard bins cv_sra_sci_h = {INSTR_CV_SRA_SCI_H}; - wildcard bins cv_sra_b = {INSTR_CV_SRA_B}; - wildcard bins cv_sra_sc_b = {INSTR_CV_SRA_SC_B}; - wildcard bins cv_sra_sci_b = {INSTR_CV_SRA_SCI_B}; - wildcard bins cv_sll_h = {INSTR_CV_SLL_H}; - wildcard bins cv_sll_sc_h = {INSTR_CV_SLL_SC_H}; - wildcard bins cv_sll_sci_h = {INSTR_CV_SLL_SCI_H}; - wildcard bins cv_sll_b = {INSTR_CV_SLL_B}; - wildcard bins cv_sll_sc_b = {INSTR_CV_SLL_SC_B}; - wildcard bins cv_sll_sci_b = {INSTR_CV_SLL_SCI_B}; - wildcard bins cv_or_h = {INSTR_CV_OR_H}; - wildcard bins cv_or_sc_h = {INSTR_CV_OR_SC_H}; - wildcard bins cv_or_sci_h = {INSTR_CV_OR_SCI_H}; - wildcard bins cv_or_b = {INSTR_CV_OR_B}; - wildcard bins cv_or_sc_b = {INSTR_CV_OR_SC_B}; - wildcard bins cv_or_sci_b = {INSTR_CV_OR_SCI_B}; - wildcard bins cv_xor_h = {INSTR_CV_XOR_H}; - wildcard bins cv_xor_sc_h = {INSTR_CV_XOR_SC_H}; - wildcard bins cv_xor_sci_h = {INSTR_CV_XOR_SCI_H}; - wildcard bins cv_xor_b = {INSTR_CV_XOR_B}; - wildcard bins cv_xor_sc_b = {INSTR_CV_XOR_SC_B}; - wildcard bins cv_xor_sci_b = {INSTR_CV_XOR_SCI_B}; - wildcard bins cv_and_h = {INSTR_CV_AND_H}; - wildcard bins cv_and_sc_h = {INSTR_CV_AND_SC_H}; - wildcard bins cv_and_sci_h = {INSTR_CV_AND_SCI_H}; - wildcard bins cv_and_b = {INSTR_CV_AND_B}; - wildcard bins cv_and_sc_b = {INSTR_CV_AND_SC_B}; - wildcard bins cv_and_sci_b = {INSTR_CV_AND_SCI_B}; - wildcard bins cv_abs_h = {INSTR_CV_ABS_H}; - wildcard bins cv_abs_b = {INSTR_CV_ABS_B}; - wildcard bins cv_dotup_h = {INSTR_CV_DOTUP_H}; - wildcard bins cv_dotup_sc_h = {INSTR_CV_DOTUP_SC_H}; - wildcard bins cv_dotup_sci_h = {INSTR_CV_DOTUP_SCI_H}; - wildcard bins cv_dotup_b = {INSTR_CV_DOTUP_B}; - wildcard bins cv_dotup_sc_b = {INSTR_CV_DOTUP_SC_B}; - wildcard bins cv_dotup_sci_b = {INSTR_CV_DOTUP_SCI_B}; - wildcard bins cv_dotusp_h = {INSTR_CV_DOTUSP_H}; - wildcard bins cv_dotusp_sc_h = {INSTR_CV_DOTUSP_SC_H}; - wildcard bins cv_dotusp_sci_h = {INSTR_CV_DOTUSP_SCI_H}; - wildcard bins cv_dotusp_b = {INSTR_CV_DOTUSP_B}; - wildcard bins cv_dotusp_sc_b = {INSTR_CV_DOTUSP_SC_B}; - wildcard bins cv_dotusp_sci_b = {INSTR_CV_DOTUSP_SCI_B}; - wildcard bins cv_dotsp_h = {INSTR_CV_DOTSP_H}; - wildcard bins cv_dotsp_sc_h = {INSTR_CV_DOTSP_SC_H}; - wildcard bins cv_dotsp_sci_h = {INSTR_CV_DOTSP_SCI_H}; - wildcard bins cv_dotsp_b = {INSTR_CV_DOTSP_B}; - wildcard bins cv_dotsp_sc_b = {INSTR_CV_DOTSP_SC_B}; - wildcard bins cv_dotsp_sci_b = {INSTR_CV_DOTSP_SCI_B}; - wildcard bins cv_sdotup_h = {INSTR_CV_SDOTUP_H}; - wildcard bins cv_sdotup_sc_h = {INSTR_CV_SDOTUP_SC_H}; - wildcard bins cv_sdotup_sci_h = {INSTR_CV_SDOTUP_SCI_H}; - wildcard bins cv_sdotup_b = {INSTR_CV_SDOTUP_B}; - wildcard bins cv_sdotup_sc_b = {INSTR_CV_SDOTUP_SC_B}; - wildcard bins cv_sdotup_sci_b = {INSTR_CV_SDOTUP_SCI_B}; - wildcard bins cv_sdotusp_h = {INSTR_CV_SDOTUSP_H}; - wildcard bins cv_sdotusp_sc_h = {INSTR_CV_SDOTUSP_SC_H}; - wildcard bins cv_sdotusp_sci_h = {INSTR_CV_SDOTUSP_SCI_H}; - wildcard bins cv_sdotusp_b = {INSTR_CV_SDOTUSP_B}; - wildcard bins cv_sdotusp_sc_b = {INSTR_CV_SDOTUSP_SC_B}; - wildcard bins cv_sdotusp_sci_b = {INSTR_CV_SDOTUSP_SCI_B}; - wildcard bins cv_sdotsp_h = {INSTR_CV_SDOTSP_H}; - wildcard bins cv_sdotsp_sc_h = {INSTR_CV_SDOTSP_SC_H}; - wildcard bins cv_sdotsp_sci_h = {INSTR_CV_SDOTSP_SCI_H}; - wildcard bins cv_sdotsp_b = {INSTR_CV_SDOTSP_B}; - wildcard bins cv_sdotsp_sc_b = {INSTR_CV_SDOTSP_SC_B}; - wildcard bins cv_sdotsp_sci_b = {INSTR_CV_SDOTSP_SCI_B}; - wildcard bins cv_extract_h = {INSTR_CV_EXTRACT_H}; - wildcard bins cv_extract_b = {INSTR_CV_EXTRACT_B}; - wildcard bins cv_extractu_h = {INSTR_CV_EXTRACTU_H}; - wildcard bins cv_extractu_b = {INSTR_CV_EXTRACTU_B}; - wildcard bins cv_insert_h = {INSTR_CV_INSERT_H}; - wildcard bins cv_insert_b = {INSTR_CV_INSERT_B}; - wildcard bins cv_shuffle_h = {INSTR_CV_SHUFFLE_H}; - wildcard bins cv_shuffle_sci_h = {INSTR_CV_SHUFFLE_SCI_H}; - wildcard bins cv_shuffle_b = {INSTR_CV_SHUFFLE_B}; - wildcard bins cv_shufflei0_sci_b = {INSTR_CV_SHUFFLEI0_SCI_B}; - wildcard bins cv_shufflei1_sci_b = {INSTR_CV_SHUFFLEI1_SCI_B}; - wildcard bins cv_shufflei2_sci_b = {INSTR_CV_SHUFFLEI2_SCI_B}; - wildcard bins cv_shufflei3_sci_b = {INSTR_CV_SHUFFLEI3_SCI_B}; - wildcard bins cv_shuffle2_h = {INSTR_CV_SHUFFLE2_H}; - wildcard bins cv_shuffle2_b = {INSTR_CV_SHUFFLE2_B}; - wildcard bins cv_pack = {INSTR_CV_PACK}; - wildcard bins cv_pack_h = {INSTR_CV_PACK_H}; - wildcard bins cv_packhi_b = {INSTR_CV_PACKHI_B}; - wildcard bins cv_packlo_b = {INSTR_CV_PACKLO_B}; - wildcard bins cv_cmpeq_h = {INSTR_CV_CMPEQ_H}; - wildcard bins cv_cmpeq_sc_h = {INSTR_CV_CMPEQ_SC_H}; - wildcard bins cv_cmpeq_sci_h = {INSTR_CV_CMPEQ_SCI_H}; - wildcard bins cv_cmpeq_b = {INSTR_CV_CMPEQ_B}; - wildcard bins cv_cmpeq_sc_b = {INSTR_CV_CMPEQ_SC_B}; - wildcard bins cv_cmpeq_sci_b = {INSTR_CV_CMPEQ_SCI_B}; - wildcard bins cv_cmpne_h = {INSTR_CV_CMPNE_H}; - wildcard bins cv_cmpne_sc_h = {INSTR_CV_CMPNE_SC_H}; - wildcard bins cv_cmpne_sci_h = {INSTR_CV_CMPNE_SCI_H}; - wildcard bins cv_cmpne_b = {INSTR_CV_CMPNE_B}; - wildcard bins cv_cmpne_sc_b = {INSTR_CV_CMPNE_SC_B}; - wildcard bins cv_cmpne_sci_b = {INSTR_CV_CMPNE_SCI_B}; - wildcard bins cv_cmpgt_h = {INSTR_CV_CMPGT_H}; - wildcard bins cv_cmpgt_sc_h = {INSTR_CV_CMPGT_SC_H}; - wildcard bins cv_cmpgt_sci_h = {INSTR_CV_CMPGT_SCI_H}; - wildcard bins cv_cmpgt_b = {INSTR_CV_CMPGT_B}; - wildcard bins cv_cmpgt_sc_b = {INSTR_CV_CMPGT_SC_B}; - wildcard bins cv_cmpgt_sci_b = {INSTR_CV_CMPGT_SCI_B}; - wildcard bins cv_cmpge_h = {INSTR_CV_CMPGE_H}; - wildcard bins cv_cmpge_sc_h = {INSTR_CV_CMPGE_SC_H}; - wildcard bins cv_cmpge_sci_h = {INSTR_CV_CMPGE_SCI_H}; - wildcard bins cv_cmpge_b = {INSTR_CV_CMPGE_B}; - wildcard bins cv_cmpge_sc_b = {INSTR_CV_CMPGE_SC_B}; - wildcard bins cv_cmpge_sci_b = {INSTR_CV_CMPGE_SCI_B}; - wildcard bins cv_cmplt_h = {INSTR_CV_CMPLT_H}; - wildcard bins cv_cmplt_sc_h = {INSTR_CV_CMPLT_SC_H}; - wildcard bins cv_cmplt_sci_h = {INSTR_CV_CMPLT_SCI_H}; - wildcard bins cv_cmplt_b = {INSTR_CV_CMPLT_B}; - wildcard bins cv_cmplt_sc_b = {INSTR_CV_CMPLT_SC_B}; - wildcard bins cv_cmplt_sci_b = {INSTR_CV_CMPLT_SCI_B}; - wildcard bins cv_cmple_h = {INSTR_CV_CMPLE_H}; - wildcard bins cv_cmple_sc_h = {INSTR_CV_CMPLE_SC_H}; - wildcard bins cv_cmple_sci_h = {INSTR_CV_CMPLE_SCI_H}; - wildcard bins cv_cmple_b = {INSTR_CV_CMPLE_B}; - wildcard bins cv_cmple_sc_b = {INSTR_CV_CMPLE_SC_B}; - wildcard bins cv_cmple_sci_b = {INSTR_CV_CMPLE_SCI_B}; - wildcard bins cv_cmpgtu_h = {INSTR_CV_CMPGTU_H}; - wildcard bins cv_cmpgtu_sc_h = {INSTR_CV_CMPGTU_SC_H}; - wildcard bins cv_cmpgtu_sci_h = {INSTR_CV_CMPGTU_SCI_H}; - wildcard bins cv_cmpgtu_b = {INSTR_CV_CMPGTU_B}; - wildcard bins cv_cmpgtu_sc_b = {INSTR_CV_CMPGTU_SC_B}; - wildcard bins cv_cmpgtu_sci_b = {INSTR_CV_CMPGTU_SCI_B}; - wildcard bins cv_cmpgeu_h = {INSTR_CV_CMPGEU_H}; - wildcard bins cv_cmpgeu_sc_h = {INSTR_CV_CMPGEU_SC_H}; - wildcard bins cv_cmpgeu_sci_h = {INSTR_CV_CMPGEU_SCI_H}; - wildcard bins cv_cmpgeu_b = {INSTR_CV_CMPGEU_B}; - wildcard bins cv_cmpgeu_sc_b = {INSTR_CV_CMPGEU_SC_B}; - wildcard bins cv_cmpgeu_sci_b = {INSTR_CV_CMPGEU_SCI_B}; - wildcard bins cv_cmpltu_h = {INSTR_CV_CMPLTU_H}; - wildcard bins cv_cmpltu_sc_h = {INSTR_CV_CMPLTU_SC_H}; - wildcard bins cv_cmpltu_sci_h = {INSTR_CV_CMPLTU_SCI_H}; - wildcard bins cv_cmpltu_b = {INSTR_CV_CMPLTU_B}; - wildcard bins cv_cmpltu_sc_b = {INSTR_CV_CMPLTU_SC_B}; - wildcard bins cv_cmpltu_sci_b = {INSTR_CV_CMPLTU_SCI_B}; - wildcard bins cv_cmpleu_h = {INSTR_CV_CMPLEU_H}; - wildcard bins cv_cmpleu_sc_h = {INSTR_CV_CMPLEU_SC_H}; - wildcard bins cv_cmpleu_sci_h = {INSTR_CV_CMPLEU_SCI_H}; - wildcard bins cv_cmpleu_b = {INSTR_CV_CMPLEU_B}; - wildcard bins cv_cmpleu_sc_b = {INSTR_CV_CMPLEU_SC_B}; - wildcard bins cv_cmpleu_sci_b = {INSTR_CV_CMPLEU_SCI_B}; - wildcard bins cv_cplxmul_r = {INSTR_CV_CPLXMUL_R}; - wildcard bins cv_cplxmul_r_div2 = {INSTR_CV_CPLXMUL_R_DIV2}; - wildcard bins cv_cplxmul_r_div4 = {INSTR_CV_CPLXMUL_R_DIV4}; - wildcard bins cv_cplxmul_r_div8 = {INSTR_CV_CPLXMUL_R_DIV8}; - wildcard bins cv_cplxmul_i = {INSTR_CV_CPLXMUL_I}; - wildcard bins cv_cplxmul_i_div2 = {INSTR_CV_CPLXMUL_I_DIV2}; - wildcard bins cv_cplxmul_i_div4 = {INSTR_CV_CPLXMUL_I_DIV4}; - wildcard bins cv_cplxmul_i_div8 = {INSTR_CV_CPLXMUL_I_DIV8}; - wildcard bins cv_cplxconj = {INSTR_CV_CPLXCONJ}; - wildcard bins cv_subrotmj = {INSTR_CV_SUBROTMJ}; - wildcard bins cv_subrotmj_div2 = {INSTR_CV_SUBROTMJ_DIV2}; - wildcard bins cv_subrotmj_div4 = {INSTR_CV_SUBROTMJ_DIV4}; - wildcard bins cv_subrotmj_div8 = {INSTR_CV_SUBROTMJ_DIV8}; - wildcard bins cv_add_div2 = {INSTR_CV_ADD_DIV2}; - wildcard bins cv_add_div4 = {INSTR_CV_ADD_DIV4}; - wildcard bins cv_add_div8 = {INSTR_CV_ADD_DIV8}; - wildcard bins cv_sub_div2 = {INSTR_CV_SUB_DIV2}; - wildcard bins cv_sub_div4 = {INSTR_CV_SUB_DIV4}; - wildcard bins cv_sub_div8 = {INSTR_CV_SUB_DIV8}; + `RV32X_PULP_INSTR_BINS } //cross xpulp instr while in debug mode diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv index c4940e8678..83af8344cd 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv @@ -132,5 +132,334 @@ bins xpulp_custom_2 = {OPCODE_CUSTOM_2}; \ bins xpulp_custom_3 = {OPCODE_CUSTOM_3}; +`define RV32X_PULP_INSTR_BINS \ + wildcard bins cv_lb_pi_ri = {INSTR_CV_LB_PI_RI}; \ + wildcard bins cv_lh_pi_ri = {INSTR_CV_LH_PI_RI}; \ + wildcard bins cv_lw_pi_ri = {INSTR_CV_LW_PI_RI}; \ + wildcard bins cv_elw_pi_ri = {INSTR_CV_ELW_PI_RI}; \ + wildcard bins cv_lbu_pi_ri = {INSTR_CV_LBU_PI_RI}; \ + wildcard bins cv_lhu_pi_ri = {INSTR_CV_LHU_PI_RI}; \ + wildcard bins cv_beqimm = {INSTR_CV_BEQIMM}; \ + wildcard bins cv_bneimm = {INSTR_CV_BNEIMM}; \ + wildcard bins cv_lb_pi_rr = {INSTR_CV_LB_PI_RR}; \ + wildcard bins cv_lh_pi_rr = {INSTR_CV_LH_PI_RR}; \ + wildcard bins cv_lw_pi_rr = {INSTR_CV_LW_PI_RR}; \ + wildcard bins cv_lbu_pi_rr = {INSTR_CV_LBU_PI_RR}; \ + wildcard bins cv_lhu_pi_rr = {INSTR_CV_LHU_PI_RR}; \ + wildcard bins cv_lb_rr = {INSTR_CV_LB_RR}; \ + wildcard bins cv_lh_rr = {INSTR_CV_LH_RR}; \ + wildcard bins cv_lw_rr = {INSTR_CV_LW_RR}; \ + wildcard bins cv_lbu_rr = {INSTR_CV_LBU_RR}; \ + wildcard bins cv_lhu_rr = {INSTR_CV_LHU_RR}; \ + wildcard bins cv_sb_pi_ri = {INSTR_CV_SB_PI_RI}; \ + wildcard bins cv_sh_pi_ri = {INSTR_CV_SH_PI_RI}; \ + wildcard bins cv_sw_pi_ri = {INSTR_CV_SW_PI_RI}; \ + wildcard bins cv_sb_pi_rr = {INSTR_CV_SB_PI_RR}; \ + wildcard bins cv_sh_pi_rr = {INSTR_CV_SH_PI_RR}; \ + wildcard bins cv_sw_pi_rr = {INSTR_CV_SW_PI_RR}; \ + wildcard bins cv_sb_rr = {INSTR_CV_SB_RR}; \ + wildcard bins cv_sh_rr = {INSTR_CV_SH_RR}; \ + wildcard bins cv_sw_rr = {INSTR_CV_SW_RR}; \ + wildcard bins cv_starti0 = {INSTR_CV_STARTI_0}; \ + wildcard bins cv_start0 = {INSTR_CV_START_0}; \ + wildcard bins cv_endi0 = {INSTR_CV_ENDI_0}; \ + wildcard bins cv_end0 = {INSTR_CV_END_0}; \ + wildcard bins cv_counti0 = {INSTR_CV_COUNTI_0}; \ + wildcard bins cv_count0 = {INSTR_CV_COUNT_0}; \ + wildcard bins cv_setupi0 = {INSTR_CV_SETUPI_0}; \ + wildcard bins cv_setup0 = {INSTR_CV_SETUP_0}; \ + wildcard bins cv_starti1 = {INSTR_CV_STARTI_1}; \ + wildcard bins cv_start1 = {INSTR_CV_START_1}; \ + wildcard bins cv_endi1 = {INSTR_CV_ENDI_1}; \ + wildcard bins cv_end1 = {INSTR_CV_END_1}; \ + wildcard bins cv_counti1 = {INSTR_CV_COUNTI_1}; \ + wildcard bins cv_count1 = {INSTR_CV_COUNT_1}; \ + wildcard bins cv_setupi1 = {INSTR_CV_SETUPI_1}; \ + wildcard bins cv_setup1 = {INSTR_CV_SETUP_1}; \ + wildcard bins cv_extractr = {INSTR_CV_EXTRACTR}; \ + wildcard bins cv_extractur = {INSTR_CV_EXTRACTUR}; \ + wildcard bins cv_insertr = {INSTR_CV_INSERTR}; \ + wildcard bins cv_bclrr = {INSTR_CV_BCLRR}; \ + wildcard bins cv_bsetr = {INSTR_CV_BSETR}; \ + wildcard bins cv_ror = {INSTR_CV_ROR}; \ + wildcard bins cv_ff1 = {INSTR_CV_FF1}; \ + wildcard bins cv_fl1 = {INSTR_CV_FL1}; \ + wildcard bins cv_clb = {INSTR_CV_CLB}; \ + wildcard bins cv_cnt = {INSTR_CV_CNT}; \ + wildcard bins cv_abs = {INSTR_CV_ABS}; \ + wildcard bins cv_sle = {INSTR_CV_SLE}; \ + wildcard bins cv_sleu = {INSTR_CV_SLEU}; \ + wildcard bins cv_min = {INSTR_CV_MIN}; \ + wildcard bins cv_minu = {INSTR_CV_MINU}; \ + wildcard bins cv_max = {INSTR_CV_MAX}; \ + wildcard bins cv_maxu = {INSTR_CV_MAXU}; \ + wildcard bins cv_exths = {INSTR_CV_EXTHS}; \ + wildcard bins cv_exthz = {INSTR_CV_EXTHZ}; \ + wildcard bins cv_extbs = {INSTR_CV_EXTBS}; \ + wildcard bins cv_extbz = {INSTR_CV_EXTBZ}; \ + wildcard bins cv_clip = {INSTR_CV_CLIP}; \ + wildcard bins cv_clipu = {INSTR_CV_CLIPU}; \ + wildcard bins cv_clipr = {INSTR_CV_CLIPR}; \ + wildcard bins cv_clipur = {INSTR_CV_CLIPUR}; \ + wildcard bins cv_addnr = {INSTR_CV_ADDNR}; \ + wildcard bins cv_addunr = {INSTR_CV_ADDUNR}; \ + wildcard bins cv_addrnr = {INSTR_CV_ADDRNR}; \ + wildcard bins cv_addurnr = {INSTR_CV_ADDURNR}; \ + wildcard bins cv_subnr = {INSTR_CV_SUBNR}; \ + wildcard bins cv_subunr = {INSTR_CV_SUBUNR}; \ + wildcard bins cv_subrnr = {INSTR_CV_SUBRNR}; \ + wildcard bins cv_suburnr = {INSTR_CV_SUBURNR}; \ + wildcard bins cv_mac = {INSTR_CV_MAC}; \ + wildcard bins cv_msu = {INSTR_CV_MSU}; \ + wildcard bins cv_extract = {INSTR_CV_EXTRACT}; \ + wildcard bins cv_extractu = {INSTR_CV_EXTRACTU}; \ + wildcard bins cv_insert = {INSTR_CV_INSERT}; \ + wildcard bins cv_bclr = {INSTR_CV_BCLR}; \ + wildcard bins cv_bset = {INSTR_CV_BSET}; \ + wildcard bins cv_bitrev = {INSTR_CV_BITREV}; \ + wildcard bins cv_addn = {INSTR_CV_ADDN}; \ + wildcard bins cv_addun = {INSTR_CV_ADDUN}; \ + wildcard bins cv_addrn = {INSTR_CV_ADDRN}; \ + wildcard bins cv_addurn = {INSTR_CV_ADDURN}; \ + wildcard bins cv_subn = {INSTR_CV_SUBN}; \ + wildcard bins cv_subun = {INSTR_CV_SUBUN}; \ + wildcard bins cv_subrn = {INSTR_CV_SUBRN}; \ + wildcard bins cv_suburn = {INSTR_CV_SUBURN}; \ + wildcard bins cv_mulsn = {INSTR_CV_MULSN}; \ + wildcard bins cv_mulhhsn = {INSTR_CV_MULHHSN}; \ + wildcard bins cv_mulsrn = {INSTR_CV_MULSRN}; \ + wildcard bins cv_mulhhsrn = {INSTR_CV_MULHHSRN}; \ + wildcard bins cv_mulun = {INSTR_CV_MULUN}; \ + wildcard bins cv_mulhhun = {INSTR_CV_MULHHUN}; \ + wildcard bins cv_mulurn = {INSTR_CV_MULURN}; \ + wildcard bins cv_mulhhurn = {INSTR_CV_MULHHURN}; \ + wildcard bins cv_macsn = {INSTR_CV_MACSN}; \ + wildcard bins cv_machhsn = {INSTR_CV_MACHHSN}; \ + wildcard bins cv_macsrn = {INSTR_CV_MACSRN}; \ + wildcard bins cv_machhsrn = {INSTR_CV_MACHHSRN}; \ + wildcard bins cv_macun = {INSTR_CV_MACUN}; \ + wildcard bins cv_machhun = {INSTR_CV_MACHHUN}; \ + wildcard bins cv_macurn = {INSTR_CV_MACURN}; \ + wildcard bins cv_machhurn = {INSTR_CV_MACHHURN}; \ + wildcard bins cv_add_h = {INSTR_CV_ADD_H}; \ + wildcard bins cv_add_sc_h = {INSTR_CV_ADD_SC_H}; \ + wildcard bins cv_add_sci_h = {INSTR_CV_ADD_SCI_H}; \ + wildcard bins cv_add_b = {INSTR_CV_ADD_B}; \ + wildcard bins cv_add_sc_b = {INSTR_CV_ADD_SC_B}; \ + wildcard bins cv_add_sci_b = {INSTR_CV_ADD_SCI_B}; \ + wildcard bins cv_sub_h = {INSTR_CV_SUB_H}; \ + wildcard bins cv_sub_sc_h = {INSTR_CV_SUB_SC_H}; \ + wildcard bins cv_sub_sci_h = {INSTR_CV_SUB_SCI_H}; \ + wildcard bins cv_sub_b = {INSTR_CV_SUB_B}; \ + wildcard bins cv_sub_sc_b = {INSTR_CV_SUB_SC_B}; \ + wildcard bins cv_sub_sci_b = {INSTR_CV_SUB_SCI_B}; \ + wildcard bins cv_avg_h = {INSTR_CV_AVG_H}; \ + wildcard bins cv_avg_sc_h = {INSTR_CV_AVG_SC_H}; \ + wildcard bins cv_avg_sci_h = {INSTR_CV_AVG_SCI_H}; \ + wildcard bins cv_avg_b = {INSTR_CV_AVG_B}; \ + wildcard bins cv_avg_sc_b = {INSTR_CV_AVG_SC_B}; \ + wildcard bins cv_avg_sci_b = {INSTR_CV_AVG_SCI_B}; \ + wildcard bins cv_avgu_h = {INSTR_CV_AVGU_H}; \ + wildcard bins cv_avgu_sc_h = {INSTR_CV_AVGU_SC_H}; \ + wildcard bins cv_avgu_sci_h = {INSTR_CV_AVGU_SCI_H}; \ + wildcard bins cv_avgu_b = {INSTR_CV_AVGU_B}; \ + wildcard bins cv_avgu_sc_b = {INSTR_CV_AVGU_SC_B}; \ + wildcard bins cv_avgu_sci_b = {INSTR_CV_AVGU_SCI_B}; \ + wildcard bins cv_min_h = {INSTR_CV_MIN_H}; \ + wildcard bins cv_min_sc_h = {INSTR_CV_MIN_SC_H}; \ + wildcard bins cv_min_sci_h = {INSTR_CV_MIN_SCI_H}; \ + wildcard bins cv_min_b = {INSTR_CV_MIN_B}; \ + wildcard bins cv_min_sc_b = {INSTR_CV_MIN_SC_B}; \ + wildcard bins cv_min_sci_b = {INSTR_CV_MIN_SCI_B}; \ + wildcard bins cv_minu_h = {INSTR_CV_MINU_H}; \ + wildcard bins cv_minu_sc_h = {INSTR_CV_MINU_SC_H}; \ + wildcard bins cv_minu_sci_h = {INSTR_CV_MINU_SCI_H}; \ + wildcard bins cv_minu_b = {INSTR_CV_MINU_B}; \ + wildcard bins cv_minu_sc_b = {INSTR_CV_MINU_SC_B}; \ + wildcard bins cv_minu_sci_b = {INSTR_CV_MINU_SCI_B}; \ + wildcard bins cv_max_h = {INSTR_CV_MAX_H}; \ + wildcard bins cv_max_sc_h = {INSTR_CV_MAX_SC_H}; \ + wildcard bins cv_max_sci_h = {INSTR_CV_MAX_SCI_H}; \ + wildcard bins cv_max_b = {INSTR_CV_MAX_B}; \ + wildcard bins cv_max_sc_b = {INSTR_CV_MAX_SC_B}; \ + wildcard bins cv_max_sci_b = {INSTR_CV_MAX_SCI_B}; \ + wildcard bins cv_maxu_h = {INSTR_CV_MAXU_H}; \ + wildcard bins cv_maxu_sc_h = {INSTR_CV_MAXU_SC_H}; \ + wildcard bins cv_maxu_sci_h = {INSTR_CV_MAXU_SCI_H}; \ + wildcard bins cv_maxu_b = {INSTR_CV_MAXU_B}; \ + wildcard bins cv_maxu_sc_b = {INSTR_CV_MAXU_SC_B}; \ + wildcard bins cv_maxu_sci_b = {INSTR_CV_MAXU_SCI_B}; \ + wildcard bins cv_srl_h = {INSTR_CV_SRL_H}; \ + wildcard bins cv_srl_sc_h = {INSTR_CV_SRL_SC_H}; \ + wildcard bins cv_srl_sci_h = {INSTR_CV_SRL_SCI_H}; \ + wildcard bins cv_srl_b = {INSTR_CV_SRL_B}; \ + wildcard bins cv_srl_sc_b = {INSTR_CV_SRL_SC_B}; \ + wildcard bins cv_srl_sci_b = {INSTR_CV_SRL_SCI_B}; \ + wildcard bins cv_sra_h = {INSTR_CV_SRA_H}; \ + wildcard bins cv_sra_sc_h = {INSTR_CV_SRA_SC_H}; \ + wildcard bins cv_sra_sci_h = {INSTR_CV_SRA_SCI_H}; \ + wildcard bins cv_sra_b = {INSTR_CV_SRA_B}; \ + wildcard bins cv_sra_sc_b = {INSTR_CV_SRA_SC_B}; \ + wildcard bins cv_sra_sci_b = {INSTR_CV_SRA_SCI_B}; \ + wildcard bins cv_sll_h = {INSTR_CV_SLL_H}; \ + wildcard bins cv_sll_sc_h = {INSTR_CV_SLL_SC_H}; \ + wildcard bins cv_sll_sci_h = {INSTR_CV_SLL_SCI_H}; \ + wildcard bins cv_sll_b = {INSTR_CV_SLL_B}; \ + wildcard bins cv_sll_sc_b = {INSTR_CV_SLL_SC_B}; \ + wildcard bins cv_sll_sci_b = {INSTR_CV_SLL_SCI_B}; \ + wildcard bins cv_or_h = {INSTR_CV_OR_H}; \ + wildcard bins cv_or_sc_h = {INSTR_CV_OR_SC_H}; \ + wildcard bins cv_or_sci_h = {INSTR_CV_OR_SCI_H}; \ + wildcard bins cv_or_b = {INSTR_CV_OR_B}; \ + wildcard bins cv_or_sc_b = {INSTR_CV_OR_SC_B}; \ + wildcard bins cv_or_sci_b = {INSTR_CV_OR_SCI_B}; \ + wildcard bins cv_xor_h = {INSTR_CV_XOR_H}; \ + wildcard bins cv_xor_sc_h = {INSTR_CV_XOR_SC_H}; \ + wildcard bins cv_xor_sci_h = {INSTR_CV_XOR_SCI_H}; \ + wildcard bins cv_xor_b = {INSTR_CV_XOR_B}; \ + wildcard bins cv_xor_sc_b = {INSTR_CV_XOR_SC_B}; \ + wildcard bins cv_xor_sci_b = {INSTR_CV_XOR_SCI_B}; \ + wildcard bins cv_and_h = {INSTR_CV_AND_H}; \ + wildcard bins cv_and_sc_h = {INSTR_CV_AND_SC_H}; \ + wildcard bins cv_and_sci_h = {INSTR_CV_AND_SCI_H}; \ + wildcard bins cv_and_b = {INSTR_CV_AND_B}; \ + wildcard bins cv_and_sc_b = {INSTR_CV_AND_SC_B}; \ + wildcard bins cv_and_sci_b = {INSTR_CV_AND_SCI_B}; \ + wildcard bins cv_abs_h = {INSTR_CV_ABS_H}; \ + wildcard bins cv_abs_b = {INSTR_CV_ABS_B}; \ + wildcard bins cv_dotup_h = {INSTR_CV_DOTUP_H}; \ + wildcard bins cv_dotup_sc_h = {INSTR_CV_DOTUP_SC_H}; \ + wildcard bins cv_dotup_sci_h = {INSTR_CV_DOTUP_SCI_H}; \ + wildcard bins cv_dotup_b = {INSTR_CV_DOTUP_B}; \ + wildcard bins cv_dotup_sc_b = {INSTR_CV_DOTUP_SC_B}; \ + wildcard bins cv_dotup_sci_b = {INSTR_CV_DOTUP_SCI_B}; \ + wildcard bins cv_dotusp_h = {INSTR_CV_DOTUSP_H}; \ + wildcard bins cv_dotusp_sc_h = {INSTR_CV_DOTUSP_SC_H}; \ + wildcard bins cv_dotusp_sci_h = {INSTR_CV_DOTUSP_SCI_H}; \ + wildcard bins cv_dotusp_b = {INSTR_CV_DOTUSP_B}; \ + wildcard bins cv_dotusp_sc_b = {INSTR_CV_DOTUSP_SC_B}; \ + wildcard bins cv_dotusp_sci_b = {INSTR_CV_DOTUSP_SCI_B}; \ + wildcard bins cv_dotsp_h = {INSTR_CV_DOTSP_H}; \ + wildcard bins cv_dotsp_sc_h = {INSTR_CV_DOTSP_SC_H}; \ + wildcard bins cv_dotsp_sci_h = {INSTR_CV_DOTSP_SCI_H}; \ + wildcard bins cv_dotsp_b = {INSTR_CV_DOTSP_B}; \ + wildcard bins cv_dotsp_sc_b = {INSTR_CV_DOTSP_SC_B}; \ + wildcard bins cv_dotsp_sci_b = {INSTR_CV_DOTSP_SCI_B}; \ + wildcard bins cv_sdotup_h = {INSTR_CV_SDOTUP_H}; \ + wildcard bins cv_sdotup_sc_h = {INSTR_CV_SDOTUP_SC_H}; \ + wildcard bins cv_sdotup_sci_h = {INSTR_CV_SDOTUP_SCI_H}; \ + wildcard bins cv_sdotup_b = {INSTR_CV_SDOTUP_B}; \ + wildcard bins cv_sdotup_sc_b = {INSTR_CV_SDOTUP_SC_B}; \ + wildcard bins cv_sdotup_sci_b = {INSTR_CV_SDOTUP_SCI_B}; \ + wildcard bins cv_sdotusp_h = {INSTR_CV_SDOTUSP_H}; \ + wildcard bins cv_sdotusp_sc_h = {INSTR_CV_SDOTUSP_SC_H}; \ + wildcard bins cv_sdotusp_sci_h = {INSTR_CV_SDOTUSP_SCI_H}; \ + wildcard bins cv_sdotusp_b = {INSTR_CV_SDOTUSP_B}; \ + wildcard bins cv_sdotusp_sc_b = {INSTR_CV_SDOTUSP_SC_B}; \ + wildcard bins cv_sdotusp_sci_b = {INSTR_CV_SDOTUSP_SCI_B}; \ + wildcard bins cv_sdotsp_h = {INSTR_CV_SDOTSP_H}; \ + wildcard bins cv_sdotsp_sc_h = {INSTR_CV_SDOTSP_SC_H}; \ + wildcard bins cv_sdotsp_sci_h = {INSTR_CV_SDOTSP_SCI_H}; \ + wildcard bins cv_sdotsp_b = {INSTR_CV_SDOTSP_B}; \ + wildcard bins cv_sdotsp_sc_b = {INSTR_CV_SDOTSP_SC_B}; \ + wildcard bins cv_sdotsp_sci_b = {INSTR_CV_SDOTSP_SCI_B}; \ + wildcard bins cv_extract_h = {INSTR_CV_EXTRACT_H}; \ + wildcard bins cv_extract_b = {INSTR_CV_EXTRACT_B}; \ + wildcard bins cv_extractu_h = {INSTR_CV_EXTRACTU_H}; \ + wildcard bins cv_extractu_b = {INSTR_CV_EXTRACTU_B}; \ + wildcard bins cv_insert_h = {INSTR_CV_INSERT_H}; \ + wildcard bins cv_insert_b = {INSTR_CV_INSERT_B}; \ + wildcard bins cv_shuffle_h = {INSTR_CV_SHUFFLE_H}; \ + wildcard bins cv_shuffle_sci_h = {INSTR_CV_SHUFFLE_SCI_H}; \ + wildcard bins cv_shuffle_b = {INSTR_CV_SHUFFLE_B}; \ + wildcard bins cv_shufflei0_sci_b = {INSTR_CV_SHUFFLEI0_SCI_B}; \ + wildcard bins cv_shufflei1_sci_b = {INSTR_CV_SHUFFLEI1_SCI_B}; \ + wildcard bins cv_shufflei2_sci_b = {INSTR_CV_SHUFFLEI2_SCI_B}; \ + wildcard bins cv_shufflei3_sci_b = {INSTR_CV_SHUFFLEI3_SCI_B}; \ + wildcard bins cv_shuffle2_h = {INSTR_CV_SHUFFLE2_H}; \ + wildcard bins cv_shuffle2_b = {INSTR_CV_SHUFFLE2_B}; \ + wildcard bins cv_pack = {INSTR_CV_PACK}; \ + wildcard bins cv_pack_h = {INSTR_CV_PACK_H}; \ + wildcard bins cv_packhi_b = {INSTR_CV_PACKHI_B}; \ + wildcard bins cv_packlo_b = {INSTR_CV_PACKLO_B}; \ + wildcard bins cv_cmpeq_h = {INSTR_CV_CMPEQ_H}; \ + wildcard bins cv_cmpeq_sc_h = {INSTR_CV_CMPEQ_SC_H}; \ + wildcard bins cv_cmpeq_sci_h = {INSTR_CV_CMPEQ_SCI_H}; \ + wildcard bins cv_cmpeq_b = {INSTR_CV_CMPEQ_B}; \ + wildcard bins cv_cmpeq_sc_b = {INSTR_CV_CMPEQ_SC_B}; \ + wildcard bins cv_cmpeq_sci_b = {INSTR_CV_CMPEQ_SCI_B}; \ + wildcard bins cv_cmpne_h = {INSTR_CV_CMPNE_H}; \ + wildcard bins cv_cmpne_sc_h = {INSTR_CV_CMPNE_SC_H}; \ + wildcard bins cv_cmpne_sci_h = {INSTR_CV_CMPNE_SCI_H}; \ + wildcard bins cv_cmpne_b = {INSTR_CV_CMPNE_B}; \ + wildcard bins cv_cmpne_sc_b = {INSTR_CV_CMPNE_SC_B}; \ + wildcard bins cv_cmpne_sci_b = {INSTR_CV_CMPNE_SCI_B}; \ + wildcard bins cv_cmpgt_h = {INSTR_CV_CMPGT_H}; \ + wildcard bins cv_cmpgt_sc_h = {INSTR_CV_CMPGT_SC_H}; \ + wildcard bins cv_cmpgt_sci_h = {INSTR_CV_CMPGT_SCI_H}; \ + wildcard bins cv_cmpgt_b = {INSTR_CV_CMPGT_B}; \ + wildcard bins cv_cmpgt_sc_b = {INSTR_CV_CMPGT_SC_B}; \ + wildcard bins cv_cmpgt_sci_b = {INSTR_CV_CMPGT_SCI_B}; \ + wildcard bins cv_cmpge_h = {INSTR_CV_CMPGE_H}; \ + wildcard bins cv_cmpge_sc_h = {INSTR_CV_CMPGE_SC_H}; \ + wildcard bins cv_cmpge_sci_h = {INSTR_CV_CMPGE_SCI_H}; \ + wildcard bins cv_cmpge_b = {INSTR_CV_CMPGE_B}; \ + wildcard bins cv_cmpge_sc_b = {INSTR_CV_CMPGE_SC_B}; \ + wildcard bins cv_cmpge_sci_b = {INSTR_CV_CMPGE_SCI_B}; \ + wildcard bins cv_cmplt_h = {INSTR_CV_CMPLT_H}; \ + wildcard bins cv_cmplt_sc_h = {INSTR_CV_CMPLT_SC_H}; \ + wildcard bins cv_cmplt_sci_h = {INSTR_CV_CMPLT_SCI_H}; \ + wildcard bins cv_cmplt_b = {INSTR_CV_CMPLT_B}; \ + wildcard bins cv_cmplt_sc_b = {INSTR_CV_CMPLT_SC_B}; \ + wildcard bins cv_cmplt_sci_b = {INSTR_CV_CMPLT_SCI_B}; \ + wildcard bins cv_cmple_h = {INSTR_CV_CMPLE_H}; \ + wildcard bins cv_cmple_sc_h = {INSTR_CV_CMPLE_SC_H}; \ + wildcard bins cv_cmple_sci_h = {INSTR_CV_CMPLE_SCI_H}; \ + wildcard bins cv_cmple_b = {INSTR_CV_CMPLE_B}; \ + wildcard bins cv_cmple_sc_b = {INSTR_CV_CMPLE_SC_B}; \ + wildcard bins cv_cmple_sci_b = {INSTR_CV_CMPLE_SCI_B}; \ + wildcard bins cv_cmpgtu_h = {INSTR_CV_CMPGTU_H}; \ + wildcard bins cv_cmpgtu_sc_h = {INSTR_CV_CMPGTU_SC_H}; \ + wildcard bins cv_cmpgtu_sci_h = {INSTR_CV_CMPGTU_SCI_H}; \ + wildcard bins cv_cmpgtu_b = {INSTR_CV_CMPGTU_B}; \ + wildcard bins cv_cmpgtu_sc_b = {INSTR_CV_CMPGTU_SC_B}; \ + wildcard bins cv_cmpgtu_sci_b = {INSTR_CV_CMPGTU_SCI_B}; \ + wildcard bins cv_cmpgeu_h = {INSTR_CV_CMPGEU_H}; \ + wildcard bins cv_cmpgeu_sc_h = {INSTR_CV_CMPGEU_SC_H}; \ + wildcard bins cv_cmpgeu_sci_h = {INSTR_CV_CMPGEU_SCI_H}; \ + wildcard bins cv_cmpgeu_b = {INSTR_CV_CMPGEU_B}; \ + wildcard bins cv_cmpgeu_sc_b = {INSTR_CV_CMPGEU_SC_B}; \ + wildcard bins cv_cmpgeu_sci_b = {INSTR_CV_CMPGEU_SCI_B}; \ + wildcard bins cv_cmpltu_h = {INSTR_CV_CMPLTU_H}; \ + wildcard bins cv_cmpltu_sc_h = {INSTR_CV_CMPLTU_SC_H}; \ + wildcard bins cv_cmpltu_sci_h = {INSTR_CV_CMPLTU_SCI_H}; \ + wildcard bins cv_cmpltu_b = {INSTR_CV_CMPLTU_B}; \ + wildcard bins cv_cmpltu_sc_b = {INSTR_CV_CMPLTU_SC_B}; \ + wildcard bins cv_cmpltu_sci_b = {INSTR_CV_CMPLTU_SCI_B}; \ + wildcard bins cv_cmpleu_h = {INSTR_CV_CMPLEU_H}; \ + wildcard bins cv_cmpleu_sc_h = {INSTR_CV_CMPLEU_SC_H}; \ + wildcard bins cv_cmpleu_sci_h = {INSTR_CV_CMPLEU_SCI_H}; \ + wildcard bins cv_cmpleu_b = {INSTR_CV_CMPLEU_B}; \ + wildcard bins cv_cmpleu_sc_b = {INSTR_CV_CMPLEU_SC_B}; \ + wildcard bins cv_cmpleu_sci_b = {INSTR_CV_CMPLEU_SCI_B}; \ + wildcard bins cv_cplxmul_r = {INSTR_CV_CPLXMUL_R}; \ + wildcard bins cv_cplxmul_r_div2 = {INSTR_CV_CPLXMUL_R_DIV2}; \ + wildcard bins cv_cplxmul_r_div4 = {INSTR_CV_CPLXMUL_R_DIV4}; \ + wildcard bins cv_cplxmul_r_div8 = {INSTR_CV_CPLXMUL_R_DIV8}; \ + wildcard bins cv_cplxmul_i = {INSTR_CV_CPLXMUL_I}; \ + wildcard bins cv_cplxmul_i_div2 = {INSTR_CV_CPLXMUL_I_DIV2}; \ + wildcard bins cv_cplxmul_i_div4 = {INSTR_CV_CPLXMUL_I_DIV4}; \ + wildcard bins cv_cplxmul_i_div8 = {INSTR_CV_CPLXMUL_I_DIV8}; \ + wildcard bins cv_cplxconj = {INSTR_CV_CPLXCONJ}; \ + wildcard bins cv_subrotmj = {INSTR_CV_SUBROTMJ}; \ + wildcard bins cv_subrotmj_div2 = {INSTR_CV_SUBROTMJ_DIV2}; \ + wildcard bins cv_subrotmj_div4 = {INSTR_CV_SUBROTMJ_DIV4}; \ + wildcard bins cv_subrotmj_div8 = {INSTR_CV_SUBROTMJ_DIV8}; \ + wildcard bins cv_add_div2 = {INSTR_CV_ADD_DIV2}; \ + wildcard bins cv_add_div4 = {INSTR_CV_ADD_DIV4}; \ + wildcard bins cv_add_div8 = {INSTR_CV_ADD_DIV8}; \ + wildcard bins cv_sub_div2 = {INSTR_CV_SUB_DIV2}; \ + wildcard bins cv_sub_div4 = {INSTR_CV_SUB_DIV4}; \ + wildcard bins cv_sub_div8 = {INSTR_CV_SUB_DIV8}; `endif // __UVME_CV32E40P_MACROS_SV__ From 7d79a6b4016339950fd8c4785f33970df19bf9bf Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 17:14:34 +0800 Subject: [PATCH 39/97] replace rvfi_insn with pipeline id_stage signal and chk debug_req cp only in machine mode Signed-off-by: Vaibhav Jain --- cv32e40p/env/uvme/cov/uvme_debug_covg.sv | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv index 2f36153387..fe9f6e5cda 100644 --- a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv @@ -429,13 +429,14 @@ class uvme_debug_covg extends uvm_component; covergroup cg_debug_with_f_inst; `per_instance_fcov - dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { + dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins dbg_req_active = {1'b1}; bins dbg_req_0_to_1 = (0 => 1); } step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins debug_step_mode_set = {1'b1}; + bins dbg_step_mode_set = {1'b1}; + bins dbg_step_mode_not_set = {1'b0}; } ebreak: coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { @@ -462,7 +463,7 @@ class uvme_debug_covg extends uvm_component; bins ill_inst_hit = {1}; } - f_inst : coverpoint cntxt.debug_cov_vif.mon_cb.rvfi_insn { + f_inst : coverpoint cntxt.debug_cov_vif.mon_cb.id_stage_instr_rdata_i iff (cntxt.debug_cov_vif.mon_cb.id_stage_instr_valid_i == 1) { `RV32F_INSTR_BINS } @@ -511,20 +512,21 @@ class uvme_debug_covg extends uvm_component; covergroup cg_debug_with_xpulp_inst; `per_instance_fcov - dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { + dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins dbg_req_active = {1'b1}; bins dbg_req_0_to_1 = (0 => 1); } step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins debug_step_mode_set = {1'b1}; + bins dbg_step_mode_set = {1'b1}; + bins dbg_step_mode_not_set = {1'b0}; } dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins in_debug_mode = {1}; } - xpulp_instruction : coverpoint cntxt.debug_cov_vif.mon_cb.rvfi_insn { + xpulp_instruction : coverpoint cntxt.debug_cov_vif.mon_cb.id_stage_instr_rdata_i iff (cntxt.debug_cov_vif.mon_cb.id_stage_instr_valid_i == 1) { `RV32X_PULP_INSTR_BINS } From 41441521a499ef2fe44344a8e363fb8db1a1dc96 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 17:20:55 +0800 Subject: [PATCH 40/97] update cp and cross naming, add trigger crosses and conditions Signed-off-by: Vaibhav Jain --- cv32e40p/env/uvme/cov/uvme_debug_covg.sv | 148 ++++++++++++++++------- 1 file changed, 103 insertions(+), 45 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv index fe9f6e5cda..74750003a2 100644 --- a/cv32e40p/env/uvme/cov/uvme_debug_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_debug_covg.sv @@ -426,118 +426,176 @@ class uvme_debug_covg extends uvm_component; dbg_req_vs_step : cross dbg_req, step; endgroup - covergroup cg_debug_with_f_inst; + covergroup cg_debug_with_rv32f_inst; `per_instance_fcov - dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { + cp_dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins dbg_req_active = {1'b1}; bins dbg_req_0_to_1 = (0 => 1); } - step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { + cp_step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins dbg_step_mode_set = {1'b1}; bins dbg_step_mode_not_set = {1'b0}; } - ebreak: coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { + cp_ebreak: coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { bins ebreak_ex = {1}; } - cebreak : coverpoint cntxt.debug_cov_vif.mon_cb.is_cebreak { + cp_cebreak : coverpoint cntxt.debug_cov_vif.mon_cb.is_cebreak { bins cebreak_ex= {1'b1}; } - ebreakm_set: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[15] { + cp_ebreakm_set: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[15] { bins ebreakm_is_set = {1}; } - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins in_debug_mode = {1}; + cp_trigger_match : coverpoint cntxt.debug_cov_vif.mon_cb.trigger_match_i { + bins not_match = {0}; + bins match = {1}; } - irq : coverpoint |cntxt.debug_cov_vif.mon_cb.irq_i { - bins irq_trans_0_to_1 = (1'b0 => 1'b1); + cp_trigger_en : coverpoint cntxt.debug_cov_vif.mon_cb.tdata1[2] { + bins trig_en = {1}; } - ill : coverpoint cntxt.debug_cov_vif.mon_cb.illegal_insn_i { + cp_dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { + bins in_debug_mode = {1}; + } + + cp_irq : coverpoint (cntxt.debug_cov_vif.mon_cb.irq_i & cntxt.debug_cov_vif.mon_cb.mie_q) { + wildcard bins irq_31_trans_0_to_1 = ( {1'b0,31'b?} => {1'b1,31'b?} ); + wildcard bins irq_30_trans_0_to_1 = ( {1'b0,1'b0,30'b?} => {1'b0,1'b1,30'b?} ); + wildcard bins irq_29_trans_0_to_1 = ( {2'b0,1'b0,29'b?} => {2'b0,1'b1,29'b?} ); + wildcard bins irq_28_trans_0_to_1 = ( {3'b0,1'b0,28'b?} => {3'b0,1'b1,28'b?} ); + wildcard bins irq_27_trans_0_to_1 = ( {4'b0,1'b0,27'b?} => {4'b0,1'b1,27'b?} ); + wildcard bins irq_26_trans_0_to_1 = ( {5'b0,1'b0,26'b?} => {5'b0,1'b1,26'b?} ); + wildcard bins irq_25_trans_0_to_1 = ( {6'b0,1'b0,25'b?} => {6'b0,1'b1,25'b?} ); + wildcard bins irq_24_trans_0_to_1 = ( {7'b0,1'b0,24'b?} => {7'b0,1'b1,24'b?} ); + wildcard bins irq_23_trans_0_to_1 = ( {8'b0,1'b0,23'b?} => {8'b0,1'b1,23'b?} ); + wildcard bins irq_22_trans_0_to_1 = ( {9'b0,1'b0,22'b?} => {9'b0,1'b1,22'b?} ); + wildcard bins irq_21_trans_0_to_1 = ( {10'b0,1'b0,21'b?} => {10'b0,1'b1,21'b?} ); + wildcard bins irq_20_trans_0_to_1 = ( {11'b0,1'b0,20'b?} => {11'b0,1'b1,20'b?} ); + wildcard bins irq_19_trans_0_to_1 = ( {12'b0,1'b0,19'b?} => {12'b0,1'b1,19'b?} ); + wildcard bins irq_18_trans_0_to_1 = ( {13'b0,1'b0,18'b?} => {13'b0,1'b1,18'b?} ); + wildcard bins irq_17_trans_0_to_1 = ( {14'b0,1'b0,17'b?} => {14'b0,1'b1,17'b?} ); + wildcard bins irq_16_trans_0_to_1 = ( {15'b0,1'b0,16'b?} => {15'b0,1'b1,16'b?} ); + wildcard bins irq_11_trans_0_to_1 = ( {20'b0,1'b0,11'b?} => {20'b0,1'b1,11'b?} ); + wildcard bins irq_3_trans_0_to_1 = ( {24'b0,1'b0,3'b?,1'b0,3'b?} => {24'b0,1'b?,3'b?,1'b1,3'b?} ); + wildcard bins irq_7_trans_0_to_1 = ( {24'b0,1'b0,3'b?,1'b0,3'b?} => {24'b0,1'b1,3'b?,1'b0,3'b?} ); + } + + cp_ill : coverpoint cntxt.debug_cov_vif.mon_cb.illegal_insn_i { bins ill_inst_hit = {1}; } - f_inst : coverpoint cntxt.debug_cov_vif.mon_cb.id_stage_instr_rdata_i iff (cntxt.debug_cov_vif.mon_cb.id_stage_instr_valid_i == 1) { + cp_rv32f_inst : coverpoint cntxt.debug_cov_vif.mon_cb.id_stage_instr_rdata_i iff (cntxt.debug_cov_vif.mon_cb.id_stage_instr_valid_i == 1) { `RV32F_INSTR_BINS } - apu_req_valid : coverpoint cntxt.debug_cov_vif.mon_cb.apu_req { + cp_apu_req_valid : coverpoint cntxt.debug_cov_vif.mon_cb.apu_req { bins apu_req_valid = {1'b1}; } - apu_grant_valid : coverpoint cntxt.debug_cov_vif.mon_cb.apu_gnt { + cp_apu_grant_valid : coverpoint cntxt.debug_cov_vif.mon_cb.apu_gnt { bins apu_gnt_valid[] = {1'b1}; } - apu_busy : coverpoint cntxt.debug_cov_vif.mon_cb.apu_busy { + cp_apu_busy : coverpoint cntxt.debug_cov_vif.mon_cb.apu_busy { bins apu_busy[] = {1'b0, 1'b1}; bins apu_busy_0_to_1 = (0 => 1); bins apu_busy_1_to_0 = (1 => 0); } - dbg_x_finst : cross dbg_req, f_inst; + // cross rv32f instr execution at debug req only - no trigger + cr_dbg_x_rv32f : cross cp_dbg_req, cp_rv32f_inst, cp_trigger_match { + ignore_bins no_trigger_match = binsof(cp_trigger_match) intersect {1}; + } + + // cross debug single stepping for each rv32f instr - no trigger + cr_step_x_rv32f : cross cp_step, cp_rv32f_inst, cp_trigger_match { + ignore_bins single_step_disable = binsof(cp_step) intersect {0}; + ignore_bins no_trigger_match = binsof(cp_trigger_match) intersect {1}; + } + + // cross debug entry with trigger addr match at rv32f inst + cr_trigger_with_rv32f : cross cp_trigger_match, cp_trigger_en, cp_rv32f_inst; - step_x_finst : cross step, f_inst; + cr_rv32f_in_dbg_mode : cross cp_dm, cp_rv32f_inst; - f_inst_in_dbg_mode : cross dm, f_inst; + // debug mode entry with debug_halt_req during multi cycle fp inst + cr_dbg_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req; + cr_dbg_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req; - //debug mode entry with debug_halt_req during multi cycle fp inst - dbg_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, dbg_req; - dbg_while_multi_cyc_f_B : cross apu_busy, dbg_req; + // debug_halt_req with irq during multi cycle fp inst + cr_dbg_irq_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_irq; + cr_dbg_irq_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req, cp_irq; - //debug_halt_req with irq during multi cycle fp inst - dbg_irq_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, dbg_req, irq; - dbg_irq_while_multi_cyc_f_B : cross apu_busy, dbg_req, irq; + // debug_halt_req with illegal instr during multi cycle fp inst + cr_dbg_ill_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_ill; + cr_dbg_ill_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req, cp_ill; - //debug_halt_req with illegal instr during multi cycle fp inst - dbg_ill_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, dbg_req, ill; - dbg_ill_while_multi_cyc_f_B : cross apu_busy, dbg_req, ill; + // debug mode entry with ebreak during multi cycle fp inst + cr_ebreak_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_ebreak, cp_ebreakm_set; + cr_ebreak_while_multi_cyc_f_B : cross cp_apu_busy, cp_ebreak, cp_ebreakm_set; - //debug mode entry with ebreak during multi cycle fp inst - ebreak_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, ebreak, ebreakm_set; - ebreak_while_multi_cyc_f_B : cross apu_busy, ebreak, ebreakm_set; + // debug mode entry with cebreak during multi cycle fp inst + cr_cebreak_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_cebreak, cp_ebreakm_set; + cr_cebreak_while_multi_cyc_f_B : cross cp_apu_busy, cp_cebreak, cp_ebreakm_set; - //debug mode entry with cebreak during multi cycle fp inst - cebreak_while_multi_cyc_f_A : cross apu_req_valid, apu_grant_valid, cebreak, ebreakm_set; - cebreak_while_multi_cyc_f_B : cross apu_busy, cebreak, ebreakm_set; + // debug mode entry with trigger during multi cycle fp inst + cr_dbg_trig_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_trigger_match, cp_trigger_en; + cr_dbg_trig_while_multi_cyc_f_B : cross cp_apu_busy, cp_trigger_match, cp_trigger_en; endgroup covergroup cg_debug_with_xpulp_inst; `per_instance_fcov - dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { + cp_dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins dbg_req_active = {1'b1}; bins dbg_req_0_to_1 = (0 => 1); } - step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { + cp_step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins dbg_step_mode_set = {1'b1}; bins dbg_step_mode_not_set = {1'b0}; } - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { + cp_trigger_match : coverpoint cntxt.debug_cov_vif.mon_cb.trigger_match_i { + bins not_match = {0}; + bins match = {1}; + } + + cp_trigger_en : coverpoint cntxt.debug_cov_vif.mon_cb.tdata1[2] { + bins trig_en = {1}; + } + + cp_dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { bins in_debug_mode = {1}; } - xpulp_instruction : coverpoint cntxt.debug_cov_vif.mon_cb.id_stage_instr_rdata_i iff (cntxt.debug_cov_vif.mon_cb.id_stage_instr_valid_i == 1) { + cp_xpulp_instr : coverpoint cntxt.debug_cov_vif.mon_cb.id_stage_instr_rdata_i iff (cntxt.debug_cov_vif.mon_cb.id_stage_instr_valid_i == 1) { `RV32X_PULP_INSTR_BINS } - //cross xpulp instr while in debug mode - xpulp_instructions_in_dbg_mode : cross dm, xpulp_instruction; + // cross xpulp instr while in debug mode + cr_xpulp_instructions_in_dbg_mode : cross cp_dm, cp_xpulp_instr; - //cross xpulp instr excution at debug req - dbg_req_at_xpulp_instr : cross dbg_req, xpulp_instruction; + // cross xpulp instr execution at debug req only - no trigger + cr_dbg_req_at_xpulp_instr : cross cp_dbg_req, cp_xpulp_instr, cp_trigger_match { + ignore_bins no_trigger_match = binsof(cp_trigger_match) intersect {1}; + } + + // cross debug single stepping for each xpulp instr - no trigger + cr_dbg_single_step_xpulp_instr : cross cp_step, cp_xpulp_instr, cp_trigger_match { + ignore_bins single_step_disable = binsof(cp_step) intersect {0}; + ignore_bins no_trigger_match = binsof(cp_trigger_match) intersect {1}; + } - //cross debug single stepping for each xpulp instr - dbg_single_step_xpulp_instr : cross step, xpulp_instruction; + // cross debug entry with trigger addr match at xpulp inst + cr_trigger_with_xpulp_instr : cross cp_trigger_match, cp_trigger_en, cp_xpulp_instr; endgroup @@ -568,7 +626,7 @@ function uvme_debug_covg::new(string name = "debug_covg", uvm_component parent = cg_debug_at_reset = new(); cg_fence_in_debug = new(); cg_debug_causes = new(); - cg_debug_with_f_inst = new(); + cg_debug_with_rv32f_inst = new(); cg_debug_with_xpulp_inst = new(); endfunction : new @@ -625,7 +683,7 @@ task uvme_debug_covg::sample_clk_i(); cg_debug_at_reset.sample(); cg_fence_in_debug.sample(); cg_debug_causes.sample(); - cg_debug_with_f_inst.sample(); + cg_debug_with_rv32f_inst.sample(); cg_debug_with_xpulp_inst.sample(); end endtask : sample_clk_i From ea7751ed8568fa903c51e76f3f1d876ec389a70d Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 17:21:48 +0800 Subject: [PATCH 41/97] re-enable imperas isacov for pulp instr Signed-off-by: Vaibhav Jain --- ...cv32e40p_imperas_riscv_coverage_config.svh | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh index dbdf843906..d6e657ee77 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh @@ -7,10 +7,10 @@ `define COVER_BASE_RV32I `define COVER_LEVEL_COMPL_BAS //`define COVER_LEVEL_COMPL_EXT - `define COVER_LEVEL_DV_UP_BAS - `define COVER_LEVEL_DV_UP_EXT - `define COVER_LEVEL_DV_PR_BAS - `define COVER_LEVEL_DV_PR_EXT + //`define COVER_LEVEL_DV_UP_BAS + //`define COVER_LEVEL_DV_UP_EXT + //`define COVER_LEVEL_DV_PR_BAS + //`define COVER_LEVEL_DV_PR_EXT `define COVER_RV32I `define COVER_RV32M `define COVER_RV32C @@ -31,15 +31,15 @@ `define COVER_RV32ZCF_ILLEGAL `endif - //`ifdef PULP - // `define COVER_XPULPV2 - // `ifdef CLUSTER - // `define COVER_XPULPV2C - // `else - // `define COVER_XPULPV2C_ILLEGAL - // `endif - //`else - // `define COVER_XPULPV2_ILLEGAL - // `define COVER_XPULPV2C_ILLEGAL - //`endif + `ifdef PULP + `define COVER_XPULPV2 + `ifdef CLUSTER + `define COVER_XPULPV2C + `else + `define COVER_XPULPV2C_ILLEGAL + `endif + `else + `define COVER_XPULPV2_ILLEGAL + `define COVER_XPULPV2C_ILLEGAL + `endif `endif From 4b5afb29725ad178e3ef882298b3c63acd14554a Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 17:24:11 +0800 Subject: [PATCH 42/97] add debug signals for cov_if Signed-off-by: Vaibhav Jain --- cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 95f6f301ce..6b8cf94418 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -514,6 +514,10 @@ interface uvmt_cv32e40p_cov_if input ex_regfile_alu_we_i, input ex_apu_valid, input ex_apu_rvalid_q, + input debug_req_i, + input debug_mode_q, + input [31:0] dcsr_q, + input trigger_match_i, output logic[5:0] o_curr_fpu_apu_op_if, output logic[5:0] o_last_fpu_apu_op_if, @@ -571,6 +575,10 @@ interface uvmt_cv32e40p_cov_if input apu_perf_wb_o; input id_stage_apu_op_ex_o; input id_stage_apu_en_ex_o; + input debug_req_i; + input debug_mode_q; + input trigger_match_i; + input dcsr_q; output is_mulh_ex; output is_misaligned_data_req_ex; output is_post_inc_ld_st_inst_ex; From ad0648e4167f297673a6bc1c8cf473368d9342d6 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 17:25:18 +0800 Subject: [PATCH 43/97] fix cb inouts Signed-off-by: Vaibhav Jain --- cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 6b8cf94418..e9261b4c70 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -579,10 +579,10 @@ interface uvmt_cv32e40p_cov_if input debug_mode_q; input trigger_match_i; input dcsr_q; - output is_mulh_ex; - output is_misaligned_data_req_ex; - output is_post_inc_ld_st_inst_ex; - output ex_apu_valid_memorised; + inout is_mulh_ex; + inout is_misaligned_data_req_ex; + inout is_post_inc_ld_st_inst_ex; + inout ex_apu_valid_memorised; endclocking : mon_cb //calculate each APU operation's current clock cycle number during execution for functional coverage use From 36d1b29c849fd8dfabcc0af880e33f7a3cbd56ce Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 15 Dec 2023 17:40:43 +0800 Subject: [PATCH 44/97] add new test corev_rand_pulp_instr_debug and rand debug test_cfg Signed-off-by: Vaibhav Jain --- .../cv32e40pv2_interrupt_debug_short.yaml | 14 +++---- .../corev_rand_pulp_instr_debug/corev-dv.yaml | 39 +++++++++++++++++++ .../corev_rand_pulp_instr_debug/test.yaml | 10 +++++ .../tests/test_cfg/gen_rand_debug_req.yaml | 5 +++ 4 files changed, 61 insertions(+), 7 deletions(-) create mode 100644 cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/corev-dv.yaml create mode 100644 cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/test.yaml create mode 100644 cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 7cb1b5abac..7c05e6d192 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -22,27 +22,27 @@ builds: # List of tests tests: corev_rand_pulp_instr_ebreak_debug_test: - testname: corev_rand_pulp_instr_test + testname: corev_rand_pulp_instr_debug description: pulp rand test with ebreak debug build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_ebreak corev_rand_pulp_instr_single_step_debug_test: - testname: corev_rand_pulp_instr_test + testname: corev_rand_pulp_instr_debug description: pulp rand test with single-step debug build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_single_step_en corev_rand_pulp_instr_debug_trigger_test: - testname: corev_rand_pulp_instr_test + testname: corev_rand_pulp_instr_debug description: pulp rand test with debug trigger build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_trigger_basic corev_rand_pulp_instr_interrupt_test: @@ -113,7 +113,7 @@ tests: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: debug_trigger_basic + test_cfg: debug_trigger_basic,gen_rand_debug_req debug_test: build: uvmt_cv32e40p diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/corev-dv.yaml new file mode 100644 index 0000000000..e3a496e0b0 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/corev-dv.yaml @@ -0,0 +1,39 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for corev-dv test generator +# corev-dv generator test +name: corev_rand_pulp_instr_debug +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated random pulp instr test +plusargs: > + +instr_cnt=2000 + +num_of_sub_program=0 + +insert_rand_directed_instr_stream=1 + +test_rand_directed_instr_stream_num=9 + +directed_instr_0=cv32e40p_xpulp_rand_stream,2 + +directed_instr_1=cv32e40p_xpulp_short_rand_stream,4 + +directed_instr_2=riscv_load_store_rand_instr_stream,1 + +rand_directed_instr_0=riscv_load_store_rand_instr_stream,2 + +rand_directed_instr_1=riscv_mem_region_stress_test,2 + +rand_directed_instr_2=riscv_load_store_hazard_instr_stream,2 + +rand_directed_instr_3=riscv_multi_page_load_store_instr_stream,2 + +rand_directed_instr_4=riscv_jal_instr,2 + +rand_directed_instr_5=riscv_hazard_instr_stream,2 + +rand_directed_instr_6=cv32e40p_xpulp_simd_stream_test,2 + +rand_directed_instr_7=cv32e40p_xpulp_mac_stream_test,2 + +rand_directed_instr_8=riscv_int_numeric_corner_stream,2 + +no_fence=0 + +hint_instr_ratio=2 + +no_data_page=0 + +randomize_csr=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +no_wfi=1 + +no_dret=1 + +fix_sp=1 + +enable_misaligned_instr=1 + +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/test.yaml new file mode 100644 index 0000000000..82e2020742 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_instr_debug/test.yaml @@ -0,0 +1,10 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for random pulp instr test +name: corev_rand_pulp_instr_debug +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Random debug in xpulp instruction stream +plusargs: > + +gen_reduced_rand_dbg_req diff --git a/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml b/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml new file mode 100644 index 0000000000..eff7693166 --- /dev/null +++ b/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml @@ -0,0 +1,5 @@ +name: gen_rand_debug_req +description: > + Generate Random debug halt request +plusargs: > + +gen_reduced_rand_dbg_req From 19e0b63dbb9c232e6a09f55c0b38859647e58ab9 Mon Sep 17 00:00:00 2001 From: bsm Date: Thu, 21 Dec 2023 17:18:38 +0800 Subject: [PATCH 45/97] Fix hwloop cov model issue during debug entry due to cbreak. Fix hwloop cov issue during vector mode irq entry Signed-off-by: bsm --- cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 95cd8da7e1..7f2dc41a53 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -38,6 +38,7 @@ class uvme_rv32x_hwloop_covg # ( localparam CSR_LPSTART0_ADDR = 32'hCC0; localparam CSR_LPEND0_ADDR = 32'hCC1; localparam CSR_LPCOUNT0_ADDR = 32'hCC2; + localparam INSTR_CBREAK = 32'h9002; localparam INSN_ILLEGAL = 32'hFFFFFFFF; // user-defined for any illegal insn that leads to illegal exception localparam INSN_EBREAKM = 32'hFFFFFFFE; // user-defined @@ -1199,10 +1200,10 @@ class uvme_rv32x_hwloop_covg # ( prev_irq_onehot_priority = cv32e40p_rvvi_vif.irq_onehot_priority; endfunction : update_prev_irq_onehot_priority - function bit pc_is_mtvec_base_addr(); - if (cv32e40p_rvvi_vif.pc_rdata == cv32e40p_rvvi_vif.mtvec_base_addr) return 1; + function bit pc_is_mtvec_addr(); + if (cv32e40p_rvvi_vif.pc_rdata >= cv32e40p_rvvi_vif.mtvec_base_addr && cv32e40p_rvvi_vif.pc_rdata < (cv32e40p_rvvi_vif.mtvec_base_addr + 32*4)) return 1; // direct or vector mode else return 0; - endfunction : pc_is_mtvec_base_addr + endfunction : pc_is_mtvec_addr function bit is_mcause_irq(); return cv32e40p_rvvi_vif.csr_mcause_irq; @@ -1217,7 +1218,7 @@ class uvme_rv32x_hwloop_covg # ( wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.trap); if (cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0 && !pending_irq) begin // set excep flag only if no pending irq case (cv32e40p_rvvi_vif.insn) - INSTR_EBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin + INSTR_EBREAK, INSTR_CBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin @(posedge cv32e40p_rvvi_vif.clk); continue; end else begin is_ebreak = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to EBREAK"), UVM_DEBUG); end @@ -1297,7 +1298,7 @@ class uvme_rv32x_hwloop_covg # ( if (cv32e40p_rvvi_vif.valid) begin : VALID_DETECTED if (enter_hwloop_sub) begin - if (pc_is_mtvec_base_addr() && !is_mcause_irq()) begin : EXCEPTION_ENTRY + if (pc_is_mtvec_addr() && !is_mcause_irq()) begin : EXCEPTION_ENTRY for (int i=0; i Date: Thu, 21 Dec 2023 15:57:15 +0100 Subject: [PATCH 46/97] Temporary workaround for GNU GCC issue #36 (https://github.com/openhwgroup/corev-gcc/issues/36). Signed-off-by: Pascal Gouedo --- .../pulp_hardware_loop_interrupt_test.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/cv32e40p/tests/programs/custom/pulp_hardware_loop_interrupt_test/pulp_hardware_loop_interrupt_test.c b/cv32e40p/tests/programs/custom/pulp_hardware_loop_interrupt_test/pulp_hardware_loop_interrupt_test.c index 7827fb2ccf..7cd4a5e53b 100644 --- a/cv32e40p/tests/programs/custom/pulp_hardware_loop_interrupt_test/pulp_hardware_loop_interrupt_test.c +++ b/cv32e40p/tests/programs/custom/pulp_hardware_loop_interrupt_test/pulp_hardware_loop_interrupt_test.c @@ -216,9 +216,29 @@ __attribute__((interrupt ("machine"))) void u_sw_direct_irq_handler(void) { "j u_sw_irq_handler\n" ); +#ifdef FPU +#define MSTATUS_FS_INITIAL 0x00002000 + +void fp_enable () +{ + unsigned int fs = MSTATUS_FS_INITIAL; + + asm volatile("csrs mstatus, %0;" + "csrwi fcsr, 0;" + "csrs mstatus, %0;" + : : "r"(fs) + ); +} +#endif + int main(int argc, char *argv[]) { int retval; +#ifdef FPU + // Floating Point enable + fp_enable(); +#endif + // Test 1 retval = test1(); if (retval != EXIT_SUCCESS) From c0f098e3a11ff25066aea8ae8b7029477a12cee2 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Fri, 22 Dec 2023 11:48:40 +0100 Subject: [PATCH 47/97] Added more options to run_many Signed-off-by: Pascal Gouedo --- bin/run_many | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/bin/run_many b/bin/run_many index 85d42c4b23..5b3f9e36ed 100755 --- a/bin/run_many +++ b/bin/run_many @@ -7,34 +7,48 @@ # Uses a different seed for each run. # Generates the same "make test" command generated by the "ci_check" script. # -# Usage: run_many [test-program] [simulator] [nruns] -# For example, "run_many hello-world vcs 2" will run the hello-world +# Usage: run_many [cfg] [test-program] [simulator] [nruns] [user_flags] +# For example, "run_many default hello-world vcs 2" will run the hello-world # test-program with VCS twice. # # TODO: command-line argument processing is primitive. if [ $# -gt 0 ] then - TESTPROGRAM=$1 + CFG=$1 else - TESTPROGRAM=hello-world + CFG=default fi if [ $# -gt 1 ] then - SIM=$2 + TESTPROGRAM=$2 else - SIM=vcs + TESTPROGRAM=hello-world fi if [ $# -gt 2 ] then - RUNS=$3 + SIM=$3 +else + SIM=vcs +fi + +if [ $# -gt 3 ] +then + RUNS=$4 else RUNS=2 fi let RUNSM1=$RUNS-1 +if [ $# -gt 4 ] +then + USER_FLAGS=$5 +else + USER_FLAGS= +fi + if [[ -z "${CV_CORE}" ]]; then echo CV_CORE not defined... cannot proceed. @@ -56,8 +70,8 @@ counter=0 until [ $counter -gt $RUNSM1 ] do THISSEED=`date +%N` - echo "make test SEED=$THISSEED TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO" - make test SEED=$THISSEED TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO + echo "make test CFG=$CFG TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO SEED=$THISSEED VSIM_USER_FLAGS=$USER_FLAGS" + make test CFG=$CFG TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO SEED=$THISSEED VSIM_USER_FLAGS=$USER_FLAGS ((counter++)) done From 0893ad70f756730c6ebffa11bcb4729992da3098 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Fri, 22 Dec 2023 11:49:33 +0100 Subject: [PATCH 48/97] Changed regression running options for debug_test_boot_set test Signed-off-by: Pascal Gouedo --- cv32e40p/regress/cv32e40p_debug.yaml | 4 ++-- cv32e40p/regress/cv32e40p_full_covg_no_pulp.yaml | 4 ++-- cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml | 2 +- cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cv32e40p/regress/cv32e40p_debug.yaml b/cv32e40p/regress/cv32e40p_debug.yaml index cd41ad2953..644933da4d 100644 --- a/cv32e40p/regress/cv32e40p_debug.yaml +++ b/cv32e40p/regress/cv32e40p_debug.yaml @@ -35,8 +35,8 @@ tests: build: uvmt_cv32e40p description: Debug reset test with random boot set dir: cv32e40p/sim/uvmt - cmd: make test TEST=debug_test_boot_set - num: 50 + cmd: make test TEST=debug_test_boot_set SEED=1 VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + num: 1 corev_rand_debug: build: uvmt_cv32e40p diff --git a/cv32e40p/regress/cv32e40p_full_covg_no_pulp.yaml b/cv32e40p/regress/cv32e40p_full_covg_no_pulp.yaml index 92e2b1d84e..b0349d91db 100644 --- a/cv32e40p/regress/cv32e40p_full_covg_no_pulp.yaml +++ b/cv32e40p/regress/cv32e40p_full_covg_no_pulp.yaml @@ -283,8 +283,8 @@ tests: build: uvmt_cv32e40p description: Debug test target debug_req at BOOT_SET dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set - num: 50 + cmd: make test COREV=YES TEST=debug_test_boot_set SEED=1 VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + num: 1 interrupt_bootstrap: build: uvmt_cv32e40p diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index 4b1eee87a1..447b32cfc6 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -109,7 +109,7 @@ tests: build: uvmt_cv32e40p description: debug_test_boot_set (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" SEED=1 VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 num: 1 debug_test_known_miscompares: diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 7c05e6d192..024ee5294c 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -126,7 +126,7 @@ tests: build: uvmt_cv32e40p description: debug_test_boot_set (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" SEED=1 VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 num: 1 debug_test_known_miscompares: From 9ed9aa285a18bea5512fb823084c256d0926241b Mon Sep 17 00:00:00 2001 From: bsm Date: Tue, 26 Dec 2023 14:43:30 +0800 Subject: [PATCH 49/97] Improve to handle different trap scenarioes Signed-off-by: bsm --- .../env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 29 ++++++++++++------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 7f2dc41a53..1123ffc656 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -1216,7 +1216,13 @@ class uvme_rv32x_hwloop_covg # ( forever begin : SET_EXCEPTION_FLAG wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.trap); - if (cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0 && !pending_irq) begin // set excep flag only if no pending irq + if ( + cv32e40p_rvvi_vif.pc_rdata == prev_pc_rdata_main || // set excep when not garbage data during trap (main) + cv32e40p_rvvi_vif.pc_rdata == prev_pc_rdata_sub // set excep when not garbage data during trap (sub) - todo: revise is needed when sub is fully implement + ) begin + wait (!cv32e40p_rvvi_vif.trap); // bypass if garbage data exist + end + else if (cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0 && !pending_irq) begin // set excep flag only if no pending irq case (cv32e40p_rvvi_vif.insn) INSTR_EBREAK, INSTR_CBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin @(posedge cv32e40p_rvvi_vif.clk); continue; @@ -1312,15 +1318,15 @@ class uvme_rv32x_hwloop_covg # ( end end // EXCEPTION_ENTRY else if (pc_is_mtvec_addr() && is_mcause_irq()) begin : IRQ_ENTRY - if (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]) begin - is_ebreak = 0; is_ecall = 0; is_illegal = 0; enter_hwloop_sub = 0; - pending_irq = 0; - `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry is replaced with IRQ Entry (higher priority)"), UVM_DEBUG); - `IF_CURRENT_IS_MAIN_HWLOOP(0, IS_IRQ) - `IF_CURRENT_IS_MAIN_HWLOOP(1, IS_IRQ) - update_prev_irq_onehot_priority(); - is_irq = 1; wait (!is_irq); continue; - end + if (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]) begin + is_ebreak = 0; is_ecall = 0; is_illegal = 0; enter_hwloop_sub = 0; + pending_irq = 0; + `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry is replaced with IRQ Entry (higher priority)"), UVM_DEBUG); + `IF_CURRENT_IS_MAIN_HWLOOP(0, IS_IRQ) + `IF_CURRENT_IS_MAIN_HWLOOP(1, IS_IRQ) + update_prev_irq_onehot_priority(); + is_irq = 1; wait (!is_irq); continue; + end end // IRQ_ENTRY // [optional] todo: for hwloops that outside main code (e.g irq only, dbg only, or irq->dbg); currently commented out due to pending for implementation @@ -1330,6 +1336,7 @@ class uvme_rv32x_hwloop_covg # ( check_exception_exit(); if (!(is_ebreak || is_ecall || is_illegal)) enter_hwloop_sub = 0; + prev_pc_rdata_sub = cv32e40p_rvvi_vif.pc_rdata; end else begin : MAIN @@ -1362,7 +1369,7 @@ class uvme_rv32x_hwloop_covg # ( `uvm_info(_header, $sformatf("DEBUG - No prematured hwloops when test done"), UVM_DEBUG); end else begin - `uvm_error(_header, $sformatf("Detected prematured hwloops when test done. Please debug ... ")); + `uvm_error(_header, $sformatf("Detected prematured hwloops when test done. Please debug ... ")); // fixme: to be commented out end endfunction : final_phase From 7cafed81a4837fcf410c3807902f9dcb7238077f Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 26 Dec 2023 15:16:39 +0800 Subject: [PATCH 50/97] fix issue for MAC instructions not getting has_rd set Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv index aa66013e7e..415b1cb1cb 100644 --- a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv +++ b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv @@ -230,7 +230,7 @@ class cv32e40p_instr extends riscv_instr; // special overrides for xcorev // for ALU, there exists variations for R and S types - if (category == ALU) begin + if (category inside {ALU,MAC}) begin if (instr_name inside {CV_CLIP, CV_CLIPU}) has_imm = 1'b1; if (format == S_FORMAT) has_rd = 1'b1; end @@ -698,7 +698,7 @@ class cv32e40p_instr extends riscv_instr; imm_str = $sformatf("%0d", $signed(imm[5:0])); end end else - super.update_imm_str(); + super.update_imm_str(); endfunction // `include "isa/riscv_instr_cov.svh" From 46eee92c67732c6d06e4913025c31b7dcb18a147 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 26 Dec 2023 15:21:36 +0800 Subject: [PATCH 51/97] remove C_SWSP, C_FSWSP from randomize_debug_rom_instr to exclude from debug program Signed-off-by: Vaibhav Jain --- cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv index 1cc876d7dd..a16141c3fa 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_rand_instr_stream.sv @@ -261,7 +261,7 @@ class cv32e40p_rand_instr_stream extends riscv_rand_instr_stream; exclude_instr = {exclude_instr, CV_BEQIMM, CV_BNEIMM, BEQ, BNE, BLT, BGE, BLTU, BGEU, C_BEQZ, C_BNEZ, JALR, JAL, C_JR, C_JALR, C_J, C_JAL}; end - exclude_instr = {exclude_instr, CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW, C_ADDI16SP, URET, SRET, MRET, DRET, ECALL}; + exclude_instr = {exclude_instr, CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW, C_ADDI16SP, C_SWSP, C_FSWSP, URET, SRET, MRET, DRET, ECALL}; instr = riscv_instr::get_rand_instr(.exclude_instr(exclude_instr)); instr.m_cfg = cfg; randomize_gpr(instr); From f288a44dd744b3eb9c6e0a418f93774227ac8334 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 26 Dec 2023 15:27:15 +0800 Subject: [PATCH 52/97] fix issue due to no debug_exception handler causing debug progam gpr,fpr state restore not completed Signed-off-by: Vaibhav Jain --- .../env/corev-dv/cv32e40p_debug_rom_gen.sv | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv index 804a5d236e..855202e7e1 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_debug_rom_gen.sv @@ -174,7 +174,26 @@ class cv32e40p_debug_rom_gen extends riscv_debug_rom_gen; // Insert section info so linker can place // debug exception code at the correct adress instr_stream.push_back(".section .debugger_exception, \"ax\""); - super.gen_debug_exception_handler(); + + // In CV32E40P there is no way to know the Instruction address + // that caused the debug exception entry. + // In these tests, this scenario is simply handled with assumptions: + // - The random illegal exception in debug program is generated + // as part of random instructions + // - And debug stack pointer is not used in any other random + // instruction in debug program + // With these 2 assumptions to ensure smooth continuity of rest of + // the test program, we simply jump to "debug_end" section to exit + // the debug rom properly. + + if (cfg.gen_debug_section) begin + str = {$sformatf("la x%0d, debug_end", cfg.scratch_reg), + $sformatf("jalr x0, x%0d, 0", cfg.scratch_reg), + "dret"}; + gen_section($sformatf("%0sdebug_exception", hart_prefix(hart)), str); + end else begin + super.gen_debug_exception_handler(); + end // Inser section info to place remaining code in the // original section From bec569901c0ed25e3976cbda056314ad28c6a586 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 26 Dec 2023 15:30:42 +0800 Subject: [PATCH 53/97] fix issue due to illegal instr inserted in hwloop body from sequence causing total loop body instr to be more than 30 with cv.setupi Signed-off-by: Vaibhav Jain --- .../cv32e40p_pulp_hwloop_instr_lib.sv | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index 96e253e7ad..edc6b1a4b2 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -277,6 +277,34 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; `uvm_fatal(this.get_type_name(), "cv32e40p_exclude_regs out of range") end + // Ensure the illegal inserted in the sequence function cv32e40p_insert_illegal_hint_instr() + // does not violate the hwloop end label offset limits with cv.setupi instr + // As a workaround here if illegal_instr_ratio is non-zero, + // The number of instructions in hwloop are reduced by 3(Change if + // needed), to allow illegal/hint instr insertion in the sequence. + // The coverage here is not critical as the max range with cv.setupi + // will be exercised in tests without illegals. + if (cfg.illegal_instr_ratio > 0) begin + if(gen_nested_loop) begin + if (use_setup_inst[1] && use_loop_setupi_inst[1] && (num_hwloop_instr[1] >= 28)) begin + num_hwloop_instr[1] = num_hwloop_instr[1] - 3; + if (num_hwloop_instr[0] >= 6) + num_hwloop_instr[0] = num_hwloop_instr[0] - 3; + else + num_hwloop_instr[0] = 3; + end else if (use_setup_inst[0] && use_loop_setupi_inst[0] && (num_hwloop_instr[0] >= 28)) begin + num_hwloop_instr[0] = num_hwloop_instr[0] - 3; + end + end else begin + if (use_setup_inst[1] && use_loop_setupi_inst[1] && (num_hwloop_instr[1] >= 28)) begin + num_hwloop_instr[1] = num_hwloop_instr[1] - 3; + end + if (use_setup_inst[0] && use_loop_setupi_inst[0] && (num_hwloop_instr[0] >= 28)) begin + num_hwloop_instr[0] = num_hwloop_instr[0] - 3; + end + end + end + gen_xpulp_hwloop_control_instr(); endfunction : post_randomize From f932ccb1486f7e182e0f315160d595000f8c6dd3 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 26 Dec 2023 15:31:33 +0800 Subject: [PATCH 54/97] update cv32e40p core hash Signed-off-by: Vaibhav Jain --- cv32e40p/sim/ExternalRepos.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index e51bb24e6f..3b9572f57e 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= d658f650c072bc429ef95aa631dfc186f56b7d4b +CV_CORE_HASH ?= c010206894d1f2143ffcfac751bdb2351d08ffdc CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. From d3ff477d54a487e1ee3c98e4abaa95915a8467f6 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 26 Dec 2023 16:54:01 +0800 Subject: [PATCH 55/97] add gen_limit_debug_req test cfg yaml and modify gen_rand_debug_req for fully random debug req Signed-off-by: Vaibhav Jain --- cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml | 2 +- cv32e40p/tests/test_cfg/gen_limit_debug_req.yaml | 5 +++++ cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) create mode 100644 cv32e40p/tests/test_cfg/gen_limit_debug_req.yaml diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 024ee5294c..4ceaf9fe4b 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -113,7 +113,7 @@ tests: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" - test_cfg: debug_trigger_basic,gen_rand_debug_req + test_cfg: debug_trigger_basic,gen_limit_debug_req debug_test: build: uvmt_cv32e40p diff --git a/cv32e40p/tests/test_cfg/gen_limit_debug_req.yaml b/cv32e40p/tests/test_cfg/gen_limit_debug_req.yaml new file mode 100644 index 0000000000..07bee7902e --- /dev/null +++ b/cv32e40p/tests/test_cfg/gen_limit_debug_req.yaml @@ -0,0 +1,5 @@ +name: gen_limit_debug_req +description: > + Generate few random debug halt requests in range 1 to 5, or use plusarg num_debug_req=val to set number +plusargs: > + +gen_reduced_rand_dbg_req diff --git a/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml b/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml index eff7693166..5692669993 100644 --- a/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml +++ b/cv32e40p/tests/test_cfg/gen_rand_debug_req.yaml @@ -2,4 +2,4 @@ name: gen_rand_debug_req description: > Generate Random debug halt request plusargs: > - +gen_reduced_rand_dbg_req + +gen_random_debug From b86ff58c75a745d1ea0732ecba3352f31ec45236 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 26 Dec 2023 16:55:53 +0800 Subject: [PATCH 56/97] add a new test for hwloop with random interrupts,trigger and ebreak Signed-off-by: Vaibhav Jain --- cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml index 8a3bd04753..2d70bf12fd 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml @@ -103,6 +103,14 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic,debug_single_step_en + corev_rand_pulp_hwloop_debug_with_int_debug_trigger_and_ebreak: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and ebreak random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak + corev_rand_pulp_hwloop_debug_with_int_debug_trigger_single_step: testname: corev_rand_pulp_hwloop_debug description: hwloop debug with interrupt, debug trigger and single step random test From 5c83ea16a81c35dbf8d79115031a348fb0effce7 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 26 Dec 2023 17:00:25 +0800 Subject: [PATCH 57/97] add new tests for debug combinations with corev_rand_pulp_instr_debug and tests with test_cfg gen_rand_debug_req Signed-off-by: Vaibhav Jain --- .../cv32e40pv2_interrupt_debug_short.yaml | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 4ceaf9fe4b..378dd408d2 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -21,6 +21,14 @@ builds: # List of tests tests: + corev_rand_pulp_instr_random_debug_test: + testname: corev_rand_pulp_instr_test + description: pulp instr test with random debug halt req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_debug_req + corev_rand_pulp_instr_ebreak_debug_test: testname: corev_rand_pulp_instr_debug description: pulp rand test with ebreak debug @@ -45,6 +53,46 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: debug_trigger_basic + corev_rand_pulp_instr_debug_trigger_with_ebreak: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with debug trigger and ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_ebreak + + corev_rand_pulp_instr_debug_trigger_with_single_step: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,debug_single_step_en + + corev_rand_pulp_instr_debug_trigger_with_random_debug_req: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with debug trigger and random debug req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_trigger_basic,gen_rand_debug_req + + corev_rand_pulp_instr_debug_ebreak_with_random_debug_req: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with debug ebreak and random debug req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_ebreak,gen_rand_debug_req + + corev_rand_pulp_instr_debug_single_step_with_random_debug_req: + testname: corev_rand_pulp_instr_debug + description: pulp rand test with debug ebreak and random debug req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: debug_single_step_en,gen_rand_debug_req + corev_rand_pulp_instr_interrupt_test: testname: corev_rand_pulp_instr_test description: pulp instr test with random interrupts @@ -53,12 +101,68 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: gen_rand_int + corev_rand_pulp_instr_interrupt_debug_test: + testname: corev_rand_pulp_instr_test + description: pulp instr test with random interrupts and debug halt req + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,gen_rand_debug_req + + corev_rand_pulp_instr_debug_test_with_int_and_debug_trigger: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic + + corev_rand_pulp_instr_debug_test_with_int_and_debug_single_step: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_single_step_en + + corev_rand_pulp_instr_debug_test_with_int_and_debug_ebreak: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt and debug ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_ebreak + + corev_rand_pulp_instr_debug_test_with_int_debug_trigger_and_ebreak: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt, debug trigger and debug ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak + + corev_rand_pulp_instr_debug_test_with_int_debug_trigger_and_single_step: + testname: corev_rand_pulp_instr_debug + description: pulp instr random test with random interrupt, debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + corev_rand_pulp_hwloop_debug: build: uvmt_cv32e40p description: hwloop debug random test dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + corev_rand_pulp_hwloop_test_with_random_debug: + testname: corev_rand_pulp_hwloop_debug + description: hwloop random debug req test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + test_cfg: gen_rand_debug_req + corev_rand_pulp_hwloop_debug_ebreak: testname: corev_rand_pulp_hwloop_debug description: hwloop ebreak debug random test @@ -99,6 +203,14 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" test_cfg: gen_rand_int,debug_trigger_basic + corev_rand_pulp_hwloop_debug_with_int_debug_ebreak: + testname: corev_rand_pulp_hwloop_debug + description: hwloop debug with interrupt and debug ebreak random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + test_cfg: gen_rand_int,debug_ebreak + corev_rand_pulp_hwloop_interrupt_test: testname: corev_rand_pulp_hwloop_test description: hwloop test with random interrupts From 2cdadd58ea0fdf33e9a5a6e978a9488645ff6326 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Tue, 26 Dec 2023 22:55:58 +0800 Subject: [PATCH 58/97] corrected testname Signed-off-by: Vaibhav Jain --- cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 378dd408d2..49b0e89b1c 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -70,7 +70,7 @@ tests: test_cfg: debug_trigger_basic,debug_single_step_en corev_rand_pulp_instr_debug_trigger_with_random_debug_req: - testname: corev_rand_pulp_instr_debug + testname: corev_rand_pulp_instr_test description: pulp rand test with debug trigger and random debug req build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt @@ -78,7 +78,7 @@ tests: test_cfg: debug_trigger_basic,gen_rand_debug_req corev_rand_pulp_instr_debug_ebreak_with_random_debug_req: - testname: corev_rand_pulp_instr_debug + testname: corev_rand_pulp_instr_test description: pulp rand test with debug ebreak and random debug req build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt @@ -86,7 +86,7 @@ tests: test_cfg: debug_ebreak,gen_rand_debug_req corev_rand_pulp_instr_debug_single_step_with_random_debug_req: - testname: corev_rand_pulp_instr_debug + testname: corev_rand_pulp_instr_test description: pulp rand test with debug ebreak and random debug req build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt @@ -156,7 +156,7 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" corev_rand_pulp_hwloop_test_with_random_debug: - testname: corev_rand_pulp_hwloop_debug + testname: corev_rand_pulp_hwloop_test description: hwloop random debug req test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt From b6ada0520de2f6a92d5cb1b2fed0dbbdb94e66aa Mon Sep 17 00:00:00 2001 From: bsm Date: Wed, 27 Dec 2023 10:42:30 +0800 Subject: [PATCH 59/97] Fix issue when exception happen within debug mode Signed-off-by: bsm --- cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 1123ffc656..8ef9a6bea0 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -1222,7 +1222,7 @@ class uvme_rv32x_hwloop_covg # ( ) begin wait (!cv32e40p_rvvi_vif.trap); // bypass if garbage data exist end - else if (cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0 && !pending_irq) begin // set excep flag only if no pending irq + else if (cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0 && !pending_irq && !is_dbg_mode) begin // set excep flag only if no pending irq and not in dbg mode case (cv32e40p_rvvi_vif.insn) INSTR_EBREAK, INSTR_CBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin @(posedge cv32e40p_rvvi_vif.clk); continue; From c5cdd274df995ed798ecb331dc9747449ddf98bd Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 29 Dec 2023 11:11:16 +0800 Subject: [PATCH 60/97] add multiuserenv switch for vcover merge Signed-off-by: bsm --- mk/uvmt/vsim.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk index f4d651b318..fb11d631fe 100644 --- a/mk/uvmt/vsim.mk +++ b/mk/uvmt/vsim.mk @@ -263,7 +263,7 @@ COV_FLAGS = COV_REPORT = cov_report COV_MERGE_TARGET = COV_MERGE_FIND = find $(SIM_CFG_RESULTS) -type f -name "*.ucdb" | grep -v corev-dv > $(VSIM_COV_MERGE_DIR)/ucdb.list -COV_MERGE_FLAGS = merge -testassociated -verbose -64 -out merged.ucdb -inputs ucdb.list +COV_MERGE_FLAGS = merge -testassociated -verbose -64 -multiuserenv -out merged.ucdb -inputs ucdb.list ifeq ($(call IS_YES,$(MERGE)),YES) COV_DIR=$(VSIM_COV_MERGE_DIR) From d4e38a5cab09e1506b45d00e71f0199886fffb83 Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 29 Dec 2023 11:13:40 +0800 Subject: [PATCH 61/97] Add tb params and cov bins macros for ISA instructions Signed-off-by: bsm --- cv32e40p/env/uvme/uvme_cv32e40p_constants.sv | 69 ++ cv32e40p/env/uvme/uvme_cv32e40p_macros.sv | 43 ++ .../env/uvme/uvme_cv32e40p_param_all_insn.sv | 624 ------------------ cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv | 1 - 4 files changed, 112 insertions(+), 625 deletions(-) delete mode 100644 cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv b/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv index 9c089cfbee..46e9c51950 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_constants.sv @@ -76,6 +76,7 @@ parameter TB_OPCODE_OP_FNMSUB = 7'h4b; parameter TB_OPCODE_STORE_FP = 7'h27; parameter TB_OPCODE_LOAD_FP = 7'h07; +// RV32F parameter TB_INS_FMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FMADD}; parameter TB_INS_FMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FMSUB}; parameter TB_INS_FNMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, TB_OPCODE_OP_FNMSUB}; @@ -104,6 +105,74 @@ parameter TB_INS_FLW = {12'b?,5'b?,3'b010,5'b?,TB_OPCODE_LOAD parameter TB_INS_FSW = {7'b?,5'b?,5'b?,3'b010,5'b?,TB_OPCODE_STORE_FP}; +parameter TB_INSTR_LUI = {25'b?, TB_OPCODE_LUI}; +parameter TB_INSTR_AUIPC = {25'b?, TB_OPCODE_AUIPC}; +parameter TB_INSTR_JAL = {25'b?, TB_OPCODE_JAL}; +parameter TB_INSTR_JALR = {17'b?, 3'b000, 5'b?, TB_OPCODE_JALR}; +// BRANCH +parameter TB_INSTR_BEQ = {17'b?, 3'b000, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BNE = {17'b?, 3'b001, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BLT = {17'b?, 3'b100, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BGE = {17'b?, 3'b101, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BLTU = {17'b?, 3'b110, 5'b?, TB_OPCODE_BRANCH}; +parameter TB_INSTR_BGEU = {17'b?, 3'b111, 5'b?, TB_OPCODE_BRANCH}; +// OPIMM +parameter TB_INSTR_ADDI = {17'b?, 3'b000, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SLTI = {17'b?, 3'b010, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SLTIU = {17'b?, 3'b011, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_XORI = {17'b?, 3'b100, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_ORI = {17'b?, 3'b110, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_ANDI = {17'b?, 3'b111, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SLLI = {7'b0000000, 10'b?, 3'b001, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SRLI = {7'b0000000, 10'b?, 3'b101, 5'b?, TB_OPCODE_OPIMM}; +parameter TB_INSTR_SRAI = {7'b0100000, 10'b?, 3'b101, 5'b?, TB_OPCODE_OPIMM}; +// OP +parameter TB_INSTR_ADD = {7'b0000000, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SUB = {7'b0100000, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SLL = {7'b0000000, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SLT = {7'b0000000, 10'b?, 3'b010, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SLTU = {7'b0000000, 10'b?, 3'b011, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_XOR = {7'b0000000, 10'b?, 3'b100, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SRL = {7'b0000000, 10'b?, 3'b101, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_SRA = {7'b0100000, 10'b?, 3'b101, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_OR = {7'b0000000, 10'b?, 3'b110, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_AND = {7'b0000000, 10'b?, 3'b111, 5'b?, TB_OPCODE_OP}; +// FENCE +parameter TB_INSTR_FENCE = {4'b0, 8'b?, 13'b0, TB_OPCODE_FENCE}; +parameter TB_INSTR_FENCEI = {17'b0, 3'b001, 5'b0, TB_OPCODE_FENCE}; +// SYSTEM +parameter TB_INSTR_CSRRW = {17'b?, 3'b001, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRS = {17'b?, 3'b010, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRC = {17'b?, 3'b011, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRWI = {17'b?, 3'b101, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRSI = {17'b?, 3'b110, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_CSRRCI = {17'b?, 3'b111, 5'b?, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_ECALL = {12'b000000000000, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_EBREAK = {12'b000000000001, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_URET = {12'b000000000010, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_SRET = {12'b000100000010, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_MRET = {12'b001100000010, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_DRET = {12'b011110110010, 13'b0, TB_OPCODE_SYSTEM}; +parameter TB_INSTR_WFI = {12'b000100000101, 13'b0, TB_OPCODE_SYSTEM}; +// RV32M +parameter TB_INSTR_DIV = {7'b0000001, 10'b?, 3'b100, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_DIVU = {7'b0000001, 10'b?, 3'b101, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_REM = {7'b0000001, 10'b?, 3'b110, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_REMU = {7'b0000001, 10'b?, 3'b111, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_PMUL = {7'b0000001, 10'b?, 3'b000, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_PMUH = {7'b0000001, 10'b?, 3'b001, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_PMULHSU = {7'b0000001, 10'b?, 3'b010, 5'b?, TB_OPCODE_OP}; +parameter TB_INSTR_PMULHU = {7'b0000001, 10'b?, 3'b011, 5'b?, TB_OPCODE_OP}; +// LOAD STORE +parameter TB_INSTR_LB = {17'b?, 3'b000, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_LH = {17'b?, 3'b001, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_LW = {17'b?, 3'b010, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_LBU = {17'b?, 3'b100, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_LHU = {17'b?, 3'b101, 5'b?, TB_OPCODE_LOAD}; +parameter TB_INSTR_SB = {17'b?, 3'b000, 5'b?, TB_OPCODE_STORE}; +parameter TB_INSTR_SH = {17'b?, 3'b001, 5'b?, TB_OPCODE_STORE}; +parameter TB_INSTR_SW = {17'b?, 3'b010, 5'b?, TB_OPCODE_STORE}; + //XPULP instructions custom opcodes parameter OPCODE_CUSTOM_0 = 7'h0b; parameter OPCODE_CUSTOM_1 = 7'h2b; diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv index 83af8344cd..6a629368c0 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv @@ -87,6 +87,49 @@ wildcard bins fnmsub = {TB_INS_FNMSUB}; \ wildcard bins fnmadd = {TB_INS_FNMADD}; +`define OPIMM_INSTR_BINS \ + wildcard bins addi = {TB_INSTR_ADDI}; \ + wildcard bins slti = {TB_INSTR_SLTI}; \ + wildcard bins sltiu = {TB_INSTR_SLTIU}; \ + wildcard bins xori = {TB_INSTR_XORI}; \ + wildcard bins ori = {TB_INSTR_ORI}; \ + wildcard bins andi = {TB_INSTR_ANDI}; \ + wildcard bins slli = {TB_INSTR_SLLI}; \ + wildcard bins srli = {TB_INSTR_SRLI}; \ + wildcard bins srai = {TB_INSTR_SRAI}; + +`define OP_INSTR_BINS \ + wildcard bins _add = {TB_INSTR_ADD}; \ + wildcard bins _sub = {TB_INSTR_SUB}; \ + wildcard bins _sll = {TB_INSTR_SLL}; \ + wildcard bins _slt = {TB_INSTR_SLT}; \ + wildcard bins _sltu = {TB_INSTR_SLTU}; \ + wildcard bins _xor = {TB_INSTR_XOR}; \ + wildcard bins _srl = {TB_INSTR_SRL}; \ + wildcard bins _sra = {TB_INSTR_SRA}; \ + wildcard bins _or = {TB_INSTR_OR}; \ + wildcard bins _and = {TB_INSTR_AND}; \ + +`define RV32M_INSTR_BINS \ + wildcard bins div = {TB_INSTR_DIV}; \ + wildcard bins divu = {TB_INSTR_DIVU}; \ + wildcard bins rem = {TB_INSTR_REM}; \ + wildcard bins remu = {TB_INSTR_REMU}; \ + wildcard bins pmul = {TB_INSTR_PMUL}; \ + wildcard bins pmuh = {TB_INSTR_PMUH}; \ + wildcard bins pmulhsu = {TB_INSTR_PMULHSU}; \ + wildcard bins pmulhu = {TB_INSTR_PMULHU}; + +`define LOAD_STORE_INSTR_BINS \ + wildcard bins lb = {TB_INSTR_LB}; \ + wildcard bins lh = {TB_INSTR_LH}; \ + wildcard bins lw = {TB_INSTR_LW}; \ + wildcard bins lbu = {TB_INSTR_LBU}; \ + wildcard bins lhu = {TB_INSTR_LHU}; \ + wildcard bins sb = {TB_INSTR_SB}; \ + wildcard bins sh = {TB_INSTR_SH}; \ + wildcard bins sw = {TB_INSTR_SW}; + `define FPU_OP_BINS \ bins apu_op_fmadd = {APU_OP_FMADD}; \ bins apu_op_fnmsub = {APU_OP_FNMSUB}; \ diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv b/cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv deleted file mode 100644 index 6bbfc0ba4e..0000000000 --- a/cv32e40p/env/uvme/uvme_cv32e40p_param_all_insn.sv +++ /dev/null @@ -1,624 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2023 Dolphin Design -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40P_PARAM_ALL_INSN__ -`define __UVME_CV32E40P_PARAM_ALL_INSN__ - -// note: -// 1) below instructions parameters are mirror copy of cv32e40p_pkg.sv and cv32e40p_tracer_pkg.sv -// 2) cv32e40p_pkg.sv is available at /cv32e40p/rtl/include -// 3) cv32e40p_tracer_pkg.sv is available at /cv32e40p/bhv/include - - //////////////////////////////////////////////// - // ___ ____ _ // - // / _ \ _ __ / ___|___ __| | ___ ___ // - // | | | | '_ \| | / _ \ / _` |/ _ \/ __| // - // | |_| | |_) | |__| (_) | (_| | __/\__ \ // - // \___/| .__/ \____\___/ \__,_|\___||___/ // - // |_| // - //////////////////////////////////////////////// - - parameter OPCODE_SYSTEM = 7'h73; - parameter OPCODE_FENCE = 7'h0f; - parameter OPCODE_OP = 7'h33; - parameter OPCODE_OPIMM = 7'h13; - parameter OPCODE_STORE = 7'h23; - parameter OPCODE_LOAD = 7'h03; - parameter OPCODE_BRANCH = 7'h63; - parameter OPCODE_JALR = 7'h67; - parameter OPCODE_JAL = 7'h6f; - parameter OPCODE_AUIPC = 7'h17; - parameter OPCODE_LUI = 7'h37; - parameter OPCODE_OP_FP = 7'h53; - parameter OPCODE_OP_FMADD = 7'h43; - parameter OPCODE_OP_FNMADD = 7'h4f; - parameter OPCODE_OP_FMSUB = 7'h47; - parameter OPCODE_OP_FNMSUB = 7'h4b; - parameter OPCODE_STORE_FP = 7'h27; - parameter OPCODE_LOAD_FP = 7'h07; - parameter OPCODE_AMO = 7'h2F; - // Those custom opcodes are used for PULP custom instructions - // parameter OPCODE_CUSTOM_0 = 7'h0b; - // parameter OPCODE_CUSTOM_1 = 7'h2b; - // parameter OPCODE_CUSTOM_2 = 7'h5b; - // parameter OPCODE_CUSTOM_3 = 7'h7b; - - // Atomic operations - parameter AMO_LR = 5'b00010; - parameter AMO_SC = 5'b00011; - parameter AMO_SWAP = 5'b00001; - parameter AMO_ADD = 5'b00000; - parameter AMO_XOR = 5'b00100; - parameter AMO_AND = 5'b01100; - parameter AMO_OR = 5'b01000; - parameter AMO_MIN = 5'b10000; - parameter AMO_MAX = 5'b10100; - parameter AMO_MINU = 5'b11000; - parameter AMO_MAXU = 5'b11100; - - // instruction masks (for tracer) - parameter INSTR_LUI = {25'b?, OPCODE_LUI}; - parameter INSTR_AUIPC = {25'b?, OPCODE_AUIPC}; - parameter INSTR_JAL = {25'b?, OPCODE_JAL}; - parameter INSTR_JALR = {17'b?, 3'b000, 5'b?, OPCODE_JALR}; - // BRANCH - parameter INSTR_BEQ = {17'b?, 3'b000, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BNE = {17'b?, 3'b001, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BLT = {17'b?, 3'b100, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BGE = {17'b?, 3'b101, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BLTU = {17'b?, 3'b110, 5'b?, OPCODE_BRANCH}; - parameter INSTR_BGEU = {17'b?, 3'b111, 5'b?, OPCODE_BRANCH}; - // OPIMM - parameter INSTR_ADDI = {17'b?, 3'b000, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SLTI = {17'b?, 3'b010, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SLTIU = {17'b?, 3'b011, 5'b?, OPCODE_OPIMM}; - parameter INSTR_XORI = {17'b?, 3'b100, 5'b?, OPCODE_OPIMM}; - parameter INSTR_ORI = {17'b?, 3'b110, 5'b?, OPCODE_OPIMM}; - parameter INSTR_ANDI = {17'b?, 3'b111, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SLLI = {7'b0000000, 10'b?, 3'b001, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SRLI = {7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OPIMM}; - parameter INSTR_SRAI = {7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OPIMM}; - // OP - parameter INSTR_ADD = {7'b0000000, 10'b?, 3'b000, 5'b?, OPCODE_OP}; - parameter INSTR_SUB = {7'b0100000, 10'b?, 3'b000, 5'b?, OPCODE_OP}; - parameter INSTR_SLL = {7'b0000000, 10'b?, 3'b001, 5'b?, OPCODE_OP}; - parameter INSTR_SLT = {7'b0000000, 10'b?, 3'b010, 5'b?, OPCODE_OP}; - parameter INSTR_SLTU = {7'b0000000, 10'b?, 3'b011, 5'b?, OPCODE_OP}; - parameter INSTR_XOR = {7'b0000000, 10'b?, 3'b100, 5'b?, OPCODE_OP}; - parameter INSTR_SRL = {7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OP}; - parameter INSTR_SRA = {7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OP}; - parameter INSTR_OR = {7'b0000000, 10'b?, 3'b110, 5'b?, OPCODE_OP}; - parameter INSTR_AND = {7'b0000000, 10'b?, 3'b111, 5'b?, OPCODE_OP}; - - parameter INSTR_PAVG = {7'b0000010, 10'b?, 3'b000, 5'b?, OPCODE_OP}; - parameter INSTR_PAVGU = {7'b0000010, 10'b?, 3'b001, 5'b?, OPCODE_OP}; - - // FENCE - parameter INSTR_FENCE = {4'b0, 8'b?, 13'b0, OPCODE_FENCE}; - parameter INSTR_FENCEI = {17'b0, 3'b001, 5'b0, OPCODE_FENCE}; - // SYSTEM - parameter INSTR_CSRRW = {17'b?, 3'b001, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRS = {17'b?, 3'b010, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRC = {17'b?, 3'b011, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRWI = {17'b?, 3'b101, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRSI = {17'b?, 3'b110, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_CSRRCI = {17'b?, 3'b111, 5'b?, OPCODE_SYSTEM}; - parameter INSTR_ECALL = {12'b000000000000, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_EBREAK = {12'b000000000001, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_URET = {12'b000000000010, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_SRET = {12'b000100000010, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_MRET = {12'b001100000010, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_DRET = {12'b011110110010, 13'b0, OPCODE_SYSTEM}; - parameter INSTR_WFI = {12'b000100000101, 13'b0, OPCODE_SYSTEM}; - - // RV32M - parameter INSTR_DIV = {7'b0000001, 10'b?, 3'b100, 5'b?, OPCODE_OP}; - parameter INSTR_DIVU = {7'b0000001, 10'b?, 3'b101, 5'b?, OPCODE_OP}; - parameter INSTR_REM = {7'b0000001, 10'b?, 3'b110, 5'b?, OPCODE_OP}; - parameter INSTR_REMU = {7'b0000001, 10'b?, 3'b111, 5'b?, OPCODE_OP}; - parameter INSTR_PMUL = {7'b0000001, 10'b?, 3'b000, 5'b?, OPCODE_OP}; - parameter INSTR_PMUH = {7'b0000001, 10'b?, 3'b001, 5'b?, OPCODE_OP}; - parameter INSTR_PMULHSU = {7'b0000001, 10'b?, 3'b010, 5'b?, OPCODE_OP}; - parameter INSTR_PMULHU = {7'b0000001, 10'b?, 3'b011, 5'b?, OPCODE_OP}; - - // RV32F - parameter INSTR_FMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FMADD}; - parameter INSTR_FMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FMSUB}; - parameter INSTR_FNMSUB = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FNMSUB}; - parameter INSTR_FNMADD = {5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FNMADD}; - - parameter INSTR_FADD = {5'b00000, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSUB = {5'b00001, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMUL = {5'b00010, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FDIV = {5'b00011, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSQRT = {5'b01011, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSGNJS = {5'b00100, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSGNJNS = {5'b00100, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FSGNJXS = {5'b00100, 2'b00, 10'b?, 3'b010, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMIN = {5'b00101, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMAX = {5'b00101, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCVTWS = {5'b11000, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCVTWUS = {5'b11000, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMVXS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FEQS = {5'b10100, 2'b00, 10'b?, 3'b010, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FLTS = {5'b10100, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FLES = {5'b10100, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCLASS = {5'b11100, 2'b00, 5'b0, 5'b?, 3'b001, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCVTSW = {5'b11010, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FCVTSWU = {5'b11010, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP}; - parameter INSTR_FMVSX = {5'b11110, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_OP_FP}; - - // RV32A - parameter INSTR_LR = {AMO_LR, 2'b?, 5'b0, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_SC = {AMO_SC, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOSWAP = {AMO_SWAP, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOADD = {AMO_ADD, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOXOR = {AMO_XOR, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOAND = {AMO_AND, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOOR = {AMO_OR, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOMIN = {AMO_MIN, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOMAX = {AMO_MAX, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOMINU = {AMO_MINU, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - parameter INSTR_AMOMAXU = {AMO_MAXU, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO}; - - - // LOAD STORE - parameter INSTR_LB = {17'b?, 3'b000, 5'b?, OPCODE_LOAD}; - parameter INSTR_LH = {17'b?, 3'b001, 5'b?, OPCODE_LOAD}; - parameter INSTR_LW = {17'b?, 3'b010, 5'b?, OPCODE_LOAD}; - parameter INSTR_LBU = {17'b?, 3'b100, 5'b?, OPCODE_LOAD}; - parameter INSTR_LHU = {17'b?, 3'b101, 5'b?, OPCODE_LOAD}; - - parameter INSTR_SB = {17'b?, 3'b000, 5'b?, OPCODE_STORE}; - parameter INSTR_SH = {17'b?, 3'b001, 5'b?, OPCODE_STORE}; - parameter INSTR_SW = {17'b?, 3'b010, 5'b?, OPCODE_STORE}; - - // parameter INSTR_FL = {OPCODE_LOAD_FP}; - // parameter INSTR_FS = {OPCODE_STORE_FP} - - // CUSTOM_0 - parameter INSTR_BEQIMM = {17'b?, 3'b110, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_BNEIMM = {17'b?, 3'b111, 5'b?, OPCODE_CUSTOM_0}; - - // Post-Increment Register-Immediate Load - parameter INSTR_CVLBI = {17'b?, 3'b000, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_CVLBUI = {17'b?, 3'b100, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_CVLHI = {17'b?, 3'b001, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_CVLHUI = {17'b?, 3'b101, 5'b?, OPCODE_CUSTOM_0}; - parameter INSTR_CVLWI = {17'b?, 3'b010, 5'b?, OPCODE_CUSTOM_0}; - - // Event Load - parameter INSTR_CVELW = {17'b?, 3'b011, 5'b?, OPCODE_CUSTOM_0}; - - // CUSTOM_1 - // Post-Increment Register-Register Load - parameter INSTR_CVLBR = {7'b0000000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLBUR = {7'b0001000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLHR = {7'b0000001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLHUR = {7'b0001001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLWR = {7'b0000010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // Register-Register Load - parameter INSTR_CVLBRR = {7'b0000100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLBURR = {7'b0001100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLHRR = {7'b0000101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLHURR = {7'b0001101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVLWRR = {7'b0000110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // Post-Increment Register-Immediate Store - parameter INSTR_CVSBI = {17'b?, 3'b000, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSHI = {17'b?, 3'b001, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSWI = {17'b?, 3'b010, 5'b?, OPCODE_CUSTOM_1}; - - // Post-Increment Register-Register Store operations encoding - parameter INSTR_CVSBR = {7'b0010000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSHR = {7'b0010001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSWR = {7'b0010010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // Register-Register Store operations - parameter INSTR_CVSBRR = {7'b0010100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSHRR = {7'b0010101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CVSWRR = {7'b0010110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // Hardware Loops - parameter INSTR_CVSTARTI0 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVSTART0 = {12'b000000000000, 5'b?, 3'b100, 4'b0001, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVSENDI0 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVEND0 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVCOUNTI0 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVCOUNT0 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVSETUPI0 = {17'b?, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1}; - parameter INSTR_CVSETUP0 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1}; - - parameter INSTR_CVSTARTI1 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVSTART1 = {12'b000000000000, 5'b?, 3'b100, 4'b0001, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVSENDI1 = {12'b?, 5'b00000, 3'b100, 4'b0010, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVEND1 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVCOUNTI1 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVCOUNT1 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVSETUPI1 = {17'b?, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1}; - parameter INSTR_CVSETUP1 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1}; - - - parameter INSTR_FF1 = {7'b0100001, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_FL1 = {7'b0100010, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CLB = {7'b0100011, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_CNT = {7'b0100100, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_EXTHS = {7'b0110000, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_EXTHZ = {7'b0110001, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_EXTBS = {7'b0110010, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_EXTBZ = {7'b0110011, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PADDNR = {7'b1000000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PADDUNR = {7'b1000001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PADDRNR = {7'b1000010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PADDURNR = {7'b1000011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSUBNR = {7'b1000100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSUBUNR = {7'b1000101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSUBRNR = {7'b1000110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSUBURNR = {7'b1000111, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PABS = {7'b0101000, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PCLIP = {7'b0111000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PCLIPU = {7'b0111001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PCLIPR = {7'b0111010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PCLIPUR = {7'b0111011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PSLET = {7'b0101001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PSLETU = {7'b0101010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMIN = {7'b0101011, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMINU = {7'b0101100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMAX = {7'b0101101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMAXU = {7'b0101110, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_ROR = {7'b0100000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PBEXTR = {7'b0011000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PBEXTUR = {7'b0011001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PBINSR = {7'b0011010, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PBCLRR = {7'b0011100, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PBSETR = {7'b0011101, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - parameter INSTR_PMAC = {7'b1001000, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - parameter INSTR_PMSU = {7'b1001001, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1}; - - // CUSTOM_2 - parameter INSTR_PBEXT = {2'b00, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBEXTU = {2'b01, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBINS = {2'b10, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBCLR = {2'b00, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBSET = {2'b01, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PBREV = {2'b11, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_2}; - - parameter INSTR_PADDN = {2'b00, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PADDUN = {2'b01, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PADDRN = {2'b10, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PADDURN = {2'b11, 15'b?, 3'b010, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PSUBN = {2'b00, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PSUBUN = {2'b01, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PSUBRN = {2'b10, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PSUBURN = {2'b11, 15'b?, 3'b011, 5'b?, OPCODE_CUSTOM_2}; - - parameter INSTR_PMULSN = {2'b00, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULHHSN = {2'b01, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULSRN = {2'b10, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULHHSRN = {2'b11, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULUN = {2'b00, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULHHUN = {2'b01, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULURN = {2'b10, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMULHHURN = {2'b11, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACSN = {2'b00, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACHHSN = {2'b01, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACSRN = {2'b10, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACHHSRN = {2'b11, 5'b?, 10'b?, 3'b110, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACUN = {2'b00, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACHHUN = {2'b01, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACURN = {2'b10, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; - parameter INSTR_PMACHHURN = {2'b11, 5'b?, 10'b?, 3'b111, 5'b?, OPCODE_CUSTOM_2}; - - - // CUSTOM_3 - // SIMD ALU - parameter INSTR_CVADDH = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDSCH = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDSCIH = {5'b00000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDB = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDSCB = {5'b00000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDSCIB = {5'b00000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSUBH = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBSCH = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBSCIH = {5'b00001, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBB = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBSCB = {5'b00001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBSCIB = {5'b00001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVAVGH = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGSCH = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGSCIH = {5'b00010, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGB = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGSCB = {5'b00010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGSCIB = {5'b00010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVAVGUH = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUSCH = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUSCIH = {5'b00011, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUB = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUSCB = {5'b00011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVAVGUSCIB = {5'b00011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVMINH = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINSCH = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINSCIH = {5'b00100, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINB = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINSCB = {5'b00100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINSCIB = {5'b00100, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVMINUH = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUSCH = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUSCIH = {5'b00101, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUB = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUSCB = {5'b00101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMINUSCIB = {5'b00101, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVMAXH = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXSCH = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXSCIH = {5'b00110, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXB = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXSCB = {5'b00110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXSCIB = {5'b00110, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVMAXUH = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUSCH = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUSCIH = {5'b00111, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUB = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUSCB = {5'b00111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVMAXUSCIB = {5'b00111, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSRLH = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLSCH = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLSCIH = {5'b01000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLB = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLSCB = {5'b01000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRLSCIB = {5'b01000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSRAH = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRASCH = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRASCIH = {5'b01001, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRAB = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRASCB = {5'b01001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSRASCIB = {5'b01001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSLLH = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLSCH = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLSCIH = {5'b01010, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLB = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLSCB = {5'b01010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSLLSCIB = {5'b01010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVORH = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORSCH = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORSCIH = {5'b01011, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORB = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORSCB = {5'b01011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVORSCIB = {5'b01011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVXORH = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORSCH = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORSCIH = {5'b01100, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORB = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORSCB = {5'b01100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVXORSCIB = {5'b01100, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVANDH = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDSCH = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDSCIH = {5'b01101, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDB = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDSCB = {5'b01101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVANDSCIB = {5'b01101, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVABSH = {5'b01110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVABSB = {5'b01110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVEXTRACTH = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVEXTRACTB = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVEXTRACTUH = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVEXTRACTUB = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVINSERTH = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVINSERTB = {5'b10111, 1'b0, 6'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVDOTUPH = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPSCH = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPSCIH = {5'b10000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPB = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPSCB = {5'b10000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUPSCIB = {5'b10000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVDOTUSPH = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPSCH = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPSCIH = {5'b10001, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPB = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPSCB = {5'b10001, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTUSPSCIB = {5'b10001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVDOTSPH = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPSCH = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPSCIH = {5'b10010, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPB = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPSCB = {5'b10010, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVDOTSPSCIB = {5'b10010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSDOTUPH = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPSCH = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPSCIH = {5'b10011, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPB = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPSCB = {5'b10011, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUPSCIB = {5'b10011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSDOTUSPH = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPSCH = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPSCIH = {5'b10100, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPB = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPSCB = {5'b10100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTUSPSCIB = {5'b10100, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSDOTSPH = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPSCH = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPSCIH = {5'b10101, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPB = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPSCB = {5'b10101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSDOTSPSCIB = {5'b10101, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSHUFFLEH = {5'b11000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLESCIH = {5'b11000, 1'b0, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEB = {5'b11000, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEL0SCIB = {5'b11000, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEL1SCIB = {5'b11001, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEL2SCIB = {5'b11010, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLEL3SCIB = {5'b11011, 1'b0, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSHUFFLE2H = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSHUFFLE2B = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVPACK = {5'b11110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVPACKH = {5'b11110, 1'b0, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVPACKHIB = {5'b11111, 1'b0, 1'b1, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVPACKLOB = {5'b11111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - - // SIMD COMPARISON - parameter INSTR_CVCMPEQH = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQSCH = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQSCIH = {5'b00000, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQB = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQSCB = {5'b00000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPEQSCIB = {5'b00000, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPNEH = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNESCH = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNESCIH = {5'b00001, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNEB = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNESCB = {5'b00001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPNESCIB = {5'b00001, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPGTH = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTSCH = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTSCIH = {5'b00010, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTB = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTSCB = {5'b00010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTSCIB = {5'b00010, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPGEH = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGESCH = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGESCIH = {5'b00011, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEB = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGESCB = {5'b00011, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGESCIB = {5'b00011, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPLTH = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTSCH = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTSCIH = {5'b00100, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTB = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTSCB = {5'b00100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTSCIB = {5'b00100, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPLEH = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLESCH = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLESCIH = {5'b00101, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEB = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLESCB = {5'b00101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLESCIB = {5'b00101, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPGTUH = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUSCH = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUSCIH = {5'b00110, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUB = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUSCB = {5'b00110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGTUSCIB = {5'b00110, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPGEUH = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUSCH = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUSCIH = {5'b00111, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUB = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUSCB = {5'b00111, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPGEUSCIB = {5'b00111, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPLTUH = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUSCH = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUSCIH = {5'b01000, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUB = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUSCB = {5'b01000, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLTUSCIB = {5'b01000, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVCMPLEUH = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUSCH = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUSCIH = {5'b01001, 1'b1, 6'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUB = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUSCB = {5'b01001, 1'b1, 1'b0, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCMPLEUSCIB = {5'b01001, 1'b1, 6'b?, 5'b?, 3'b111, 5'b?, OPCODE_CUSTOM_3}; - - // SIMD CPLX - parameter INSTR_CVCPLXMULR = {5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCPLXMULRDIV2 = { - 5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVCPLXMULRDIV4 = { - 5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVCPLXMULRDIV8 = { - 5'b01010, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3 - }; - - parameter INSTR_CVCPLXMULI = {5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVCPLXMULIDIV2 = { - 5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVCPLXMULIDIV4 = { - 5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVCPLXMULIDIV8 = { - 5'b01010, 1'b1, 1'b1, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3 - }; - - parameter INSTR_CVCPLXCONJ = { - 5'b01011, 1'b1, 1'b0, 5'b00000, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3 - }; - - parameter INSTR_CVSUBROTMJ = {5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBROTMJDIV2 = { - 5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVSUBROTMJDIV4 = { - 5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3 - }; - parameter INSTR_CVSUBROTMJDIV8 = { - 5'b01100, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3 - }; - - parameter INSTR_CVADDIV2 = {5'b01101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDIV4 = {5'b01101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVADDIV8 = {5'b01101, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - - parameter INSTR_CVSUBIV2 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBIV4 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_CUSTOM_3}; - parameter INSTR_CVSUBIV8 = {5'b01110, 1'b1, 1'b0, 5'b?, 5'b?, 3'b110, 5'b?, OPCODE_CUSTOM_3}; - - // Load-Store (RV32F) - parameter INSTR_FLW = {17'b?, 3'b010, 5'b?, OPCODE_LOAD_FP}; - parameter INSTR_FSW = {17'b?, 3'b010, 5'b?, OPCODE_STORE_FP}; - -`endif diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv index 5bca471003..18d50f4ed4 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_pkg.sv @@ -51,7 +51,6 @@ package uvme_cv32e40p_pkg; // Constants / Structs / Enums `include "uvme_cv32e40p_constants.sv" - `include "uvme_cv32e40p_param_all_insn.sv" // fixme: remove this and import package from core-v-cores (e.g cv32e40p_tracer_pkg.sv) `include "uvme_cv32e40p_tdefs.sv" cv32e40p_isa_ext_t cv32e40p_core_isa_list[$] = `CV32E40P_ISA_DV; // CV32E40P supported ISAs From 61b536ffddeeb3220846e7b4e05ff2e6d474a91d Mon Sep 17 00:00:00 2001 From: bsm Date: Fri, 29 Dec 2023 11:16:47 +0800 Subject: [PATCH 62/97] allow hwloop cvg model need to handle exception within debug mode scenario Signed-off-by: bsm --- .../env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 533 +++--------------- 1 file changed, 66 insertions(+), 467 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 8ef9a6bea0..e0ebb32c59 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -112,6 +112,7 @@ class uvme_rv32x_hwloop_covg # ( bit en_cvg_sampling = 1; bit in_nested_loop0 = 0, in_nested_loop0_d1 = 0; bit is_ebreak = 0, is_ebreakm = 0, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0, is_mc_insn = 0; + bit is_trap = 0; // trap any period that is redundant due to handling entry which causes data flush bit enter_hwloop_sub = 0; bit pending_irq = 0; logic [31:0] prev_irq_onehot_priority = 0, prev_irq_onehot_priority_always = 0; @@ -224,40 +225,15 @@ class uvme_rv32x_hwloop_covg # ( } \ cp_hwloop_mc_insn : coverpoint (insn) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_mc_insn) { \ // RV32F \ - wildcard bins instr_fmadd = {INSTR_FMADD}; \ - wildcard bins instr_fmsub = {INSTR_FMSUB}; \ - wildcard bins instr_fnmsub = {INSTR_FNMSUB}; \ - wildcard bins instr_fnmadd = {INSTR_FNMADD}; \ - wildcard bins instr_fadd = {INSTR_FADD}; \ - wildcard bins instr_fsub = {INSTR_FSUB}; \ - wildcard bins instr_fmul = {INSTR_FMUL}; \ - wildcard bins instr_fdiv = {INSTR_FDIV}; \ - wildcard bins instr_fsqrt = {INSTR_FSQRT}; \ - wildcard bins instr_fsgnjs = {INSTR_FSGNJS}; \ - wildcard bins instr_fsgnjns = {INSTR_FSGNJNS}; \ - wildcard bins instr_fsgnjxs = {INSTR_FSGNJXS}; \ - wildcard bins instr_fmin = {INSTR_FMIN}; \ - wildcard bins instr_fmax = {INSTR_FMAX}; \ - wildcard bins instr_fcvtws = {INSTR_FCVTWS}; \ - wildcard bins instr_fcvtwus = {INSTR_FCVTWUS}; \ - wildcard bins instr_fmvxs = {INSTR_FMVXS}; \ - wildcard bins instr_feqs = {INSTR_FEQS}; \ - wildcard bins instr_flts = {INSTR_FLTS}; \ - wildcard bins instr_fles = {INSTR_FLES}; \ - wildcard bins instr_fclass = {INSTR_FCLASS}; \ - wildcard bins instr_fcvtsw = {INSTR_FCVTSW}; \ - wildcard bins instr_fcvtswu = {INSTR_FCVTSWU}; \ - wildcard bins instr_fmvsx = {INSTR_FMVSX}; \ - wildcard bins instr_flw = {INSTR_FLW}; \ - wildcard bins instr_fsw = {INSTR_FSW}; \ + `RV32F_INSTR_BINS \ // RV32M \ - wildcard bins instr_div = {INSTR_DIV}; \ - wildcard bins instr_divu = {INSTR_DIVU}; \ - wildcard bins instr_rem = {INSTR_REM}; \ - wildcard bins instr_remu = {INSTR_REMU}; \ - wildcard bins instr_pmuh = {INSTR_PMUH}; \ - wildcard bins instr_pmulhsu = {INSTR_PMULHSU}; \ - wildcard bins instr_pmulhu = {INSTR_PMULHU}; \ + wildcard bins div = {TB_INSTR_DIV}; \ + wildcard bins divu = {TB_INSTR_DIVU}; \ + wildcard bins rem = {TB_INSTR_REM}; \ + wildcard bins remu = {TB_INSTR_REMU}; \ + wildcard bins pmuh = {TB_INSTR_PMUH}; \ + wildcard bins pmulhsu = {TB_INSTR_PMULHSU}; \ + wildcard bins pmulhu = {TB_INSTR_PMULHU}; \ } \ cp_hwloop_loc : coverpoint (evt_loc) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_event_loc) { \ bins loc_lpstart = {LOC_LPSTART}; \ @@ -268,432 +244,34 @@ class uvme_rv32x_hwloop_covg # ( } \ // note: hwloop setup custom instructions are not allow in hwloop_0 (manual exclusion needed) \ cp_insn_list_in_hwloop : coverpoint (insn) iff (hwloop_stat.execute_instr_in_hwloop[``LOOP_IDX``] && hwloop_cov.en_cov_insn) { \ - wildcard bins instr_lui = {INSTR_LUI}; \ - wildcard bins instr_auipc = {INSTR_AUIPC}; \ + wildcard bins lui = {TB_INSTR_LUI}; \ + wildcard bins auipc = {TB_INSTR_AUIPC}; \ // OPIMM \ - wildcard bins instr_addi = {INSTR_ADDI}; \ - wildcard bins instr_slti = {INSTR_SLTI}; \ - wildcard bins instr_sltiu = {INSTR_SLTIU}; \ - wildcard bins instr_xori = {INSTR_XORI}; \ - wildcard bins instr_ori = {INSTR_ORI}; \ - wildcard bins instr_andi = {INSTR_ANDI}; \ - wildcard bins instr_slli = {INSTR_SLLI}; \ - wildcard bins instr_srli = {INSTR_SRLI}; \ - wildcard bins instr_srai = {INSTR_SRAI}; \ + `OPIMM_INSTR_BINS \ // OP \ - wildcard bins instr_add = {INSTR_ADD}; \ - wildcard bins instr_sub = {INSTR_SUB}; \ - wildcard bins instr_sll = {INSTR_SLL}; \ - wildcard bins instr_slt = {INSTR_SLT}; \ - wildcard bins instr_sltu = {INSTR_SLTU}; \ - wildcard bins instr_xor = {INSTR_XOR}; \ - wildcard bins instr_srl = {INSTR_SRL}; \ - wildcard bins instr_sra = {INSTR_SRA}; \ - wildcard bins instr_or = {INSTR_OR}; \ - wildcard bins instr_and = {INSTR_AND}; \ - wildcard bins instr_pavg = {INSTR_PAVG}; \ - wildcard bins instr_pavgu = {INSTR_PAVGU}; \ + `OP_INSTR_BINS \ // SYSTEM \ - wildcard bins instr_csrrw = {INSTR_CSRRW}; \ - wildcard bins instr_csrrs = {INSTR_CSRRS}; \ - wildcard bins instr_csrrc = {INSTR_CSRRC}; \ - wildcard bins instr_csrrwi = {INSTR_CSRRWI}; \ - wildcard bins instr_csrrsi = {INSTR_CSRRSI}; \ - wildcard bins instr_csrrci = {INSTR_CSRRCI}; \ - wildcard bins instr_ecall = {INSTR_ECALL}; \ - wildcard bins instr_ebreak = {INSTR_EBREAK}; \ + wildcard bins csrrw = {TB_INSTR_CSRRW}; \ + wildcard bins csrrs = {TB_INSTR_CSRRS}; \ + wildcard bins csrrc = {TB_INSTR_CSRRC}; \ + wildcard bins csrrwi = {TB_INSTR_CSRRWI}; \ + wildcard bins csrrsi = {TB_INSTR_CSRRSI}; \ + wildcard bins csrrci = {TB_INSTR_CSRRCI}; \ + wildcard bins ecall = {TB_INSTR_ECALL}; \ + wildcard bins ebreak = {TB_INSTR_EBREAK}; \ // RV32M \ - wildcard bins instr_div = {INSTR_DIV}; \ - wildcard bins instr_divu = {INSTR_DIVU}; \ - wildcard bins instr_rem = {INSTR_REM}; \ - wildcard bins instr_remu = {INSTR_REMU}; \ - wildcard bins instr_pmul = {INSTR_PMUL}; \ - wildcard bins instr_pmuh = {INSTR_PMUH}; \ - wildcard bins instr_pmulhsu = {INSTR_PMULHSU}; \ - wildcard bins instr_pmulhu = {INSTR_PMULHU}; \ + `RV32M_INSTR_BINS \ // RV32F \ - wildcard bins instr_fmadd = {INSTR_FMADD}; \ - wildcard bins instr_fmsub = {INSTR_FMSUB}; \ - wildcard bins instr_fnmsub = {INSTR_FNMSUB}; \ - wildcard bins instr_fnmadd = {INSTR_FNMADD}; \ - wildcard bins instr_fadd = {INSTR_FADD}; \ - wildcard bins instr_fsub = {INSTR_FSUB}; \ - wildcard bins instr_fmul = {INSTR_FMUL}; \ - wildcard bins instr_fdiv = {INSTR_FDIV}; \ - wildcard bins instr_fsqrt = {INSTR_FSQRT}; \ - wildcard bins instr_fsgnjs = {INSTR_FSGNJS}; \ - wildcard bins instr_fsgnjns = {INSTR_FSGNJNS}; \ - wildcard bins instr_fsgnjxs = {INSTR_FSGNJXS}; \ - wildcard bins instr_fmin = {INSTR_FMIN}; \ - wildcard bins instr_fmax = {INSTR_FMAX}; \ - wildcard bins instr_fcvtws = {INSTR_FCVTWS}; \ - wildcard bins instr_fcvtwus = {INSTR_FCVTWUS}; \ - wildcard bins instr_fmvxs = {INSTR_FMVXS}; \ - wildcard bins instr_feqs = {INSTR_FEQS}; \ - wildcard bins instr_flts = {INSTR_FLTS}; \ - wildcard bins instr_fles = {INSTR_FLES}; \ - wildcard bins instr_fclass = {INSTR_FCLASS}; \ - wildcard bins instr_fcvtsw = {INSTR_FCVTSW}; \ - wildcard bins instr_fcvtswu = {INSTR_FCVTSWU}; \ - wildcard bins instr_fmvsx = {INSTR_FMVSX}; \ + `RV32F_INSTR_BINS \ // LOAD STORE \ - wildcard bins instr_lb = {INSTR_LB}; \ - wildcard bins instr_lh = {INSTR_LH}; \ - wildcard bins instr_lw = {INSTR_LW}; \ - wildcard bins instr_lbu = {INSTR_LBU}; \ - wildcard bins instr_lhu = {INSTR_LHU}; \ - wildcard bins instr_sb = {INSTR_SB}; \ - wildcard bins instr_sh = {INSTR_SH}; \ - wildcard bins instr_sw = {INSTR_SW}; \ - // CUSTOM_0 \ - // Post-Increment Register-Immediate Load \ - wildcard bins instr_cvlbi = {INSTR_CVLBI}; \ - wildcard bins instr_cvlbui = {INSTR_CVLBUI}; \ - wildcard bins instr_cvlhi = {INSTR_CVLHI}; \ - wildcard bins instr_cvlhui = {INSTR_CVLHUI}; \ - wildcard bins instr_cvlwi = {INSTR_CVLWI}; \ - // Event Load \ - wildcard bins instr_cvelw = {INSTR_CVELW}; \ - // CUSTOM_1 \ - // Post-Increment Register-Register Load \ - wildcard bins instr_cvlbr = {INSTR_CVLBR}; \ - wildcard bins instr_cvlbur = {INSTR_CVLBUR}; \ - wildcard bins instr_cvlhr = {INSTR_CVLHR}; \ - wildcard bins instr_cvlhur = {INSTR_CVLHUR}; \ - wildcard bins instr_cvlwr = {INSTR_CVLWR}; \ - // Register-Register Load \ - wildcard bins instr_cvlbrr = {INSTR_CVLBRR}; \ - wildcard bins instr_cvlburr = {INSTR_CVLBURR}; \ - wildcard bins instr_cvlhrr = {INSTR_CVLHRR}; \ - wildcard bins instr_cvlhurr = {INSTR_CVLHURR}; \ - wildcard bins instr_cvlwrr = {INSTR_CVLWRR}; \ - // Post-Increment Register-Immediate Store \ - wildcard bins instr_cvsbi = {INSTR_CVSBI}; \ - wildcard bins instr_cvshi = {INSTR_CVSHI}; \ - wildcard bins instr_cvswi = {INSTR_CVSWI}; \ - // Post-Increment Register-Register Store operations encoding \ - wildcard bins instr_cvsbr = {INSTR_CVSBR}; \ - wildcard bins instr_cvshr = {INSTR_CVSHR}; \ - wildcard bins instr_cvswr = {INSTR_CVSWR}; \ - // Register-Register Store operations \ - wildcard bins instr_cvsbrr = {INSTR_CVSBRR}; \ - wildcard bins instr_cvshrr = {INSTR_CVSHRR}; \ - wildcard bins instr_cvswrr = {INSTR_CVSWRR}; \ - // Hardware Loops \ - wildcard bins instr_cvstarti0 = {INSTR_CVSTARTI0}; \ - wildcard bins instr_cvstart0 = {INSTR_CVSTART0}; \ - wildcard bins instr_cvsendi0 = {INSTR_CVSENDI0}; \ - wildcard bins instr_cvend0 = {INSTR_CVEND0}; \ - wildcard bins instr_cvcounti0 = {INSTR_CVCOUNTI0}; \ - wildcard bins instr_cvcount0 = {INSTR_CVCOUNT0}; \ - wildcard bins instr_cvsetupi0 = {INSTR_CVSETUPI0}; \ - wildcard bins instr_cvsetup0 = {INSTR_CVSETUP0}; \ - wildcard bins instr_cvstarti1 = {INSTR_CVSTARTI1}; \ - wildcard bins instr_cvstart1 = {INSTR_CVSTART1}; \ - wildcard bins instr_cvsendi1 = {INSTR_CVSENDI1}; \ - wildcard bins instr_cvend1 = {INSTR_CVEND1}; \ - wildcard bins instr_cvcounti1 = {INSTR_CVCOUNTI1}; \ - wildcard bins instr_cvcount1 = {INSTR_CVCOUNT1}; \ - wildcard bins instr_cvsetupi1 = {INSTR_CVSETUPI1}; \ - wildcard bins instr_cvsetup1 = {INSTR_CVSETUP1}; \ - wildcard bins instr_ff1 = {INSTR_FF1}; \ - wildcard bins instr_fl1 = {INSTR_FL1}; \ - wildcard bins instr_clb = {INSTR_CLB}; \ - wildcard bins instr_cnt = {INSTR_CNT}; \ - wildcard bins instr_exths = {INSTR_EXTHS}; \ - wildcard bins instr_exthz = {INSTR_EXTHZ}; \ - wildcard bins instr_extbs = {INSTR_EXTBS}; \ - wildcard bins instr_extbz = {INSTR_EXTBZ}; \ - wildcard bins instr_paddnr = {INSTR_PADDNR}; \ - wildcard bins instr_paddunr = {INSTR_PADDUNR}; \ - wildcard bins instr_paddrnr = {INSTR_PADDRNR}; \ - wildcard bins instr_paddurnr = {INSTR_PADDURNR}; \ - wildcard bins instr_psubnr = {INSTR_PSUBNR}; \ - wildcard bins instr_psubunr = {INSTR_PSUBUNR}; \ - wildcard bins instr_psubrnr = {INSTR_PSUBRNR}; \ - wildcard bins instr_psuburnr = {INSTR_PSUBURNR}; \ - wildcard bins instr_pabs = {INSTR_PABS}; \ - wildcard bins instr_pclip = {INSTR_PCLIP}; \ - wildcard bins instr_pclipu = {INSTR_PCLIPU}; \ - wildcard bins instr_pclipr = {INSTR_PCLIPR}; \ - wildcard bins instr_pclipur = {INSTR_PCLIPUR}; \ - wildcard bins instr_pslet = {INSTR_PSLET}; \ - wildcard bins instr_psletu = {INSTR_PSLETU}; \ - wildcard bins instr_pmin = {INSTR_PMIN}; \ - wildcard bins instr_pminu = {INSTR_PMINU}; \ - wildcard bins instr_pmax = {INSTR_PMAX}; \ - wildcard bins instr_pmaxu = {INSTR_PMAXU}; \ - wildcard bins instr_ror = {INSTR_ROR}; \ - wildcard bins instr_pbextr = {INSTR_PBEXTR}; \ - wildcard bins instr_pbextur = {INSTR_PBEXTUR}; \ - wildcard bins instr_pbinsr = {INSTR_PBINSR}; \ - wildcard bins instr_pbclrr = {INSTR_PBCLRR}; \ - wildcard bins instr_pbsetr = {INSTR_PBSETR}; \ - wildcard bins instr_pmac = {INSTR_PMAC}; \ - wildcard bins instr_pmsu = {INSTR_PMSU}; \ - // CUSTOM_2 \ - wildcard bins instr_pbext = {INSTR_PBEXT}; \ - wildcard bins instr_pbextu = {INSTR_PBEXTU}; \ - wildcard bins instr_pbins = {INSTR_PBINS}; \ - wildcard bins instr_pbclr = {INSTR_PBCLR}; \ - wildcard bins instr_pbset = {INSTR_PBSET}; \ - wildcard bins instr_pbrev = {INSTR_PBREV}; \ - wildcard bins instr_paddn = {INSTR_PADDN}; \ - wildcard bins instr_paddun = {INSTR_PADDUN}; \ - wildcard bins instr_paddrn = {INSTR_PADDRN}; \ - wildcard bins instr_paddurn = {INSTR_PADDURN}; \ - wildcard bins instr_psubn = {INSTR_PSUBN}; \ - wildcard bins instr_psubun = {INSTR_PSUBUN}; \ - wildcard bins instr_psubrn = {INSTR_PSUBRN}; \ - wildcard bins instr_psuburn = {INSTR_PSUBURN}; \ - wildcard bins instr_pmulsn = {INSTR_PMULSN}; \ - wildcard bins instr_pmulhhsn = {INSTR_PMULHHSN}; \ - wildcard bins instr_pmulsrn = {INSTR_PMULSRN}; \ - wildcard bins instr_pmulhhsrn = {INSTR_PMULHHSRN}; \ - wildcard bins instr_pmulun = {INSTR_PMULUN}; \ - wildcard bins instr_pmulhhun = {INSTR_PMULHHUN}; \ - wildcard bins instr_pmulurn = {INSTR_PMULURN}; \ - wildcard bins instr_pmulhhurn = {INSTR_PMULHHURN}; \ - wildcard bins instr_pmacsn = {INSTR_PMACSN}; \ - wildcard bins instr_pmachhsn = {INSTR_PMACHHSN}; \ - wildcard bins instr_pmacsrn = {INSTR_PMACSRN}; \ - wildcard bins instr_pmachhsrn = {INSTR_PMACHHSRN}; \ - wildcard bins instr_pmacun = {INSTR_PMACUN}; \ - wildcard bins instr_pmachhun = {INSTR_PMACHHUN}; \ - wildcard bins instr_pmacurn = {INSTR_PMACURN}; \ - wildcard bins instr_pmachhurn = {INSTR_PMACHHURN}; \ - // CUSTOM_3 \ - // SIMD ALU \ - wildcard bins instr_cvaddh = {INSTR_CVADDH}; \ - wildcard bins instr_cvaddsch = {INSTR_CVADDSCH}; \ - wildcard bins instr_cvaddscih = {INSTR_CVADDSCIH}; \ - wildcard bins instr_cvaddb = {INSTR_CVADDB}; \ - wildcard bins instr_cvaddscb = {INSTR_CVADDSCB}; \ - wildcard bins instr_cvaddscib = {INSTR_CVADDSCIB}; \ - wildcard bins instr_cvsubh = {INSTR_CVSUBH}; \ - wildcard bins instr_cvsubsch = {INSTR_CVSUBSCH}; \ - wildcard bins instr_cvsubscih = {INSTR_CVSUBSCIH}; \ - wildcard bins instr_cvsubb = {INSTR_CVSUBB}; \ - wildcard bins instr_cvsubscb = {INSTR_CVSUBSCB}; \ - wildcard bins instr_cvsubscib = {INSTR_CVSUBSCIB}; \ - wildcard bins instr_cvavgh = {INSTR_CVAVGH}; \ - wildcard bins instr_cvavgsch = {INSTR_CVAVGSCH}; \ - wildcard bins instr_cvavgscih = {INSTR_CVAVGSCIH}; \ - wildcard bins instr_cvavgb = {INSTR_CVAVGB}; \ - wildcard bins instr_cvavgscb = {INSTR_CVAVGSCB}; \ - wildcard bins instr_cvavgscib = {INSTR_CVAVGSCIB}; \ - wildcard bins instr_cvavguh = {INSTR_CVAVGUH}; \ - wildcard bins instr_cvavgusch = {INSTR_CVAVGUSCH}; \ - wildcard bins instr_cvavguscih = {INSTR_CVAVGUSCIH}; \ - wildcard bins instr_cvavgub = {INSTR_CVAVGUB}; \ - wildcard bins instr_cvavguscb = {INSTR_CVAVGUSCB}; \ - wildcard bins instr_cvavguscib = {INSTR_CVAVGUSCIB}; \ - wildcard bins instr_cvminh = {INSTR_CVMINH}; \ - wildcard bins instr_cvminsch = {INSTR_CVMINSCH}; \ - wildcard bins instr_cvminscih = {INSTR_CVMINSCIH}; \ - wildcard bins instr_cvminb = {INSTR_CVMINB}; \ - wildcard bins instr_cvminscb = {INSTR_CVMINSCB}; \ - wildcard bins instr_cvminscib = {INSTR_CVMINSCIB}; \ - wildcard bins instr_cvminuh = {INSTR_CVMINUH}; \ - wildcard bins instr_cvminusch = {INSTR_CVMINUSCH}; \ - wildcard bins instr_cvminuscih = {INSTR_CVMINUSCIH}; \ - wildcard bins instr_cvminub = {INSTR_CVMINUB}; \ - wildcard bins instr_cvminuscb = {INSTR_CVMINUSCB}; \ - wildcard bins instr_cvminuscib = {INSTR_CVMINUSCIB}; \ - wildcard bins instr_cvmaxh = {INSTR_CVMAXH}; \ - wildcard bins instr_cvmaxsch = {INSTR_CVMAXSCH}; \ - wildcard bins instr_cvmaxscih = {INSTR_CVMAXSCIH}; \ - wildcard bins instr_cvmaxb = {INSTR_CVMAXB}; \ - wildcard bins instr_cvmaxscb = {INSTR_CVMAXSCB}; \ - wildcard bins instr_cvmaxscib = {INSTR_CVMAXSCIB}; \ - wildcard bins instr_cvmaxuh = {INSTR_CVMAXUH}; \ - wildcard bins instr_cvmaxusch = {INSTR_CVMAXUSCH}; \ - wildcard bins instr_cvmaxuscih = {INSTR_CVMAXUSCIH}; \ - wildcard bins instr_cvmaxub = {INSTR_CVMAXUB}; \ - wildcard bins instr_cvmaxuscb = {INSTR_CVMAXUSCB}; \ - wildcard bins instr_cvmaxuscib = {INSTR_CVMAXUSCIB}; \ - wildcard bins instr_cvsrlh = {INSTR_CVSRLH}; \ - wildcard bins instr_cvsrlsch = {INSTR_CVSRLSCH}; \ - wildcard bins instr_cvsrlscih = {INSTR_CVSRLSCIH}; \ - wildcard bins instr_cvsrlb = {INSTR_CVSRLB}; \ - wildcard bins instr_cvsrlscb = {INSTR_CVSRLSCB}; \ - wildcard bins instr_cvsrlscib = {INSTR_CVSRLSCIB}; \ - wildcard bins instr_cvsrah = {INSTR_CVSRAH}; \ - wildcard bins instr_cvsrasch = {INSTR_CVSRASCH}; \ - wildcard bins instr_cvsrascih = {INSTR_CVSRASCIH}; \ - wildcard bins instr_cvsrab = {INSTR_CVSRAB}; \ - wildcard bins instr_cvsrascb = {INSTR_CVSRASCB}; \ - wildcard bins instr_cvsrascib = {INSTR_CVSRASCIB}; \ - wildcard bins instr_cvsllh = {INSTR_CVSLLH}; \ - wildcard bins instr_cvsllsch = {INSTR_CVSLLSCH}; \ - wildcard bins instr_cvsllscih = {INSTR_CVSLLSCIH}; \ - wildcard bins instr_cvsllb = {INSTR_CVSLLB}; \ - wildcard bins instr_cvsllscb = {INSTR_CVSLLSCB}; \ - wildcard bins instr_cvsllscib = {INSTR_CVSLLSCIB}; \ - wildcard bins instr_cvorh = {INSTR_CVORH}; \ - wildcard bins instr_cvorsch = {INSTR_CVORSCH}; \ - wildcard bins instr_cvorscih = {INSTR_CVORSCIH}; \ - wildcard bins instr_cvorb = {INSTR_CVORB}; \ - wildcard bins instr_cvorscb = {INSTR_CVORSCB}; \ - wildcard bins instr_cvorscib = {INSTR_CVORSCIB}; \ - wildcard bins instr_cvxorh = {INSTR_CVXORH}; \ - wildcard bins instr_cvxorsch = {INSTR_CVXORSCH}; \ - wildcard bins instr_cvxorscih = {INSTR_CVXORSCIH}; \ - wildcard bins instr_cvxorb = {INSTR_CVXORB}; \ - wildcard bins instr_cvxorscb = {INSTR_CVXORSCB}; \ - wildcard bins instr_cvxorscib = {INSTR_CVXORSCIB}; \ - wildcard bins instr_cvandh = {INSTR_CVANDH}; \ - wildcard bins instr_cvandsch = {INSTR_CVANDSCH}; \ - wildcard bins instr_cvandscih = {INSTR_CVANDSCIH}; \ - wildcard bins instr_cvandb = {INSTR_CVANDB}; \ - wildcard bins instr_cvandscb = {INSTR_CVANDSCB}; \ - wildcard bins instr_cvandscib = {INSTR_CVANDSCIB}; \ - wildcard bins instr_cvabsh = {INSTR_CVABSH}; \ - wildcard bins instr_cvabsb = {INSTR_CVABSB}; \ - wildcard bins instr_cvextracth = {INSTR_CVEXTRACTH}; \ - wildcard bins instr_cvextractb = {INSTR_CVEXTRACTB}; \ - wildcard bins instr_cvextractuh = {INSTR_CVEXTRACTUH}; \ - wildcard bins instr_cvextractub = {INSTR_CVEXTRACTUB}; \ - wildcard bins instr_cvinserth = {INSTR_CVINSERTH}; \ - wildcard bins instr_cvinsertb = {INSTR_CVINSERTB}; \ - wildcard bins instr_cvdotuph = {INSTR_CVDOTUPH}; \ - wildcard bins instr_cvdotupsch = {INSTR_CVDOTUPSCH}; \ - wildcard bins instr_cvdotupscih = {INSTR_CVDOTUPSCIH}; \ - wildcard bins instr_cvdotupb = {INSTR_CVDOTUPB}; \ - wildcard bins instr_cvdotupscb = {INSTR_CVDOTUPSCB}; \ - wildcard bins instr_cvdotupscib = {INSTR_CVDOTUPSCIB}; \ - wildcard bins instr_cvdotusph = {INSTR_CVDOTUSPH}; \ - wildcard bins instr_cvdotuspsch = {INSTR_CVDOTUSPSCH}; \ - wildcard bins instr_cvdotuspscih = {INSTR_CVDOTUSPSCIH}; \ - wildcard bins instr_cvdotuspb = {INSTR_CVDOTUSPB}; \ - wildcard bins instr_cvdotuspscb = {INSTR_CVDOTUSPSCB}; \ - wildcard bins instr_cvdotuspscib = {INSTR_CVDOTUSPSCIB}; \ - wildcard bins instr_cvdotsph = {INSTR_CVDOTSPH}; \ - wildcard bins instr_cvdotspsch = {INSTR_CVDOTSPSCH}; \ - wildcard bins instr_cvdotspscih = {INSTR_CVDOTSPSCIH}; \ - wildcard bins instr_cvdotspb = {INSTR_CVDOTSPB}; \ - wildcard bins instr_cvdotspscb = {INSTR_CVDOTSPSCB}; \ - wildcard bins instr_cvdotspscib = {INSTR_CVDOTSPSCIB}; \ - wildcard bins instr_cvsdotuph = {INSTR_CVSDOTUPH}; \ - wildcard bins instr_cvsdotupsch = {INSTR_CVSDOTUPSCH}; \ - wildcard bins instr_cvsdotupscih = {INSTR_CVSDOTUPSCIH}; \ - wildcard bins instr_cvsdotupb = {INSTR_CVSDOTUPB}; \ - wildcard bins instr_cvsdotupscb = {INSTR_CVSDOTUPSCB}; \ - wildcard bins instr_cvsdotupscib = {INSTR_CVSDOTUPSCIB}; \ - wildcard bins instr_cvsdotusph = {INSTR_CVSDOTUSPH}; \ - wildcard bins instr_cvsdotuspsch = {INSTR_CVSDOTUSPSCH}; \ - wildcard bins instr_cvsdotuspscih = {INSTR_CVSDOTUSPSCIH}; \ - wildcard bins instr_cvsdotuspb = {INSTR_CVSDOTUSPB}; \ - wildcard bins instr_cvsdotuspscb = {INSTR_CVSDOTUSPSCB}; \ - wildcard bins instr_cvsdotuspscib = {INSTR_CVSDOTUSPSCIB}; \ - wildcard bins instr_cvsdotsph = {INSTR_CVSDOTSPH}; \ - wildcard bins instr_cvsdotspsch = {INSTR_CVSDOTSPSCH}; \ - wildcard bins instr_cvsdotspscih = {INSTR_CVSDOTSPSCIH}; \ - wildcard bins instr_cvsdotspb = {INSTR_CVSDOTSPB}; \ - wildcard bins instr_cvsdotspscb = {INSTR_CVSDOTSPSCB}; \ - wildcard bins instr_cvsdotspscib = {INSTR_CVSDOTSPSCIB}; \ - wildcard bins instr_cvshuffleh = {INSTR_CVSHUFFLEH}; \ - wildcard bins instr_cvshufflescih = {INSTR_CVSHUFFLESCIH}; \ - wildcard bins instr_cvshuffleb = {INSTR_CVSHUFFLEB}; \ - wildcard bins instr_cvshufflel0scib = {INSTR_CVSHUFFLEL0SCIB}; \ - wildcard bins instr_cvshufflel1scib = {INSTR_CVSHUFFLEL1SCIB}; \ - wildcard bins instr_cvshufflel2scib = {INSTR_CVSHUFFLEL2SCIB}; \ - wildcard bins instr_cvshufflel3scib = {INSTR_CVSHUFFLEL3SCIB}; \ - wildcard bins instr_cvshuffle2h = {INSTR_CVSHUFFLE2H}; \ - wildcard bins instr_cvshuffle2b = {INSTR_CVSHUFFLE2B}; \ - wildcard bins instr_cvpack = {INSTR_CVPACK}; \ - wildcard bins instr_cvpackh = {INSTR_CVPACKH}; \ - wildcard bins instr_cvpackhib = {INSTR_CVPACKHIB}; \ - wildcard bins instr_cvpacklob = {INSTR_CVPACKLOB}; \ - // SIMD COMPARISON \ - wildcard bins instr_cvcmpeqh = {INSTR_CVCMPEQH}; \ - wildcard bins instr_cvcmpeqsch = {INSTR_CVCMPEQSCH}; \ - wildcard bins instr_cvcmpeqscih = {INSTR_CVCMPEQSCIH}; \ - wildcard bins instr_cvcmpeqb = {INSTR_CVCMPEQB}; \ - wildcard bins instr_cvcmpeqscb = {INSTR_CVCMPEQSCB}; \ - wildcard bins instr_cvcmpeqscib = {INSTR_CVCMPEQSCIB}; \ - wildcard bins instr_cvcmpneh = {INSTR_CVCMPNEH}; \ - wildcard bins instr_cvcmpnesch = {INSTR_CVCMPNESCH}; \ - wildcard bins instr_cvcmpnescih = {INSTR_CVCMPNESCIH}; \ - wildcard bins instr_cvcmpneb = {INSTR_CVCMPNEB}; \ - wildcard bins instr_cvcmpnescb = {INSTR_CVCMPNESCB}; \ - wildcard bins instr_cvcmpnescib = {INSTR_CVCMPNESCIB}; \ - wildcard bins instr_cvcmpgth = {INSTR_CVCMPGTH}; \ - wildcard bins instr_cvcmpgtsch = {INSTR_CVCMPGTSCH}; \ - wildcard bins instr_cvcmpgtscih = {INSTR_CVCMPGTSCIH}; \ - wildcard bins instr_cvcmpgtb = {INSTR_CVCMPGTB}; \ - wildcard bins instr_cvcmpgtscb = {INSTR_CVCMPGTSCB}; \ - wildcard bins instr_cvcmpgtscib = {INSTR_CVCMPGTSCIB}; \ - wildcard bins instr_cvcmpgeh = {INSTR_CVCMPGEH}; \ - wildcard bins instr_cvcmpgesch = {INSTR_CVCMPGESCH}; \ - wildcard bins instr_cvcmpgescih = {INSTR_CVCMPGESCIH}; \ - wildcard bins instr_cvcmpgeb = {INSTR_CVCMPGEB}; \ - wildcard bins instr_cvcmpgescb = {INSTR_CVCMPGESCB}; \ - wildcard bins instr_cvcmpgescib = {INSTR_CVCMPGESCIB}; \ - wildcard bins instr_cvcmplth = {INSTR_CVCMPLTH}; \ - wildcard bins instr_cvcmpltsch = {INSTR_CVCMPLTSCH}; \ - wildcard bins instr_cvcmpltscih = {INSTR_CVCMPLTSCIH}; \ - wildcard bins instr_cvcmpltb = {INSTR_CVCMPLTB}; \ - wildcard bins instr_cvcmpltscb = {INSTR_CVCMPLTSCB}; \ - wildcard bins instr_cvcmpltscib = {INSTR_CVCMPLTSCIB}; \ - wildcard bins instr_cvcmpleh = {INSTR_CVCMPLEH}; \ - wildcard bins instr_cvcmplesch = {INSTR_CVCMPLESCH}; \ - wildcard bins instr_cvcmplescih = {INSTR_CVCMPLESCIH}; \ - wildcard bins instr_cvcmpleb = {INSTR_CVCMPLEB}; \ - wildcard bins instr_cvcmplescb = {INSTR_CVCMPLESCB}; \ - wildcard bins instr_cvcmplescib = {INSTR_CVCMPLESCIB}; \ - wildcard bins instr_cvcmpgtuh = {INSTR_CVCMPGTUH}; \ - wildcard bins instr_cvcmpgtusch = {INSTR_CVCMPGTUSCH}; \ - wildcard bins instr_cvcmpgtuscih = {INSTR_CVCMPGTUSCIH}; \ - wildcard bins instr_cvcmpgtub = {INSTR_CVCMPGTUB}; \ - wildcard bins instr_cvcmpgtuscb = {INSTR_CVCMPGTUSCB}; \ - wildcard bins instr_cvcmpgtuscib = {INSTR_CVCMPGTUSCIB}; \ - wildcard bins instr_cvcmpgeuh = {INSTR_CVCMPGEUH}; \ - wildcard bins instr_cvcmpgeusch = {INSTR_CVCMPGEUSCH}; \ - wildcard bins instr_cvcmpgeuscih = {INSTR_CVCMPGEUSCIH}; \ - wildcard bins instr_cvcmpgeub = {INSTR_CVCMPGEUB}; \ - wildcard bins instr_cvcmpgeuscb = {INSTR_CVCMPGEUSCB}; \ - wildcard bins instr_cvcmpgeuscib = {INSTR_CVCMPGEUSCIB}; \ - wildcard bins instr_cvcmpltuh = {INSTR_CVCMPLTUH}; \ - wildcard bins instr_cvcmpltusch = {INSTR_CVCMPLTUSCH}; \ - wildcard bins instr_cvcmpltuscih = {INSTR_CVCMPLTUSCIH}; \ - wildcard bins instr_cvcmpltub = {INSTR_CVCMPLTUB}; \ - wildcard bins instr_cvcmpltuscb = {INSTR_CVCMPLTUSCB}; \ - wildcard bins instr_cvcmpltuscib = {INSTR_CVCMPLTUSCIB}; \ - wildcard bins instr_cvcmpleuh = {INSTR_CVCMPLEUH}; \ - wildcard bins instr_cvcmpleusch = {INSTR_CVCMPLEUSCH}; \ - wildcard bins instr_cvcmpleuscih = {INSTR_CVCMPLEUSCIH}; \ - wildcard bins instr_cvcmpleub = {INSTR_CVCMPLEUB}; \ - wildcard bins instr_cvcmpleuscb = {INSTR_CVCMPLEUSCB}; \ - wildcard bins instr_cvcmpleuscib = {INSTR_CVCMPLEUSCIB}; \ - // SIMD CPLX \ - wildcard bins instr_cvcplxmulr = {INSTR_CVCPLXMULR}; \ - wildcard bins instr_cvcplxmulrdiv2 = {INSTR_CVCPLXMULRDIV2}; \ - wildcard bins instr_cvcplxmulrdiv4 = {INSTR_CVCPLXMULRDIV4}; \ - wildcard bins instr_cvcplxmulrdiv8 = {INSTR_CVCPLXMULRDIV8}; \ - wildcard bins instr_cvcplxmuli = {INSTR_CVCPLXMULI}; \ - wildcard bins instr_cvcplxmulidiv2 = {INSTR_CVCPLXMULIDIV2}; \ - wildcard bins instr_cvcplxmulidiv4 = {INSTR_CVCPLXMULIDIV4}; \ - wildcard bins instr_cvcplxmulidiv8 = {INSTR_CVCPLXMULIDIV8}; \ - wildcard bins instr_cvcplxconj = {INSTR_CVCPLXCONJ}; \ - wildcard bins instr_cvsubrotmj = {INSTR_CVSUBROTMJ}; \ - wildcard bins instr_cvsubrotmjdiv2 = {INSTR_CVSUBROTMJDIV2}; \ - wildcard bins instr_cvsubrotmjdiv4 = {INSTR_CVSUBROTMJDIV4}; \ - wildcard bins instr_cvsubrotmjdiv8 = {INSTR_CVSUBROTMJDIV8}; \ - wildcard bins instr_cvaddiv2 = {INSTR_CVADDIV2}; \ - wildcard bins instr_cvaddiv4 = {INSTR_CVADDIV4}; \ - wildcard bins instr_cvaddiv8 = {INSTR_CVADDIV8}; \ - wildcard bins instr_cvsubiv2 = {INSTR_CVSUBIV2}; \ - wildcard bins instr_cvsubiv4 = {INSTR_CVSUBIV4}; \ - wildcard bins instr_cvsubiv8 = {INSTR_CVSUBIV8}; \ - // Load-Store (RV32F) \ - wildcard bins instr_flw = {INSTR_FLW}; \ - wildcard bins instr_fsw = {INSTR_FSW}; \ + `LOAD_STORE_INSTR_BINS \ + // RV32X \ + `RV32X_PULP_INSTR_BINS \ // user-defined instructions \ wildcard bins instr_illegal_exception = {{INSN_ILLEGAL}}; \ - wildcard bins instr_ebreakm = {{INSN_EBREAKM}}; \ + wildcard bins instr_ebreakm = {{INSN_EBREAKM}}; \ // Others \ - illegal_bins other_instr = default; \ + illegal_bins other_instr = default; \ } \ ccp_hwloop_type_setup_insn_list : cross cp_hwloop_type, cp_hwloop_setup, cp_insn_list_in_hwloop; \ ccp_hwloop_type_irq_loc : cross cp_hwloop_type, cp_hwloop_loc, cp_hwloop_irq; \ @@ -775,7 +353,7 @@ class uvme_rv32x_hwloop_covg # ( irq_vect_main[``LOOP_IDX``].push_back(prev_irq_onehot_priority); \ end \ DBG_HALTREQ : begin \ - is_dbg_mode = 1; hwloop_stat_main.dbg_haltreq_cnt[``LOOP_IDX``]++; \ + hwloop_stat_main.dbg_haltreq_cnt[``LOOP_IDX``]++; \ if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPSTART); \ else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPSTART_P4); \ else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_LPEND); \ @@ -783,7 +361,7 @@ class uvme_rv32x_hwloop_covg # ( else hwloop_evt_loc_main[``LOOP_IDX``][DBG_HALTREQ].push_back(LOC_OTHERS); \ end \ DBG_TRIG : begin \ - is_dbg_mode = 1; hwloop_stat_main.dbg_trigger_cnt[``LOOP_IDX``]++; \ + hwloop_stat_main.dbg_trigger_cnt[``LOOP_IDX``]++; \ if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPSTART); \ else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPSTART_P4); \ else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_LPEND); \ @@ -791,7 +369,7 @@ class uvme_rv32x_hwloop_covg # ( else hwloop_evt_loc_main[``LOOP_IDX``][DBG_TRIG].push_back(LOC_OTHERS); \ end \ DBG_STEP : begin \ - is_dbg_mode = 1; hwloop_stat_main.dbg_step_cnt[``LOOP_IDX``]++; \ + hwloop_stat_main.dbg_step_cnt[``LOOP_IDX``]++; \ if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPSTART); \ else if (`CHECK_PC_EQUAL_LPSTART(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 1, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPSTART_P4); \ else if ( `CHECK_PC_EQUAL_LPEND(hwloop_stat_main.hwloop_csr, ``LOOP_IDX``, 0, prev_pc_rdata_main)) hwloop_evt_loc_main[``LOOP_IDX``][DBG_STEP].push_back(LOC_LPEND); \ @@ -1183,15 +761,15 @@ class uvme_rv32x_hwloop_covg # ( endfunction : check_exception_entry function void check_ebreakm_entry(int lp_idx); - if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == INSTR_EBREAK) begin + if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm && cv32e40p_rvvi_vif.insn == TB_INSTR_EBREAK) begin if (lp_idx) begin `IF_CURRENT_IS_MAIN_HWLOOP(1, DBG_EBREAKM) end else begin `IF_CURRENT_IS_MAIN_HWLOOP(0, DBG_EBREAKM) end end endfunction : check_ebreakm_entry function void check_exception_exit(); - if (cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == INSTR_MRET) begin - is_ebreak = 0; is_ecall = 0; is_illegal = 0; + if (cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == TB_INSTR_MRET) begin + is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Exit"), UVM_DEBUG); end endfunction : check_exception_exit @@ -1220,20 +798,25 @@ class uvme_rv32x_hwloop_covg # ( cv32e40p_rvvi_vif.pc_rdata == prev_pc_rdata_main || // set excep when not garbage data during trap (main) cv32e40p_rvvi_vif.pc_rdata == prev_pc_rdata_sub // set excep when not garbage data during trap (sub) - todo: revise is needed when sub is fully implement ) begin + is_trap = 0; wait (!cv32e40p_rvvi_vif.trap); // bypass if garbage data exist end else if (cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0 && !pending_irq && !is_dbg_mode) begin // set excep flag only if no pending irq and not in dbg mode + is_trap = 1; case (cv32e40p_rvvi_vif.insn) - INSTR_EBREAK, INSTR_CBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin + TB_INSTR_EBREAK, INSTR_CBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin @(posedge cv32e40p_rvvi_vif.clk); continue; end else begin is_ebreak = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to EBREAK"), UVM_DEBUG); end - INSTR_ECALL : begin is_ecall = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to ECALL"), UVM_DEBUG); end + TB_INSTR_ECALL : begin is_ecall = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to ECALL"), UVM_DEBUG); end default : begin is_illegal = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to ILLEGAL"), UVM_DEBUG); end endcase wait (!(is_ebreak | is_ecall | is_illegal)); end - else wait (!cv32e40p_rvvi_vif.trap); // bypass if pending irq exist + else begin + is_trap = 0; + wait (!cv32e40p_rvvi_vif.trap); + end // bypass if pending irq exist end // EXCEPTION_HANDLING forever begin : SET_PENDING_IRQ_FLAG @@ -1258,19 +841,20 @@ class uvme_rv32x_hwloop_covg # ( forever begin : IRQ_EXIT wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]); @(posedge cv32e40p_rvvi_vif.clk); - if (is_irq && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == INSTR_MRET) begin + if (is_irq && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == TB_INSTR_MRET) begin `uvm_info(_header, $sformatf("DEBUG - IRQ Exit"), UVM_DEBUG); is_irq = 0; end end // IRQ_EXIT forever begin : DBG_ENTRY - wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]); + // wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]); wait (!is_dbg_mode); wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.pc_rdata == cv32e40p_rvvi_vif.dm_halt_addr && dcsr_cause_t'(cv32e40p_rvvi_vif.csr_dcsr_cause) inside {EBREAKM, TRIGGER, HALTREQ, STEP}) begin dcsr_cause = dcsr_cause_t'(cv32e40p_rvvi_vif.csr_dcsr_cause); + is_dbg_mode = 1; unique case(dcsr_cause) - EBREAKM : begin is_dbg_mode = 1; end + EBREAKM : begin /* do nothing */ end TRIGGER : begin if (hwloop_stat_main.execute_instr_in_hwloop[1] && !(in_nested_loop0|in_nested_loop0_d1)) begin `IF_CURRENT_IS_MAIN_HWLOOP(1, DBG_TRIG) end else begin `IF_CURRENT_IS_MAIN_HWLOOP(0, DBG_TRIG) end @@ -1288,9 +872,9 @@ class uvme_rv32x_hwloop_covg # ( end end // DBG_ENTRY forever begin : DBG_EXIT - wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]); + // wait (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]); wait (is_dbg_mode); - wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == INSTR_DRET) begin + wait (cv32e40p_rvvi_vif.clk && cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == TB_INSTR_DRET) begin @(posedge cv32e40p_rvvi_vif.clk) ; @(negedge cv32e40p_rvvi_vif.clk); `uvm_info(_header, $sformatf("DEBUG - Debug Mode Exit"), UVM_DEBUG); is_dbg_mode = 0; is_ebreakm = 0; @@ -1304,7 +888,22 @@ class uvme_rv32x_hwloop_covg # ( if (cv32e40p_rvvi_vif.valid) begin : VALID_DETECTED if (enter_hwloop_sub) begin - if (pc_is_mtvec_addr() && !is_mcause_irq()) begin : EXCEPTION_ENTRY + if (is_trap && is_dbg_mode) begin : TRAP_DUETO_DBG_ENTRY + is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; + for (int j=0; j= 0 && !temp_in_nested_loop0) begin + logic [31:0] discarded_insn; + if (!done_insn_list_capture_main[j]) begin + discarded_insn = insn_list_in_hwloop_main[j].pop_back(); + `uvm_info(_header, $sformatf("DEBUG - HWLOOP_NB_%0d Discarded insn %8h due to Trap triggered by Debug Entery", j, discarded_insn), UVM_DEBUG); + assert (discarded_insn inside {TB_INSTR_ECALL, TB_INSTR_EBREAK, INSN_ILLEGAL}); + end + `uvm_info(_header, $sformatf("DEBUG - HWLOOP_NB_%0d Trap due to Debug Entry detected", j), UVM_DEBUG); + end + end + end // TRAP_DUETO_DBG_ENTRY + else if (pc_is_mtvec_addr() && !is_mcause_irq()) begin : EXCEPTION_ENTRY for (int i=0; i Date: Tue, 2 Jan 2024 12:35:43 +0800 Subject: [PATCH 63/97] Fix regress due to previous fixes Signed-off-by: bsm --- cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index e0ebb32c59..3fe0229718 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -114,8 +114,10 @@ class uvme_rv32x_hwloop_covg # ( bit is_ebreak = 0, is_ebreakm = 0, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0, is_mc_insn = 0; bit is_trap = 0; // trap any period that is redundant due to handling entry which causes data flush bit enter_hwloop_sub = 0; + int enter_hwloop_sub_cnt = 0; bit pending_irq = 0; logic [31:0] prev_irq_onehot_priority = 0, prev_irq_onehot_priority_always = 0; + bit prev_irq_onehot_priority_is_0 = 0; dcsr_cause_t dcsr_cause; exception_code_t exception_code; @@ -801,7 +803,7 @@ class uvme_rv32x_hwloop_covg # ( is_trap = 0; wait (!cv32e40p_rvvi_vif.trap); // bypass if garbage data exist end - else if (cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0 && !pending_irq && !is_dbg_mode) begin // set excep flag only if no pending irq and not in dbg mode + else if (((cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0) || prev_irq_onehot_priority_is_0) && !pending_irq && !is_dbg_mode && !is_irq) begin // set excep flag only if no pending irq and not in dbg mode is_trap = 1; case (cv32e40p_rvvi_vif.insn) TB_INSTR_EBREAK, INSTR_CBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin @@ -823,9 +825,10 @@ class uvme_rv32x_hwloop_covg # ( @(negedge cv32e40p_rvvi_vif.clk); if (cv32e40p_rvvi_vif.irq_onehot_priority !== prev_irq_onehot_priority) begin pending_irq = 0; + prev_irq_onehot_priority_is_0 = 0; if (enter_hwloop_sub) update_prev_irq_onehot_priority(); // within excp period else if ((hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1])) begin // within main loop - if (prev_irq_onehot_priority === 0) begin update_prev_irq_onehot_priority(); end // new pending + if (prev_irq_onehot_priority === 0) begin prev_irq_onehot_priority_is_0 = 1; update_prev_irq_onehot_priority(); end // new pending else begin // last irq or any pending irq(s) if (!is_irq) pending_irq = 1; else begin @@ -888,7 +891,8 @@ class uvme_rv32x_hwloop_covg # ( if (cv32e40p_rvvi_vif.valid) begin : VALID_DETECTED if (enter_hwloop_sub) begin - if (is_trap && is_dbg_mode) begin : TRAP_DUETO_DBG_ENTRY + enter_hwloop_sub_cnt++; + if (is_trap && is_dbg_mode && enter_hwloop_sub_cnt == 1) begin : TRAP_DUETO_DBG_ENTRY // trap cycle and debug are b2b is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; for (int j=0; j Date: Wed, 3 Jan 2024 14:04:31 +0800 Subject: [PATCH 64/97] Add illegal Instr contraint for RV32FC Signed-off-by: dd-baoshan --- cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv b/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv index dcad5642e1..5a09bb73c2 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_illegal_instr.sv @@ -35,6 +35,14 @@ class cv32e40p_illegal_instr extends riscv_illegal_instr; instr_bin[31:20] != 'h7AA; // SCONTEXT } + constraint reserved_when_rv32FC_c { + if (riscv_instr_pkg::RV32FC inside {riscv_instr_pkg::supported_isa}) { + if (exception == kReservedCompressedInstr) { + reserved_c != kReservedLdsp; + } + } + } + `uvm_object_utils(cv32e40p_illegal_instr); function new(string name=""); From 6c6851fc77ca0c97ebbb592dc61c2483761e160f Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 9 Jan 2024 15:23:28 +0800 Subject: [PATCH 65/97] Enable define for some extended Imperas ISA coverpoints Signed-off-by: dd-baoshan --- .../tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh index d6e657ee77..ce76581445 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh @@ -7,7 +7,7 @@ `define COVER_BASE_RV32I `define COVER_LEVEL_COMPL_BAS //`define COVER_LEVEL_COMPL_EXT - //`define COVER_LEVEL_DV_UP_BAS + `define COVER_LEVEL_DV_UP_BAS //`define COVER_LEVEL_DV_UP_EXT //`define COVER_LEVEL_DV_PR_BAS //`define COVER_LEVEL_DV_PR_EXT From 477c3c1736d136011fbff93697c92bc658565276 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 9 Jan 2024 15:24:10 +0800 Subject: [PATCH 66/97] modify msg for rerun command Signed-off-by: dd-baoshan --- bin/templates/regress_rmdb.j2 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/templates/regress_rmdb.j2 b/bin/templates/regress_rmdb.j2 index 4aba954d56..a1cb83e574 100644 --- a/bin/templates/regress_rmdb.j2 +++ b/bin/templates/regress_rmdb.j2 @@ -206,7 +206,7 @@ {% endif %} - echo " TEST RUNCMD: (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} COMP=0 CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%)" + echo " TEST RUNCMD: (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%)" echo " logfile: (%log_file%)" echo " RTL repo: CV_CORE_REPO : ${CV_CORE_REPO}" echo " CV_CORE_BRANCH: ${CV_CORE_BRANCH}" From a05e0158cd32568e3b6ba079b4310bd9aaec78d9 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 9 Jan 2024 15:28:11 +0800 Subject: [PATCH 67/97] Fix corner case issues found in random seed Signed-off-by: dd-baoshan --- cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv | 1 + cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 2 ++ 2 files changed, 3 insertions(+) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index ff02f09941..0289ef12e4 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -1084,6 +1084,7 @@ class cv32e40p_constraint_mc_fp_instr_stream extends cv32e40p_float_zfinx_base_i use_fp_only_for_directed_instr = 1; en_clr_fflags_af_instr = 0; use_same_instr_per_stream = 1; + include_load_store_base_sp = 1; // store sp is randomly used here endfunction: pre_randomize virtual function void act_post_directed_instr( diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 3fe0229718..240028aaac 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -894,6 +894,7 @@ class uvme_rv32x_hwloop_covg # ( enter_hwloop_sub_cnt++; if (is_trap && is_dbg_mode && enter_hwloop_sub_cnt == 1) begin : TRAP_DUETO_DBG_ENTRY // trap cycle and debug are b2b is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; + prev_pc_rdata_main = prev_pc_rdata_main-4; for (int j=0; j= 0 && !temp_in_nested_loop0) begin @@ -923,6 +924,7 @@ class uvme_rv32x_hwloop_covg # ( else if (pc_is_mtvec_addr() && is_mcause_irq()) begin : IRQ_ENTRY if (hwloop_stat_main.execute_instr_in_hwloop[0] | hwloop_stat_main.execute_instr_in_hwloop[1]) begin is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; + prev_pc_rdata_main = prev_pc_rdata_main-4; pending_irq = 0; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry is replaced with IRQ Entry (higher priority)"), UVM_DEBUG); `IF_CURRENT_IS_MAIN_HWLOOP(0, IS_IRQ) From 05d8227519d3ed791246c3290280e12639a2c9e3 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 9 Jan 2024 15:32:22 +0800 Subject: [PATCH 68/97] Add random fpu streams with interrupt and debug events Signed-off-by: dd-baoshan --- .../cv32e40pv2_interrupt_debug_short.yaml | 59 +++++++++++++++++++ .../corev_rand_fp_instr_debug/corev-dv.yaml | 38 ++++++++++++ .../corev_rand_fp_instr_debug/test.yaml | 10 ++++ 3 files changed, 107 insertions(+) create mode 100644 cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml create mode 100644 cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 49b0e89b1c..77cc74f1a2 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -149,6 +149,65 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en +# Add corev_rand_fp_instr_debug similar to corev_rand_pulp_instr_debug/test with f/zfinx insn included - START + + corev_rand_fp_instr_debug_test_with_int_and_debug: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,gen_rand_debug_req + skip_sim: pulp + + corev_rand_fp_instr_debug_test_with_int_and_debug_trigger: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,gen_rand_debug_req + skip_sim: pulp + + corev_rand_fp_instr_debug_test_with_int_and_debug_single_step: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt and debug trigger + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_single_step_en,gen_rand_debug_req + skip_sim: pulp + +# note: current fp streams excluding ebreak insn +# corev_rand_fp_instr_debug_test_with_int_and_debug_ebreak: +# testname: corev_rand_fp_instr_debug +# description: pulp instr random test with random interrupt and debug ebreak +# build: uvmt_cv32e40p +# dir: cv32e40p/sim/uvmt +# cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" +# test_cfg: gen_rand_int,debug_ebreak,gen_rand_debug_req +# skip_sim: pulp +# +# corev_rand_fp_instr_debug_test_with_int_debug_trigger_and_ebreak: +# testname: corev_rand_fp_instr_debug +# description: pulp instr random test with random interrupt, debug trigger and debug ebreak +# build: uvmt_cv32e40p +# dir: cv32e40p/sim/uvmt +# cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" +# test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak,gen_rand_debug_req +# skip_sim: pulp + + corev_rand_fp_instr_debug_test_with_int_debug_trigger_and_single_step: + testname: corev_rand_fp_instr_debug + description: fp instr random test with random interrupt, debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en,gen_rand_debug_req + skip_sim: pulp + +# Add corev_rand_fp_instr_debug similar to corev_rand_pulp_instr_debug with f/zfinx insn included - END + corev_rand_pulp_hwloop_debug: build: uvmt_cv32e40p description: hwloop debug random test diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml new file mode 100644 index 0000000000..b2aa4a8f49 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml @@ -0,0 +1,38 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for corev-dv test generator +# corev-dv generator test +name: corev_rand_fp_instr_debug +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated random pulp instr test +plusargs: > + +instr_cnt=1000 + +num_of_sub_program=0 + +insert_rand_directed_instr_stream=1 + +test_rand_directed_instr_stream_num=8 + +directed_instr_0=cv32e40p_constraint_mc_fp_instr_stream,4 + +directed_instr_1=cv32e40p_fp_op_fwd_instr_stream,4 + +directed_instr_2=cv32e40p_fp_op_fwd_instr_w_loadstore_stream,4 + +rand_directed_instr_0=riscv_load_store_rand_instr_stream,1 + +rand_directed_instr_1=riscv_load_store_hazard_instr_stream,1 + +rand_directed_instr_2=riscv_multi_page_load_store_instr_stream,1 + +rand_directed_instr_3=riscv_jal_instr,1 + +rand_directed_instr_4=riscv_hazard_instr_stream,1 + +rand_directed_instr_5=cv32e40p_xpulp_simd_stream_test,1 + +rand_directed_instr_6=cv32e40p_xpulp_mac_stream_test,1 + +rand_directed_instr_7=riscv_int_numeric_corner_stream,1 + +no_fence=0 + +hint_instr_ratio=2 + +no_data_page=0 + +randomize_csr=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +no_wfi=1 + +no_dret=1 + +fix_sp=1 + +enable_misaligned_instr=1 + +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml new file mode 100644 index 0000000000..331c558b71 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml @@ -0,0 +1,10 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for random pulp instr test +name: corev_rand_fp_instr_debug +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Random debug in xpulp instruction stream +plusargs: > + # +gen_reduced_rand_dbg_req From e81e50869e0174fbaea65e47af9c6271b8b38fd3 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Wed, 10 Jan 2024 14:30:58 +0800 Subject: [PATCH 69/97] Disable trace logs generations in regression using vrun Signed-off-by: dd-baoshan --- bin/templates/regress_rmdb.j2 | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/bin/templates/regress_rmdb.j2 b/bin/templates/regress_rmdb.j2 index a1cb83e574..d4ee9ac580 100644 --- a/bin/templates/regress_rmdb.j2 +++ b/bin/templates/regress_rmdb.j2 @@ -141,6 +141,7 @@ + {% for build in r.get_builds() %} @@ -158,8 +159,8 @@ {% endfor %} - echo "BUILD RUNCMD: {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}}" - cd {{build.abs_dir}} && {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}} + echo "BUILD RUNCMD: {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} ENABLE_TRACE_LOG=NO USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}}" + cd {{build.abs_dir}} && {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} ENABLE_TRACE_LOG=NO USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}} {% endfor %} @@ -199,6 +200,7 @@ {% endfor %} + {% if lsf != None %} From 2f5ac427a904292b40068bf6f34129352d0c2e08 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Wed, 10 Jan 2024 20:57:12 +0800 Subject: [PATCH 70/97] Modify code coverage collection types Signed-off-by: dd-baoshan --- mk/uvmt/vsim.mk | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk index fb11d631fe..2688b6f71f 100644 --- a/mk/uvmt/vsim.mk +++ b/mk/uvmt/vsim.mk @@ -42,10 +42,11 @@ VSIM_COV_ONLY_PASS_TEST ?= YES VSIM_LOCAL_MODELSIMINI ?= YES VOPT_CODE_COV_DUT_ONLY ?= YES VSIM_USER_FLAGS ?= +# note: t or toggle is excluded in cv32e40p_v2 ifeq ($(call IS_YES,$(VOPT_CODE_COV_DUT_ONLY)),YES) -VOPT_COV ?= +cover=bcsetf+$(RTLSRC_VLOG_CORE_TOP). +VOPT_COV ?= +cover=bcsef+$(RTLSRC_VLOG_CORE_TOP). else -VOPT_COV ?= +cover=setf+$(RTLSRC_VLOG_TB_TOP). +VOPT_COV ?= +cover=sef+$(RTLSRC_VLOG_TB_TOP). endif VSIM_COV ?= -coverage +uvm_set_config_int=uvm_test_top,cov_model_enabled,1 VOPT_WAVES_ADV_DEBUG ?= -designfile design.bin From 069dc3106fcd9bbade280077fb5cbd3b20e97fc9 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Wed, 10 Jan 2024 21:02:35 +0800 Subject: [PATCH 71/97] Use reduced debug req in these tests Signed-off-by: dd-baoshan --- .../regress/cv32e40pv2_interrupt_debug_short.yaml | 12 ++++++------ .../corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml | 8 ++++---- .../corev-dv/corev_rand_fp_instr_debug/test.yaml | 4 ++-- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 77cc74f1a2..442b86ae46 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -157,7 +157,7 @@ tests: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - test_cfg: gen_rand_int,gen_rand_debug_req + test_cfg: gen_rand_int skip_sim: pulp corev_rand_fp_instr_debug_test_with_int_and_debug_trigger: @@ -166,7 +166,7 @@ tests: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - test_cfg: gen_rand_int,debug_trigger_basic,gen_rand_debug_req + test_cfg: gen_rand_int,debug_trigger_basic skip_sim: pulp corev_rand_fp_instr_debug_test_with_int_and_debug_single_step: @@ -175,7 +175,7 @@ tests: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - test_cfg: gen_rand_int,debug_single_step_en,gen_rand_debug_req + test_cfg: gen_rand_int,debug_single_step_en skip_sim: pulp # note: current fp streams excluding ebreak insn @@ -185,7 +185,7 @@ tests: # build: uvmt_cv32e40p # dir: cv32e40p/sim/uvmt # cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" -# test_cfg: gen_rand_int,debug_ebreak,gen_rand_debug_req +# test_cfg: gen_rand_int,debug_ebreak # skip_sim: pulp # # corev_rand_fp_instr_debug_test_with_int_debug_trigger_and_ebreak: @@ -194,7 +194,7 @@ tests: # build: uvmt_cv32e40p # dir: cv32e40p/sim/uvmt # cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" -# test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak,gen_rand_debug_req +# test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak # skip_sim: pulp corev_rand_fp_instr_debug_test_with_int_debug_trigger_and_single_step: @@ -203,7 +203,7 @@ tests: build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=10000000" - test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en,gen_rand_debug_req + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en skip_sim: pulp # Add corev_rand_fp_instr_debug similar to corev_rand_pulp_instr_debug with f/zfinx insn included - END diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml index b2aa4a8f49..405ed9733e 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml @@ -6,15 +6,15 @@ name: corev_rand_fp_instr_debug uvm_test: $(CV_CORE_LC)_instr_base_test description: > - RISCV-DV generated random pulp instr test + RISCV-DV generated random fp instr with random debug plusargs: > +instr_cnt=1000 +num_of_sub_program=0 +insert_rand_directed_instr_stream=1 +test_rand_directed_instr_stream_num=8 - +directed_instr_0=cv32e40p_constraint_mc_fp_instr_stream,4 - +directed_instr_1=cv32e40p_fp_op_fwd_instr_stream,4 - +directed_instr_2=cv32e40p_fp_op_fwd_instr_w_loadstore_stream,4 + +directed_instr_0=cv32e40p_constraint_mc_fp_instr_stream,2 + +directed_instr_1=cv32e40p_fp_op_fwd_instr_stream,2 + +directed_instr_2=cv32e40p_fp_op_fwd_instr_w_loadstore_stream,2 +rand_directed_instr_0=riscv_load_store_rand_instr_stream,1 +rand_directed_instr_1=riscv_load_store_hazard_instr_stream,1 +rand_directed_instr_2=riscv_multi_page_load_store_instr_stream,1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml index 331c558b71..14f38d205a 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/test.yaml @@ -5,6 +5,6 @@ name: corev_rand_fp_instr_debug uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > - Random debug in xpulp instruction stream + Random debug in fp instruction stream plusargs: > - # +gen_reduced_rand_dbg_req + +gen_reduced_rand_dbg_req From 4f442d07b7615c2c509589fe5426ae6f324c966b Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Fri, 12 Jan 2024 00:07:13 +0100 Subject: [PATCH 72/97] added seed field option in regress YAML files to specify a unique seed number for a specific test item --- bin/lib/cv_regression.py | 5 +++++ bin/templates/regress_rmdb.j2 | 7 +++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/bin/lib/cv_regression.py b/bin/lib/cv_regression.py index 076175f676..d68b00a960 100644 --- a/bin/lib/cv_regression.py +++ b/bin/lib/cv_regression.py @@ -96,6 +96,11 @@ def __init__(self, **kwargs): if not hasattr(self, 'log'): self.log = self.name + if hasattr(self, 'seed'): + self.seed_override = 1 + else: + self.seed_override = 0 + def set_cov(self): '''Set the coverage flag based on app setting. If cov already defined (from testlist), then ignore''' diff --git a/bin/templates/regress_rmdb.j2 b/bin/templates/regress_rmdb.j2 index d4ee9ac580..ffc37bfe86 100644 --- a/bin/templates/regress_rmdb.j2 +++ b/bin/templates/regress_rmdb.j2 @@ -61,7 +61,10 @@ - proc getSeeds { num mode regr_name } { + proc getSeeds { num mode regr_name seed_override seed_value } { + if { $seed_override == "1" } { + return $seed_value + } if {[string equal $mode "FIXED"]} { return [GetRandomValues $num] } @@ -183,7 +186,7 @@ [getTestCfgName "(%t_test_cfg:%)"] [getParameterByPriorityYesOrNo "{{iss}}" "{{t.iss}}" "(%build_iss:%)"] [getParameterByPriorityYesOrNo "{{coverage}}" "{{t.cov}}" "(%build_cov:%)"] - [getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)"] + [getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)" "{{t.seed_override}}" "{{t.seed}}"] [file join "(%results_sim_path%)" "(%t_cfg%)" "{{t.testname}}" "(%t_test_cfg_name:%)" (%t_iteration%)] [getTestName "{{t.testname}}" "(%t_cfg%)" "(%t_test_cfg_name:%)" (%t_iteration%)] [getUCDBFilename "{{t.testname}}" "(%t_test_cfg_name:%)"] From d223e8742a49dde2190f33370cf2ce65ff809f53 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Fri, 12 Jan 2024 00:07:50 +0100 Subject: [PATCH 73/97] updated failing debug_test_boot_set test item in regress files --- cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml | 4 ++-- cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index 447b32cfc6..b00debcfa1 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -109,7 +109,8 @@ tests: build: uvmt_cv32e40p description: debug_test_boot_set (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" SEED=1 VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + seed: 1 num: 1 debug_test_known_miscompares: @@ -291,4 +292,3 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=20000000" test_cfg: gen_rand_int,debug_trigger_basic - diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 442b86ae46..a816ff0652 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -297,7 +297,8 @@ tests: build: uvmt_cv32e40p description: debug_test_boot_set (adapted from v1) dir: cv32e40p/sim/uvmt - cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" SEED=1 VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + cmd: make test COREV=YES TEST=debug_test_boot_set CFG_PLUSARGS="+UVM_TIMEOUT=20000000" VSIM_USER_FLAGS=+fixed_instr_gnt_stall=10 + seed: 1 num: 1 debug_test_known_miscompares: From ee0a2c2e504cb3593adf7fb164c69f97b4782f4c Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Fri, 12 Jan 2024 20:01:51 +0800 Subject: [PATCH 74/97] Increase timeout Signed-off-by: dd-baoshan --- .../regress/cv32e40pv2_interrupt_debug.yaml | 2 +- .../cv32e40pv2_interrupt_debug_long.yaml | 2 +- .../cv32e40pv2_interrupt_debug_short.yaml | 18 +++++++++--------- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index b00debcfa1..c10dabb5e6 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -95,7 +95,7 @@ tests: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=15000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=20000000" num: 1 debug_test: diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml index 2d70bf12fd..4acb57f36e 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml @@ -85,7 +85,7 @@ tests: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=15000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=20000000" corev_rand_pulp_hwloop_debug_single_step: testname: corev_rand_pulp_hwloop_debug diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index a816ff0652..2a263fcde2 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -212,14 +212,14 @@ tests: build: uvmt_cv32e40p description: hwloop debug random test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_pulp_hwloop_test_with_random_debug: testname: corev_rand_pulp_hwloop_test description: hwloop random debug req test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_debug_req corev_rand_pulp_hwloop_debug_ebreak: @@ -227,7 +227,7 @@ tests: description: hwloop ebreak debug random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_ebreak corev_rand_pulp_hwloop_debug_trigger: @@ -235,7 +235,7 @@ tests: description: hwloop debug random test with debug trigger on instr addr match build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic corev_rand_pulp_hwloop_debug_trigger_with_ebreak: @@ -243,7 +243,7 @@ tests: description: hwloop debug random test with debug trigger and ebreak build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: debug_trigger_basic,debug_ebreak corev_rand_pulp_hwloop_debug_with_interrupt: @@ -251,7 +251,7 @@ tests: description: hwloop debug with interrupt random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int corev_rand_pulp_hwloop_debug_with_int_debug_trigger: @@ -259,7 +259,7 @@ tests: description: hwloop debug with interrupt and debug trigger random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_trigger_basic corev_rand_pulp_hwloop_debug_with_int_debug_ebreak: @@ -267,7 +267,7 @@ tests: description: hwloop debug with interrupt and debug ebreak random test build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_ebreak corev_rand_pulp_hwloop_interrupt_test: @@ -275,7 +275,7 @@ tests: description: hwloop test with random interrupts build: uvmt_cv32e40p dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=25000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int corev_rand_pulp_hwloop_exception_debug_trigger: From 6e7ff88bea7c0db85da2dc2ebbe3ed17fa18aa11 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Fri, 12 Jan 2024 20:02:33 +0800 Subject: [PATCH 75/97] Tempoary exclude Imperas func coverage. Re-enable when newer version is available Signed-off-by: dd-baoshan --- .../tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh | 2 +- mk/uvmt/vsim.mk | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh index ce76581445..af76cecb24 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_riscv_coverage_config.svh @@ -7,7 +7,7 @@ `define COVER_BASE_RV32I `define COVER_LEVEL_COMPL_BAS //`define COVER_LEVEL_COMPL_EXT - `define COVER_LEVEL_DV_UP_BAS + // `define COVER_LEVEL_DV_UP_BAS // fixme: this is needed for some f/zfinx cp //`define COVER_LEVEL_DV_UP_EXT //`define COVER_LEVEL_DV_PR_BAS //`define COVER_LEVEL_DV_PR_EXT diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk index 2688b6f71f..f921c52287 100644 --- a/mk/uvmt/vsim.mk +++ b/mk/uvmt/vsim.mk @@ -42,10 +42,11 @@ VSIM_COV_ONLY_PASS_TEST ?= YES VSIM_LOCAL_MODELSIMINI ?= YES VOPT_CODE_COV_DUT_ONLY ?= YES VSIM_USER_FLAGS ?= -# note: t or toggle is excluded in cv32e40p_v2 ifeq ($(call IS_YES,$(VOPT_CODE_COV_DUT_ONLY)),YES) +# note: t/toggle is excluded in cv32e40p_v2 VOPT_COV ?= +cover=bcsef+$(RTLSRC_VLOG_CORE_TOP). else +# note: t/toggle is excluded in cv32e40p_v2 VOPT_COV ?= +cover=sef+$(RTLSRC_VLOG_TB_TOP). endif VSIM_COV ?= -coverage +uvm_set_config_int=uvm_test_top,cov_model_enabled,1 @@ -148,7 +149,7 @@ VLOG_FLAGS += +define+USE_ISS VLOG_FLAGS += +define+USE_IMPERASDV VLOG_FILE_LIST_IDV = -f $(DV_UVMT_PATH)/imperas_dv.flist ifeq ($(call IS_YES,$(COV)),YES) -VLOG_FLAGS += +define+IMPERAS_COV +# VLOG_FLAGS += +define+IMPERAS_COV // fixme: add granuality for this enablement endif endif ifeq ($(call IS_YES,$(COV)),YES) From 19edee3f736a9d6dad1eee663685f76fc11f5265 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Fri, 12 Jan 2024 21:24:13 +0800 Subject: [PATCH 76/97] Fix to handle corner case events Signed-off-by: dd-baoshan --- .../env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 240028aaac..46ebffa918 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -99,6 +99,7 @@ class uvme_rv32x_hwloop_covg # ( local bit [(ILEN-1):0] insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ local bit [(ILEN-1):0] mc_insn_list_in_hwloop_``TYPE [HWLOOP_NB][$]; \ local bit [31:0] irq_vect_``TYPE [HWLOOP_NB][$]; \ + local bit lpend_has_pending_irq_``TYPE [HWLOOP_NB] = '{default:0}; \ local bit done_insn_list_capture_``TYPE [HWLOOP_NB] = '{default:0}; \ local bit done_insn_list_capture_d1_``TYPE [HWLOOP_NB] = '{default:0}; \ local s_hwloop_cov hwloop_cov_``TYPE [HWLOOP_NB] = '{default:0}; @@ -469,6 +470,7 @@ class uvme_rv32x_hwloop_covg # ( end // UPDATE_HWLOOP_STAT \ for (int i=0; i= 0); \ @@ -527,6 +530,7 @@ class uvme_rv32x_hwloop_covg # ( check_ebreakm_entry(i); \ end \ if (is_pc_equal_lpend(hwloop_stat_``TYPE``.hwloop_csr, i, 0, cv32e40p_rvvi_vif.pc_rdata) && hwloop_stat_``TYPE``.track_lp_cnt[i] != 0) begin \ + if (pending_irq) lpend_has_pending_irq_``TYPE``[i] = 1; \ hwloop_stat_``TYPE``.track_lp_cnt[i]--; \ done_insn_list_capture_``TYPE``[i] = 1; \ assert(hwloop_stat_``TYPE``.track_lp_cnt[i] >= 0); \ @@ -728,6 +732,7 @@ class uvme_rv32x_hwloop_covg # ( end \ hwloop_evt_loc_``TYPE``[i][MC_INSN].delete(); \ hwloop_cov_``TYPE``[i].en_cov_mc_insn = 0; \ + lpend_has_pending_irq_``TYPE``[i] = 0; \ done_insn_list_capture_``TYPE``[i] = 0; \ done_insn_list_capture_d1_``TYPE``[i] = 0; \ hwloop_cov_``TYPE``[i] = hwloop_cov_init[i]; \ @@ -807,11 +812,11 @@ class uvme_rv32x_hwloop_covg # ( is_trap = 1; case (cv32e40p_rvvi_vif.insn) TB_INSTR_EBREAK, INSTR_CBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin - @(posedge cv32e40p_rvvi_vif.clk); continue; - end - else begin is_ebreak = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to EBREAK"), UVM_DEBUG); end - TB_INSTR_ECALL : begin is_ecall = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to ECALL"), UVM_DEBUG); end - default : begin is_illegal = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to ILLEGAL"), UVM_DEBUG); end + @(posedge cv32e40p_rvvi_vif.clk); continue; + end + else begin is_ebreak = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to EBREAK"), UVM_DEBUG); end + TB_INSTR_ECALL : begin is_ecall = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to ECALL"), UVM_DEBUG); end + default : begin is_illegal = 1; `uvm_info(_header, $sformatf("DEBUG - EXCEPTION Entry due to ILLEGAL"), UVM_DEBUG); end endcase wait (!(is_ebreak | is_ecall | is_illegal)); end @@ -849,6 +854,20 @@ class uvme_rv32x_hwloop_covg # ( is_irq = 0; end end // IRQ_EXIT + forever begin : SIGNALS_CHG_WHEN_IS_IRQ_ASSERT + @(posedge is_irq); + if (is_ebreakm) begin + for (int j=0; j Date: Mon, 15 Jan 2024 15:30:58 +0100 Subject: [PATCH 77/97] Added FP enable depending on configuration. Signed-off-by: Pascal Gouedo --- .../interrupt_bootstrap/interrupt_bootstrap.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c b/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c index e0754b39e4..ef2e3725f8 100644 --- a/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c +++ b/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c @@ -168,9 +168,29 @@ int test_mtvec() { return EXIT_SUCCESS; } +#ifdef FPU +#define MSTATUS_FS_INITIAL 0x00002000 + +void fp_enable () +{ + unsigned int fs = MSTATUS_FS_INITIAL; + + asm volatile("csrs mstatus, %0;" + "csrwi fcsr, 0;" + "csrs mstatus, %0;" + : : "r"(fs) + ); +} +#endif + int main(int argc, char *argv[]) { int retval; +#ifdef FPU + // Floating Point enable + fp_enable(); +#endif + // Trash the "default" 0 table for (int i = 0; i < 32; i++) { volatile uint32_t *ptr = (volatile uint32_t *) (0 + i*4); From 7716d48c98a94f0e18c4c88cdc5517f9b1243a12 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 15 Jan 2024 15:40:46 +0100 Subject: [PATCH 78/97] Indentation corrected. Signed-off-by: Pascal Gouedo --- .../programs/custom/interrupt_bootstrap/interrupt_bootstrap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c b/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c index ef2e3725f8..f560f4db3a 100644 --- a/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c +++ b/cv32e40p/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c @@ -187,8 +187,8 @@ int main(int argc, char *argv[]) { int retval; #ifdef FPU - // Floating Point enable - fp_enable(); + // Floating Point enable + fp_enable(); #endif // Trash the "default" 0 table From 93117b0351fcf837a5a77f68e6be02b2af2029bf Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Fri, 19 Jan 2024 19:55:34 +0800 Subject: [PATCH 79/97] Increase test timeout Signed-off-by: dd-baoshan --- cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml | 2 +- cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml | 2 +- cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index c10dabb5e6..e4c7aaaa5b 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -95,7 +95,7 @@ tests: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000" num: 1 debug_test: diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml index 4acb57f36e..62571b23b7 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml @@ -85,7 +85,7 @@ tests: build: uvmt_cv32e40p description: corev_rand_interrupt_wfi_mem_stress dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000" corev_rand_pulp_hwloop_debug_single_step: testname: corev_rand_pulp_hwloop_debug diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index 9212df1ff1..0765af4896 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -28,7 +28,7 @@ tests: build: uvmt_cv32e40p description: corev_rand_pulp_hwloop_test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=20000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_pulp_instr_test: build: uvmt_cv32e40p @@ -52,7 +52,7 @@ tests: build: uvmt_cv32e40p description: hwloop exception test dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=15000000" + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000" corev_rand_pulp_illegal_instr_test: testname: corev_rand_pulp_instr_test From d3e7cad71a660f10db2032fad6cf4f225c9d80e2 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Fri, 19 Jan 2024 19:58:40 +0800 Subject: [PATCH 80/97] Fix to handle case when irq, debug and exception happen together Signed-off-by: dd-baoshan --- cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 46ebffa918..ddc178e558 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -808,7 +808,9 @@ class uvme_rv32x_hwloop_covg # ( is_trap = 0; wait (!cv32e40p_rvvi_vif.trap); // bypass if garbage data exist end - else if (((cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0) || prev_irq_onehot_priority_is_0) && !pending_irq && !is_dbg_mode && !is_irq) begin // set excep flag only if no pending irq and not in dbg mode + else if ( + ((cv32e40p_rvvi_vif.irq_onehot_priority == 0 && prev_irq_onehot_priority == 0) || prev_irq_onehot_priority_is_0 || cv32e40p_rvvi_vif.csr_dcsr_step) && + !pending_irq && !is_dbg_mode && !is_irq) begin // set excep flag only if no pending irq and not in dbg mode is_trap = 1; case (cv32e40p_rvvi_vif.insn) TB_INSTR_EBREAK, INSTR_CBREAK : if (cv32e40p_rvvi_vif.csr_dcsr_ebreakm) begin @@ -916,7 +918,7 @@ class uvme_rv32x_hwloop_covg # ( if (enter_hwloop_sub) begin enter_hwloop_sub_cnt++; - if (is_trap && is_dbg_mode && enter_hwloop_sub_cnt == 1) begin : TRAP_DUETO_DBG_ENTRY // trap (exception) cycle and debug are b2b + if (is_trap && is_dbg_mode && !cv32e40p_rvvi_vif.csr_dcsr_step && enter_hwloop_sub_cnt == 1) begin : TRAP_DUETO_DBG_ENTRY // exception trap and debug are b2b cycles (except debug step) is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; prev_pc_rdata_main = prev_pc_rdata_main-4; for (int j=0; j Date: Fri, 19 Jan 2024 20:00:57 +0800 Subject: [PATCH 81/97] Update core-v-cores hash to head Signed-off-by: dd-baoshan --- cv32e40p/sim/ExternalRepos.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index 3b9572f57e..ed088f9f11 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40p CV_CORE_BRANCH ?= dev -CV_CORE_HASH ?= c010206894d1f2143ffcfac751bdb2351d08ffdc +CV_CORE_HASH ?= head CV_CORE_TAG ?= none # The CV_CORE_HASH above points to version of the RTL that is newer. From 3de68c7c1ce80ddbd196c7e6f7cd1b875b305c16 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Fri, 19 Jan 2024 20:08:46 +0800 Subject: [PATCH 82/97] Update fp debug test to reserved debug pointer register Signed-off-by: dd-baoshan --- .../instr_lib/cv32e40p_float_instr_lib.sv | 57 ++++++++++++------- .../corev_rand_fp_instr_debug/corev-dv.yaml | 1 + 2 files changed, 37 insertions(+), 21 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index 0289ef12e4..6e8dbf1464 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -36,27 +36,28 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; `include "instr_lib/cv32e40p_float_instr_lib_defines.sv" // properties - start - string _header; - bit is_zfinx = riscv_instr_pkg::RV32ZFINX inside {riscv_instr_pkg::supported_isa}; - bit is_fp_instr, is_fpc_instr; - riscv_instr_name_t include_instr[]; - riscv_instr_name_t exclude_instr[]; - riscv_instr_category_t include_category[]; - riscv_instr_category_t exclude_category[]; - riscv_instr_group_t include_group[]; - riscv_instr_group_t exclude_group[]; - bit use_special_operand_patterns; // use special pattern opeands on directed instrs - bit use_fp_only_for_directed_instr; // use fp instr only as directed instrs in stream - bit use_no_repetitive_instr_per_stream; // directed instr is not allow to repeat in a stream - bit use_same_instr_per_stream; // same directed is use within a stream - bit use_prev_rd_on_next_operands; // previous instr rd is used for directed instr operands - bit use_diff_regs_for_operands = 0; // to control rand instr uses different registers for instr oeprands - bit more_weight_for_fdiv_fsqrt_gen; // more weight on generating fdiv and fsqrt directed_instr - bit init_gpr = (is_zfinx) ? 1 : 0; // initialize gpr registers in stream with rand value - bit init_fpr = (is_zfinx) ? 0 : 1; // initialize fpr registers in stream with rand value - bit en_clr_fflags_af_instr; // clear fflag to prevent residual fflags status of current f_instr - bit en_clr_fstate; // clean the fstate for current f_instr - bit include_load_store_base_sp; // include store instr that uses sp + string _header; + cv32e40p_instr_gen_config cfg_cv32e40p; + bit is_zfinx = riscv_instr_pkg::RV32ZFINX inside {riscv_instr_pkg::supported_isa}; + bit is_fp_instr, is_fpc_instr; + riscv_instr_name_t include_instr[]; + riscv_instr_name_t exclude_instr[]; + riscv_instr_category_t include_category[]; + riscv_instr_category_t exclude_category[]; + riscv_instr_group_t include_group[]; + riscv_instr_group_t exclude_group[]; + bit use_special_operand_patterns; // use special pattern opeands on directed instrs + bit use_fp_only_for_directed_instr; // use fp instr only as directed instrs in stream + bit use_no_repetitive_instr_per_stream; // directed instr is not allow to repeat in a stream + bit use_same_instr_per_stream; // same directed is use within a stream + bit use_prev_rd_on_next_operands; // previous instr rd is used for directed instr operands + bit use_diff_regs_for_operands = 0; // to control rand instr uses different registers for instr oeprands + bit more_weight_for_fdiv_fsqrt_gen; // more weight on generating fdiv and fsqrt directed_instr + bit init_gpr = (is_zfinx) ? 1 : 0; // initialize gpr registers in stream with rand value + bit init_fpr = (is_zfinx) ? 0 : 1; // initialize fpr registers in stream with rand value + bit en_clr_fflags_af_instr; // clear fflag to prevent residual fflags status of current f_instr + bit en_clr_fstate; // clean the fstate for current f_instr + bit include_load_store_base_sp; // include store instr that uses sp // for use_prev_rd_on_next_operands implementation usage - start riscv_reg_t prev_rd; @@ -116,7 +117,11 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; soft avail_gp_regs[i][0] inside {[S0:A5]}; // MUST: RV32C only uses 8 most common xregs soft avail_gp_regs[i][1] inside {SP}; // MUST: some random instr uses SP as rd foreach (avail_gp_regs[i][j]) { + if (cfg.gen_debug_section) { + !(avail_gp_regs[i][j] inside {cfg.reserved_regs, reserved_rd, gp_reg_scratch, gp_reg_sp, cfg_cv32e40p.dp}); + } else { !(avail_gp_regs[i][j] inside {cfg.reserved_regs, reserved_rd, gp_reg_scratch, gp_reg_sp}); + } } } } @@ -176,6 +181,11 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; en_clr_fflags_af_instr = 1; en_clr_fstate = 0; include_load_store_base_sp = $urandom_range(1); + if (cfg.gen_debug_section) begin + if (!$cast(cfg_cv32e40p, cfg)) begin + `uvm_fatal(_header, $sformatf("pre_randomize - cfg_cv32e40p casting failed")); + end + end endfunction: pre_randomize function void post_randomize(); @@ -347,6 +357,11 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream; logic [31:0] i_imm; for (int i=1; i<32; i++) begin riscv_reg_t i_gpr = riscv_reg_t'(i); + if (cfg.gen_debug_section) begin + if (i == int'(cfg_cv32e40p.dp)) begin + continue; + end + end rand_fp_val(i_imm); `SET_GPR_VALUE(i_gpr,i_imm); end diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml index 405ed9733e..2cbfb1fa66 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml @@ -36,3 +36,4 @@ plusargs: > +enable_misaligned_instr=1 +test_override_riscv_instr_stream=1 +test_override_riscv_instr_sequence=1 + +gen_debug_section=1 From 2929c3f810caff851f9ca12aa04e19a077ba3f52 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Fri, 19 Jan 2024 15:09:24 +0100 Subject: [PATCH 83/97] added directed test for all illegal instruction for custom opcodes --- .../custom_ocpode_illegal_test.S | 5131 +++++++++++++++++ .../custom_opcode_illegal_test/test.yaml | 6 + 2 files changed, 5137 insertions(+) create mode 100644 cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_ocpode_illegal_test.S create mode 100644 cv32e40p/tests/programs/custom/custom_opcode_illegal_test/test.yaml diff --git a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_ocpode_illegal_test.S b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_ocpode_illegal_test.S new file mode 100644 index 0000000000..9a61ddcf60 --- /dev/null +++ b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_ocpode_illegal_test.S @@ -0,0 +1,5131 @@ +.include "user_define.h" +.section .text.start + +.section .mtvec_bootstrap, "ax" +.globl _mtvec_bootstrap + j mtvec_handler + +.globl _start +.section .init +#.include "user_init.s" +.type _start, @function + +_start: + j _start_main + +.globl _start_main +.globl mtvec_handler +.section .text +_start_main: +h0_start: + li x22, 0x40801104 + csrw 0x301, x22 +kernel_sp: + la x31, kernel_stack_end + +trap_vec_init: + la x22, mtvec_handler + ori x22, x22, 1 + csrw 0x305, x22 # MTVEC + +mepc_setup: + la x22, init + csrw mepc, x22 + +custom_csr_setup: + nop + +init_machine_mode: + li x22, 0x58401844 + csrw 0x300, x22 # MSTATUS + li x22, 0x62079444 + csrw 0x304, x22 # MIE + mret +init: + li a0, 0x80000000 + li s0, 0x19 + li x0, 0x0 + li x1, 0x0 + li x3, 0x9d413784 + li x4, 0xe + li x5, 0xfeae9769 + li x6, 0x80000000 + li x7, 0xf7bf2feb + li x8, 0x0 + li x9, 0x38d06566 + li x10, 0x0 + li x11, 0x0 + li x12, 0x6 + li x13, 0x80000000 + li x14, 0x93130db0 + li x15, 0xa + li x16, 0x0 + li x17, 0x9bbac4e2 + li x18, 0x0 + li x19, 0x80000000 + li x20, 0x80000000 + li x21, 0x80000000 + li x22, 0x80000000 + li x23, 0xf5e35c4d + li x24, 0xd18d2d96 + li x25, 0xf5321cad + li x26, 0xffc4b9d7 + li x27, 0xb + li x28, 0x6 + li x29, 0x80000000 + li x30, 0x0 + li a0, 0x80000000 + li s0, 0xd0 + la x2, user_stack_end +main: fence.i + slli t4, s1, 18 + lui s1, 389032 + sub s3, s6, t0 + and t2, s5, s3 + fence + c.srli s1, 23 + addi t2, t0, 337 + sll t0, t2, t0 + c.nop + # .4byte 0x80fe4c33 # manual: opcode = OP, func7 = 1000000 + .4byte 0x3e0003fb # custom-3 + .4byte 0xb286bdfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x5f57cbfb # custom-3 cv.cplxconj block + .4byte 0xe097acfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd6433aab # custom-1 Plane A illegal func7 + .4byte 0x0207bbfb # custom-3 + .4byte 0xb68748ab # custom-1 plane B + .4byte 0x0ad450fb # custom-3 + .4byte 0x6abd057b # custom-3 + .4byte 0x6657eefb # custom-3 cv.subrotmj block + .4byte 0x2baa46fb # custom-3 + .4byte 0x872c4cab # custom-1 plane B + .4byte 0x1f5f0dfb # custom-3 + .4byte 0x2665817b # custom-3 + .4byte 0xb2dcbd2b # custom-1 Plane A illegal func7 + .4byte 0xa80616db # custom-2 + .4byte 0x935e422b # custom-1 plane B + .4byte 0xe9bf917b # all the groups of 8 illegal instr in custom-3 + .4byte 0x4977c42b # custom-1 plane B + .4byte 0xd8eecdab # custom-1 plane B + .4byte 0x63a51d7b # custom-3 + .4byte 0x5ca58c7b # custom-3 cv.cplxconj block + .4byte 0x6205c4ab # custom-1 plane B + .4byte 0x22d5bd7b # custom-3 + .4byte 0x5bb4c57b # custom-3 + .4byte 0xb30a827b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe273d6ab # custom-1 func3 = 101 + .4byte 0x7ecdb1fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xc6df492b # custom-1 plane B + .4byte 0x6784b62b # legal func7 but non-zero value for rs2 + .4byte 0x712de1fb # custom-3 cv.abs(.h/.b) & below + .4byte 0x6cfbfc7b # custom-3 cv.add/sub.div blocks + .4byte 0x73a4997b # custom-3 cv.abs(.h/.b) & below + .4byte 0xe8c65dfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x7d1ee3fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xf96a9efb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x6f826e7b # custom-3 cv.add/sub.div blocks + .4byte 0x9002442b # custom-1 plane B + .4byte 0xc98f247b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x175eb97b # custom-3 + .4byte 0xb1cc547b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe1844c2b # custom-1 plane B + .4byte 0xf9500f7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7e793dab # custom-1 Plane A illegal func7 + .4byte 0xeeef1adb # custom-2 bitrev 29:27 + .4byte 0x8aa344fb # custom-3 + .4byte 0xe09c985b # custom-2 bitrev 29:27 + .4byte 0xe93b847b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe84988db # custom-2 + .4byte 0xb795195b # custom-2 + .4byte 0xef279ddb # custom-2 bitrev 29:27 + .4byte 0x22f4447b # custom-3 + .4byte 0x7f02237b # all the groups of 8 illegal instr in custom-3 + .4byte 0x969cb5ab # custom-1 Plane A illegal func7 + .4byte 0xe8d3c8ab # custom-1 plane B + .4byte 0x60f4b3ab # legal func7 but non-zero value for rs2 + .4byte 0xf7cf41ab # custom-1 plane B + .4byte 0xd04494db # custom-2 bitrev 29:27 + .4byte 0x6d25547b # custom-3 cv.add/sub.div blocks + .4byte 0xa267537b # custom-3 + .4byte 0xd19e35fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x93ff12fb # custom-3 + .4byte 0xaabea37b # custom-3 + .4byte 0x658ab92b # legal func7 but non-zero value for rs2 + .4byte 0x0c304bab # custom-1 plane B + .4byte 0x7b44eafb # all the groups of 8 illegal instr in custom-3 + .4byte 0xdf5006db # custom-2 + .4byte 0xbc81985b # custom-2 + .4byte 0x56974b2b # custom-1 plane B + .4byte 0xc86257fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x5b4a257b # custom-3 + .4byte 0x528e957b # custom-3 + .4byte 0x0f4a247b # custom-3 + .4byte 0x72685d7b # custom-3 cv.abs(.h/.b) & below + .4byte 0x0b02b87b # custom-3 + .4byte 0x3a484d7b # custom-3 + .4byte 0xca413e0b # cv.elw + .4byte 0x21bd452b # custom-1 plane B + .4byte 0xe2a0c1fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xfcbf0e5b # custom-2 + .4byte 0xbfe4caab # custom-1 plane B + .4byte 0x6b3d3eab # custom-1 Plane A illegal func7 + .4byte 0xfc954d2b # custom-1 plane B + .4byte 0xe1c04f2b # custom-1 plane B + .4byte 0xcd6ac82b # custom-1 plane B + .4byte 0xfe77b0ab # custom-1 Plane A illegal func7 + .4byte 0x7bf6c77b # all the groups of 8 illegal instr in custom-3 + .4byte 0xcb03875b # custom-2 + .4byte 0xcb07667b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf8dd11db # custom-2 bitrev 29:27 + .4byte 0x2eccac7b # custom-3 + .4byte 0x7f550cfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x338b9efb # custom-3 + .4byte 0x3202257b # custom-3 + .4byte 0x503deaab # custom-1 func3 = 110 + .4byte 0x794274fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xed218d5b # custom-2 + .4byte 0x54f6957b # custom-3 cv.cplxmul block + .4byte 0xab7481fb # custom-3 + .4byte 0x0cfe41ab # custom-1 plane B + .4byte 0xda8b36ab # custom-1 Plane A illegal func7 + .4byte 0x52c9d67b # custom-3 + .4byte 0x4a4bf1ab # custom-1 func3 = 111 + .4byte 0xcbcab72b # custom-1 Plane A illegal func7 + .4byte 0xc9e6bb2b # custom-1 Plane A illegal func7 + .4byte 0x4a4e5b7b # custom-3 + .4byte 0xfaba2c7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf32bb72b # custom-1 Plane A illegal func7 + .4byte 0xae4fc3ab # custom-1 plane B + .4byte 0xeac39a7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x93df50fb # custom-3 + .4byte 0xf0c65d7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xaa7c4efb # custom-3 + .4byte 0x6bdcbd7b # custom-3 + .4byte 0xd1c442ab # custom-1 plane B + .4byte 0x4fad05fb # custom-3 + .4byte 0x477c157b # custom-3 + .4byte 0xe39e847b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x6c44c32b # custom-1 plane B + .4byte 0x0ff840ab # custom-1 plane B + .4byte 0x72d04afb # custom-3 cv.abs(.h/.b) & below + .4byte 0x2e8cba7b # custom-3 + .4byte 0x4501bdab # legal func7 but non-zero value for rs2 + .4byte 0xab8c567b # custom-3 + .4byte 0xd192caab # custom-1 plane B + .4byte 0x71519cfb # custom-3 cv.abs(.h/.b) & below + .4byte 0xdb13ae7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xe1e3cdfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd07c9bdb # custom-2 bitrev 29:27 + .4byte 0x03b598fb # custom-3 + .4byte 0xc34ec77b # custom-3 cv.shuffle block + .4byte 0x7fa1dcfb # all the groups of 8 illegal instr in custom-3 + .4byte 0xcbdf337b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x9b232cfb # custom-3 + .4byte 0xc571005b # custom-2 + .4byte 0x0b781cfb # custom-3 + .4byte 0xfbf039fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x4f1611fb # custom-3 + .4byte 0x5c63d87b # custom-3 cv.cplxconj block + .4byte 0x9a9fb52b # custom-1 Plane A illegal func7 + .4byte 0x0e70d37b # custom-3 + .4byte 0xe9cdf47b # all the groups of 8 illegal instr in custom-3 + .4byte 0x43efddfb # custom-3 + .4byte 0x31f5caab # custom-1 plane B + .4byte 0x0a6a45fb # custom-3 + .4byte 0x7bd2b87b # all the groups of 8 illegal instr in custom-3 + .4byte 0xcbaa427b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7849457b # all the groups of 8 illegal instr in custom-3 + .4byte 0x1b0c4c2b # custom-1 plane B + .4byte 0x8fa5ca2b # custom-1 plane B + .4byte 0xce15b0ab # custom-1 Plane A illegal func7 + .4byte 0xce2842ab # custom-1 plane B + .4byte 0xf0df987b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x644dceab # custom-1 plane B + .4byte 0x189fc22b # custom-1 plane B + .4byte 0xc833b1fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x491a36ab # legal func7 but non-zero value for rs2 + .4byte 0xdbc4857b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x2374997b # custom-3 + .4byte 0xbb9b6c7b # custom-3 cv.extract/insert block + .4byte 0xc369d6fb # custom-3 cv.shuffle block + .4byte 0x1f3e427b # custom-3 + .4byte 0xa31bbc7b # custom-3 + .4byte 0x277dc1ab # custom-1 plane B + .4byte 0x06f78afb # custom-3 + .4byte 0xf86fdf7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xbc3e93db # custom-2 + .4byte 0xd03706fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7d79b22b # custom-1 Plane A illegal func7 + .4byte 0x17fa4efb # custom-3 + .4byte 0x4c21c0ab # custom-1 plane B + .4byte 0x074dbefb # custom-3 + .4byte 0xd0434dfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x82a022fb # custom-3 + .4byte 0x1bf15f7b # custom-3 + .4byte 0xd1bcd9fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd85888fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd051342b # custom-1 Plane A illegal func7 + .4byte 0x4b1a41fb # custom-3 + .4byte 0xe1c883fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x6dc1937b # custom-3 cv.add/sub.div blocks + .4byte 0xa253a77b # custom-3 + .4byte 0xa7db3dab # custom-1 Plane A illegal func7 + .4byte 0xab5cbffb # custom-3 + .4byte 0x7b41442b # custom-1 plane B + .4byte 0xcb0b007b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xc424ceab # custom-1 plane B + .4byte 0x4afcc8ab # custom-1 plane B + .4byte 0x1311127b # custom-3 + .4byte 0x3354c2ab # custom-1 plane B + .4byte 0x88e04a2b # custom-1 plane B + .4byte 0xf595b92b # custom-1 Plane A illegal func7 + .4byte 0x625baffb # custom-3 + .4byte 0x7841847b # all the groups of 8 illegal instr in custom-3 + .4byte 0xf7aeb5ab # custom-1 Plane A illegal func7 + .4byte 0x6c3a3afb # custom-3 cv.add/sub.div blocks + .4byte 0xeb23d6fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xe2c9137b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x37f20b7b # custom-3 + .4byte 0xf39d697b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x5e3fe8fb # custom-3 cv.cplxconj block + .4byte 0x07afa9fb # custom-3 + .4byte 0x6af8227b # custom-3 + .4byte 0x32be3a7b # custom-3 + .4byte 0x569f1e7b # custom-3 cv.cplxmul block + .4byte 0x1a8fbc7b # custom-3 + .4byte 0x2e3cb7ab # custom-1 Plane A illegal func7 + .4byte 0xb25ff5fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x1554c1ab # custom-1 plane B + .4byte 0x94754e2b # custom-1 plane B + .4byte 0x80d54fab # custom-1 plane B + .4byte 0xf0ce3d2b # custom-1 Plane A illegal func7 + .4byte 0xcddc00db # custom-2 + .4byte 0x42a1beab # legal func7 but non-zero value for rs2 + .4byte 0xe7debc2b # custom-1 Plane A illegal func7 + .4byte 0x6f4bbe7b # custom-3 cv.add/sub.div blocks + .4byte 0xbcdfbc2b # custom-1 Plane A illegal func7 + .4byte 0x7cab427b # all the groups of 8 illegal instr in custom-3 + .4byte 0x32794eab # custom-1 plane B + .4byte 0x63cbdcfb # custom-3 + .4byte 0x2eef99fb # custom-3 + .4byte 0xf84dcbfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xac8f38ab # custom-1 Plane A illegal func7 + .4byte 0xd9fd65fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x9c0291db # custom-2 + .4byte 0xea9cc97b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe9e210db # custom-2 bitrev 29:27 + .4byte 0xdd4f4dab # custom-1 plane B + .4byte 0x5202377b # custom-3 + .4byte 0x806a1bdb # custom-2 + .4byte 0xcc4abcab # custom-1 Plane A illegal func7 + .4byte 0x2211aafb # custom-3 + .4byte 0xce96855b # custom-2 + .4byte 0x9247c87b # custom-3 + .4byte 0x7b824bab # custom-1 plane B + .4byte 0xfeffc82b # custom-1 plane B + .4byte 0xd8c235fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3f38117b # custom-3 + .4byte 0xd2bec52b # custom-1 plane B + .4byte 0x6f061dfb # custom-3 cv.add/sub.div blocks + .4byte 0xd2b411db # custom-2 bitrev 29:27 + .4byte 0xe4c4ba2b # custom-1 Plane A illegal func7 + .4byte 0xca5c1f7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xb7d693db # custom-2 + .4byte 0xd9284d7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x07a2537b # custom-3 + .4byte 0x2bdf11fb # custom-3 + .4byte 0xc05e422b # custom-1 plane B + .4byte 0xfc454e2b # custom-1 plane B + .4byte 0x3f895afb # custom-3 + .4byte 0x1fc79efb # custom-3 + .4byte 0x7940167b # all the groups of 8 illegal instr in custom-3 + .4byte 0x9bd336fb # custom-3 + .4byte 0x2846c32b # custom-1 plane B + .4byte 0xfcf5075b # custom-2 + .4byte 0x4e1020fb # custom-3 + .4byte 0xe3f1392b # custom-1 Plane A illegal func7 + .4byte 0xeabb62fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x1ab2097b # custom-3 + .4byte 0x70743ffb # custom-3 cv.abs(.h/.b) & below + .4byte 0xe2ebd37b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x32f247fb # custom-3 + .4byte 0x372bccfb # custom-3 + .4byte 0x86f3402b # custom-1 plane B + .4byte 0x22444fab # custom-1 plane B + .4byte 0xf24632fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xfa67e4fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x92b644ab # custom-1 plane B + .4byte 0xfbe585fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3f5b2a7b # custom-3 + .4byte 0xf3b6a87b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xcb5c25fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x9828c9ab # custom-1 plane B + .4byte 0xe27cab7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x70b073fb # custom-3 cv.abs(.h/.b) & below + .4byte 0x2bc0aefb # custom-3 + .4byte 0xb5a343ab # custom-1 plane B + .4byte 0xd3a73ffb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xdfac165b # custom-2 bitrev 29:27 + .4byte 0x3a351efb # custom-3 + .4byte 0xb862115b # custom-2 + .4byte 0xe7f24cab # custom-1 plane B + .4byte 0x7318f9fb # custom-3 cv.abs(.h/.b) & below + .4byte 0xd2bf25fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xe993175b # custom-2 bitrev 29:27 + .4byte 0xf1f80f7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x8ff7935b # custom-2 + .4byte 0xf1c347fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf5b7105b # custom-2 bitrev 29:27 + .4byte 0xbe86392b # custom-1 Plane A illegal func7 + .4byte 0xc1a55b7b # custom-3 cv.shuffle block + .4byte 0x5b7e967b # custom-3 + .4byte 0x2abf442b # custom-1 plane B + .4byte 0xd17ea07b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x6851b72b # custom-1 Plane A illegal func7 + .4byte 0xd9f8a1fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x5ae25e7b # custom-3 + .4byte 0xea21377b # all the groups of 8 illegal instr in custom-3 + .4byte 0xe9c664fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xb01830ab # custom-1 Plane A illegal func7 + .4byte 0xb02ce77b # all the groups of 8 illegal instr in custom-3 + .4byte 0xd247005b # custom-2 + .4byte 0xd138e07b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3ccdc3ab # custom-1 plane B + .4byte 0x5289827b # custom-3 + .4byte 0x26114c7b # custom-3 + .4byte 0x64394eab # custom-1 plane B + .4byte 0xcde78edb # custom-2 + .4byte 0x7dcab4fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x87e91adb # custom-2 + .4byte 0x078c117b # custom-3 + .4byte 0x321ec9ab # custom-1 plane B + .4byte 0x3ee9bbab # custom-1 Plane A illegal func7 + .4byte 0xde02402b # custom-1 plane B + .4byte 0x5e0b0d7b # custom-3 cv.cplxconj block + .4byte 0xe1a917fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x135d8c7b # custom-3 + .4byte 0x46d5c0fb # custom-3 + .4byte 0x5edd302b # custom-1 Plane A illegal func7 + .4byte 0xaa0f3c2b # custom-1 Plane A illegal func7 + .4byte 0xba137efb # custom-3 cv.extract/insert block + .4byte 0x0e0f967b # custom-3 + .4byte 0x92e1aefb # custom-3 + .4byte 0x4e1754fb # custom-3 + .4byte 0x1632d6fb # custom-3 + .4byte 0x279423fb # custom-3 + .4byte 0x6e47f27b # custom-3 cv.add/sub.div blocks + .4byte 0x832f17fb # custom-3 + .4byte 0x836acbab # custom-1 plane B + .4byte 0xa61d4d2b # custom-1 plane B + .4byte 0xb43339ab # custom-1 Plane A illegal func7 + .4byte 0xb10021fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xf1ef65fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3631d6fb # custom-3 + .4byte 0xde82195b # custom-2 bitrev 29:27 + .4byte 0x5ad8ba7b # custom-3 + .4byte 0xdd4a9edb # custom-2 bitrev 29:27 + .4byte 0x7a7fa8fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x5d31c8fb # custom-3 cv.cplxconj block + .4byte 0x3b19517b # custom-3 + .4byte 0x2fe708fb # custom-3 + .4byte 0xfaa91cfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x8b5f837b # custom-3 + .4byte 0x5e10a5fb # custom-3 cv.cplxconj block + .4byte 0xe90e24fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xf880e2fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xe656412b # custom-1 plane B + .4byte 0x067832ab # custom-1 Plane A illegal func7 + .4byte 0xa2e0c6fb # custom-3 + .4byte 0x55abda7b # custom-3 cv.cplxmul block + .4byte 0xf99fbb2b # custom-1 Plane A illegal func7 + .4byte 0x9a59c37b # custom-3 + .4byte 0x1f5130ab # custom-1 Plane A illegal func7 + .4byte 0x57f25ffb # custom-3 cv.cplxmul block + .4byte 0x269b9bfb # custom-3 + .4byte 0x66d5bafb # custom-3 cv.subrotmj block + .4byte 0xee9b36ab # custom-1 Plane A illegal func7 + .4byte 0xdfa6402b # custom-1 plane B + .4byte 0xeedd88db # custom-2 + .4byte 0x0f5933fb # custom-3 + .4byte 0x6ec3d77b # custom-3 cv.add/sub.div blocks + .4byte 0x9cde9ddb # custom-2 + .4byte 0xe86eba2b # custom-1 Plane A illegal func7 + .4byte 0x6e053bab # custom-1 Plane A illegal func7 + .4byte 0x02724d7b # custom-3 + .4byte 0xd28313fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xe15fd87b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xa1bb9bdb # custom-2 + .4byte 0x8bb891fb # custom-3 + .4byte 0x3e4f307b # custom-3 + .4byte 0x7f75eb7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x7db2a2fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x63ab3cfb # custom-3 + .4byte 0x57f7cf2b # custom-1 plane B + .4byte 0xa1da135b # custom-2 + .4byte 0xdfd782db # custom-2 + .4byte 0xdb9b10db # custom-2 bitrev 29:27 + .4byte 0xe327c32b # custom-1 plane B + .4byte 0x3613967b # custom-3 + .4byte 0xb8b963fb # custom-3 cv.extract/insert block + .4byte 0xce3308db # custom-2 + .4byte 0x67f01dfb # custom-3 cv.subrotmj block + .4byte 0xef2d4dab # custom-1 plane B + .4byte 0xea3b362b # custom-1 Plane A illegal func7 + .4byte 0xf21c877b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x4615067b # custom-3 + .4byte 0x1250a9fb # custom-3 + .4byte 0xe061377b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x8b5e43ab # custom-1 plane B + .4byte 0x3ca7b6ab # custom-1 Plane A illegal func7 + .4byte 0xe91cbb7b # all the groups of 8 illegal instr in custom-3 + .4byte 0xa14bb2ab # custom-1 Plane A illegal func7 + .4byte 0x72a6047b # custom-3 cv.abs(.h/.b) & below + .4byte 0xd9fa1bdb # custom-2 bitrev 29:27 + .4byte 0x9a8a9e5b # custom-2 + .4byte 0xdbbb5e7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7d5afe7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x3c45cf2b # custom-1 plane B + .4byte 0xeb642f7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x13f335fb # custom-3 + .4byte 0x6eeec87b # custom-3 cv.add/sub.div blocks + .4byte 0xd848987b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x4ef2b2fb # custom-3 + .4byte 0xb55992db # custom-2 + .4byte 0x1681b9ab # custom-1 Plane A illegal func7 + .4byte 0xf375005b # custom-2 + .4byte 0x3e864c2b # custom-1 plane B + .4byte 0x8e34422b # custom-1 plane B + .4byte 0x1c8d3bab # custom-1 Plane A illegal func7 + .4byte 0x9562b5ab # custom-1 Plane A illegal func7 + .4byte 0x8bffb4fb # custom-3 + .4byte 0xda0b177b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x16f91efb # custom-3 + .4byte 0x9f34b0ab # custom-1 Plane A illegal func7 + .4byte 0x5dbbf0fb # custom-3 cv.cplxconj block + .4byte 0x6dd845ab # custom-1 plane B + .4byte 0xe8a44bfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x7d2290fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x1a6f2dfb # custom-3 + .4byte 0xd3a54b7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x5b38017b # custom-3 + .4byte 0xcbfc815b # custom-2 + .4byte 0xb32d94db # custom-2 + .4byte 0x0ddf4aab # custom-1 plane B + .4byte 0xde5a875b # custom-2 + .4byte 0x0bac287b # custom-3 + .4byte 0x1fa9d7fb # custom-3 + .4byte 0x6b65d87b # custom-3 + .4byte 0x02b02a7b # custom-3 + .4byte 0x37983dab # custom-1 Plane A illegal func7 + .4byte 0x7988ac7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x07314d7b # custom-3 + .4byte 0x4fc6c9fb # custom-3 + .4byte 0x55fefb7b # custom-3 cv.cplxmul block + .4byte 0xf220195b # custom-2 bitrev 29:27 + .4byte 0x33d8017b # custom-3 + .4byte 0xd3ffdafb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xb0d24dfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x224759fb # custom-3 + .4byte 0x82fa07fb # custom-3 + .4byte 0x42b51afb # custom-3 + .4byte 0xa5223c2b # custom-1 Plane A illegal func7 + .4byte 0xf09199db # custom-2 bitrev 29:27 + .4byte 0x7925ecfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x7fab7e7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x5c342cfb # custom-3 cv.cplxconj block + .4byte 0xdafe66fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x70488bfb # custom-3 cv.abs(.h/.b) & below + .4byte 0x17e80dfb # custom-3 + .4byte 0xfa8ad5fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xa22dca2b # custom-1 plane B + .4byte 0xe9060f5b # custom-2 + .4byte 0xeb6948ab # custom-1 plane B + .4byte 0x9ade11fb # custom-3 + .4byte 0x6bcd1bfb # custom-3 + .4byte 0xeff1185b # custom-2 bitrev 29:27 + .4byte 0x6ab04e7b # custom-3 + .4byte 0x0f174e2b # custom-1 plane B + .4byte 0x5333c37b # custom-3 + .4byte 0xe858035b # custom-2 + .4byte 0xb22b905b # custom-2 + .4byte 0x92430f7b # custom-3 + .4byte 0x7ebb9b7b # all the groups of 8 illegal instr in custom-3 + .4byte 0xb1b191fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xbbd8b3ab # custom-1 Plane A illegal func7 + .4byte 0x6c1db9ab # custom-1 Plane A illegal func7 + .4byte 0x7b7d587b # all the groups of 8 illegal instr in custom-3 + .4byte 0x5f13737b # custom-3 cv.cplxconj block + .4byte 0x43d3ad7b # custom-3 + .4byte 0x83a0ccfb # custom-3 + .4byte 0xf3f5015b # custom-2 + .4byte 0xb2e44d2b # custom-1 plane B + .4byte 0xdbadb77b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xa3931d5b # custom-2 + .4byte 0x0e12cfab # custom-1 plane B + .4byte 0x264ed67b # custom-3 + .4byte 0xa46a19db # custom-2 + .4byte 0x366caafb # custom-3 + .4byte 0x70ef247b # custom-3 cv.abs(.h/.b) & below + .4byte 0x46c0352b # legal func7 but non-zero value for rs2 + .4byte 0x9b080c7b # custom-3 + .4byte 0x8b14c5ab # custom-1 plane B + .4byte 0xc4e03e2b # custom-1 Plane A illegal func7 + .4byte 0xb2bd607b # all the groups of 8 illegal instr in custom-3 + .4byte 0xb846492b # custom-1 plane B + .4byte 0x73c92f7b # custom-3 cv.abs(.h/.b) & below + .4byte 0x9d2ebc2b # custom-1 Plane A illegal func7 + .4byte 0xc323b9ab # custom-1 Plane A illegal func7 + .4byte 0xb193f1fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xfb8a195b # custom-2 bitrev 29:27 + .4byte 0x958892db # custom-2 + .4byte 0xe3556bfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x1a64977b # custom-3 + .4byte 0x23ec87fb # custom-3 + .4byte 0x03bd85fb # custom-3 + .4byte 0xb14e0afb # all the groups of 8 illegal instr in custom-3 + .4byte 0xa70c9bdb # custom-2 + .4byte 0xd91f3c2b # custom-1 Plane A illegal func7 + .4byte 0x85e811db # custom-2 + .4byte 0x273739fb # custom-3 + .4byte 0xb01e432b # custom-1 plane B + .4byte 0xc39629fb # custom-3 cv.shuffle block + .4byte 0x7a8bb52b # custom-1 Plane A illegal func7 + .4byte 0x7a94847b # all the groups of 8 illegal instr in custom-3 + .4byte 0xa2d6127b # custom-3 + .4byte 0x4656a4fb # custom-3 + .4byte 0xc967077b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x0390547b # custom-3 + .4byte 0x9df999db # custom-2 + .4byte 0x5ee249ab # custom-1 plane B + .4byte 0xda93427b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x4d6034ab # custom-1 Plane A illegal func7 + .4byte 0x624bc02b # custom-1 plane B + .4byte 0xe18fe2fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x0b9e8e7b # custom-3 + .4byte 0xd4e317db # custom-2 bitrev 29:27 + .4byte 0x476c58fb # custom-3 + .4byte 0x1266d27b # custom-3 + .4byte 0x7ff645fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xd6e2c4ab # custom-1 plane B + .4byte 0xe332b9fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x2b2a86fb # custom-3 + .4byte 0xe36ac92b # custom-1 plane B + .4byte 0x3af98cfb # custom-3 + .4byte 0xaa0298fb # custom-3 + .4byte 0x1f81b27b # custom-3 + .4byte 0x73ecb8fb # custom-3 cv.abs(.h/.b) & below + .4byte 0xca9e5ffb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf3340fdb # custom-2 + .4byte 0x8e8f4b2b # custom-1 plane B + .4byte 0x35fa4b2b # custom-1 plane B + .4byte 0xc115372b # custom-1 Plane A illegal func7 + .4byte 0xe7f081db # custom-2 + .4byte 0x78f7dc7b # all the groups of 8 illegal instr in custom-3 + .4byte 0xccd7055b # custom-2 + .4byte 0x2e08447b # custom-3 + .4byte 0x4358477b # custom-3 + .4byte 0x6fb3a17b # custom-3 cv.add/sub.div blocks + .4byte 0x8293da7b # custom-3 + .4byte 0xa92cbcab # custom-1 Plane A illegal func7 + .4byte 0xeabecbab # custom-1 plane B + .4byte 0xd4dc805b # custom-2 + .4byte 0xc2fe3bfb # custom-3 cv.shuffle block + .4byte 0xd3f60cfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd1c29f5b # custom-2 bitrev 29:27 + .4byte 0x5fa55d7b # custom-3 cv.cplxconj block + .4byte 0xc6733cab # custom-1 Plane A illegal func7 + .4byte 0x9d08c0ab # custom-1 plane B + .4byte 0x42198d7b # custom-3 + .4byte 0xa92f4cab # custom-1 plane B + .4byte 0x98de382b # custom-1 Plane A illegal func7 + .4byte 0x1f84a6fb # custom-3 + .4byte 0xee00175b # custom-2 bitrev 29:27 + .4byte 0x83543c7b # custom-3 + .4byte 0x5575b97b # custom-3 cv.cplxmul block + .4byte 0xb25f5cfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x6368b5ab # legal func7 but non-zero value for rs2 + .4byte 0x5f12b07b # custom-3 cv.cplxconj block + .4byte 0xb02a3c7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x58a8cc2b # custom-1 plane B + .4byte 0xb3a7c87b # all the groups of 8 illegal instr in custom-3 + .4byte 0xbd3f9adb # custom-2 + .4byte 0x7c38d0fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x7024dc7b # custom-3 cv.abs(.h/.b) & below + .4byte 0xd1cb1d5b # custom-2 bitrev 29:27 + .4byte 0x8bd8227b # custom-3 + .4byte 0xae9a965b # custom-2 + .4byte 0x9cf09adb # custom-2 + .4byte 0x26e8b12b # custom-1 Plane A illegal func7 + .4byte 0x84a8115b # custom-2 + .4byte 0x53412e7b # custom-3 + .4byte 0xa3fb38ab # custom-1 Plane A illegal func7 + .4byte 0xf367147b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x16f64b2b # custom-1 plane B + .4byte 0x7203c12b # custom-1 plane B + .4byte 0xd2aa16db # custom-2 bitrev 29:27 + .4byte 0xf8c11bdb # custom-2 bitrev 29:27 + .4byte 0x7b7afd7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x5d8acd2b # custom-1 plane B + .4byte 0x1abd4dfb # custom-3 + .4byte 0x5dfd9b7b # custom-3 cv.cplxconj block + .4byte 0x73aaeffb # custom-3 cv.abs(.h/.b) & below + .4byte 0x4a29b52b # custom-1 Plane A illegal func7 + .4byte 0x66e7c0fb # custom-3 cv.subrotmj block + .4byte 0x5f6617fb # custom-3 cv.cplxconj block + .4byte 0xd28c3c2b # custom-1 Plane A illegal func7 + .4byte 0x5cd965fb # custom-3 cv.cplxconj block + .4byte 0xb98738ab # custom-1 Plane A illegal func7 + .4byte 0x7aaa492b # custom-1 plane B + .4byte 0x8fc29bdb # custom-2 + .4byte 0xa3d4097b # custom-3 + .4byte 0x57d97afb # custom-3 cv.cplxmul block + .4byte 0xfa233bab # custom-1 Plane A illegal func7 + .4byte 0x9a9a5cfb # custom-3 + .4byte 0xf0c9975b # custom-2 bitrev 29:27 + .4byte 0xec65005b # custom-2 + .4byte 0x1322407b # custom-3 + .4byte 0x6fa505fb # custom-3 cv.add/sub.div blocks + .4byte 0xedfe995b # custom-2 bitrev 29:27 + .4byte 0xd5e4312b # custom-1 Plane A illegal func7 + .4byte 0x92283d7b # custom-3 + .4byte 0xf00f9edb # custom-2 bitrev 29:27 + .4byte 0x67f2287b # custom-3 cv.subrotmj block + .4byte 0xd81b1fdb # custom-2 bitrev 29:27 + .4byte 0xf9f2a3fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf10399db # custom-2 bitrev 29:27 + .4byte 0xc0c949fb # custom-3 cv.shuffle block + .4byte 0xbdbb40ab # custom-1 plane B + .4byte 0xd89ccf2b # custom-1 plane B + .4byte 0x86a01c5b # custom-2 + .4byte 0x7b121f7b # all the groups of 8 illegal instr in custom-3 + .4byte 0x4361377b # custom-3 + .4byte 0xe53f915b # custom-2 bitrev 29:27 + .4byte 0xf2dfc6fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xd39e6b7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xc0c835fb # custom-3 cv.shuffle block + .4byte 0x78c4bf2b # custom-1 Plane A illegal func7 + .4byte 0xc92919fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xef01c52b # custom-1 plane B + .4byte 0x630789fb # custom-3 + .4byte 0x56eeb0fb # custom-3 cv.cplxmul block + .4byte 0xd0a6937b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xf6d5cdab # custom-1 plane B + .4byte 0xd88b44ab # custom-1 plane B + .4byte 0xcd410d5b # custom-2 + .4byte 0xfa181a5b # custom-2 bitrev 29:27 + .4byte 0x66aadffb # custom-3 cv.subrotmj block + .4byte 0xf93c02db # custom-2 + .4byte 0x3942482b # custom-1 plane B + .4byte 0x36e03bfb # custom-3 + .4byte 0x4f18332b # custom-1 Plane A illegal func7 + .4byte 0x0f5d05fb # custom-3 + .4byte 0x3e36c1fb # custom-3 + .4byte 0xc961467b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xc98d6a7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x2a52387b # custom-3 + .4byte 0x32815c7b # custom-3 + .4byte 0xa2bf1cdb # custom-2 + .4byte 0x0ec6cf7b # custom-3 + .4byte 0xf15837fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xc129247b # custom-3 cv.shuffle block + .4byte 0x1727a2fb # custom-3 + .4byte 0xea9bf6fb # all the groups of 8 illegal instr in custom-3 + .4byte 0xfb0b4b7b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xb8eb7b7b # custom-3 cv.extract/insert block + .4byte 0x947f9c5b # custom-2 + .4byte 0x4b6a257b # custom-3 + .4byte 0x8b81d8fb # custom-3 + .4byte 0x3afdaafb # custom-3 + .4byte 0x6d390d7b # custom-3 cv.add/sub.div blocks + .4byte 0xcd7388db # custom-2 + .4byte 0x630dc2fb # custom-3 + .4byte 0xe03600db # custom-2 + .4byte 0xb368a6fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x2d19c2ab # custom-1 plane B + .4byte 0xb5b2ccab # custom-1 plane B + .4byte 0xeab580fb # all the groups of 8 illegal instr in custom-3 + .4byte 0x2a49d2fb # custom-3 + .4byte 0x09fc412b # custom-1 plane B + .4byte 0x5c66b5fb # custom-3 cv.cplxconj block + .4byte 0x4bde1e7b # custom-3 + .4byte 0x977818db # custom-2 + .4byte 0x8f3645ab # custom-1 plane B + .4byte 0x17a1482b # custom-1 plane B + .4byte 0x2f87dcfb # custom-3 + .4byte 0xb44145ab # custom-1 plane B + .4byte 0x471f3dfb # custom-3 + .4byte 0x7944347b # all the groups of 8 illegal instr in custom-3 + .4byte 0x66ea097b # custom-3 cv.subrotmj block + .4byte 0x7d648cfb # all the groups of 8 illegal instr in custom-3 + .4byte 0x4b870e7b # custom-3 + .4byte 0xe1f7b0ab # custom-1 Plane A illegal func7 + .4byte 0xb4d7c12b # custom-1 plane B + .4byte 0x71fa42fb # custom-3 cv.abs(.h/.b) & below + .4byte 0x51b7b8ab # legal func7 but non-zero value for rs2 + .4byte 0xfc2fb6ab # custom-1 Plane A illegal func7 + .4byte 0x154f372b # custom-1 Plane A illegal func7 + .4byte 0xb2d1147b # all the groups of 8 illegal instr in custom-3 + .4byte 0x4971ca2b # custom-1 plane B + .4byte 0xec3fb3ab # custom-1 Plane A illegal func7 + .4byte 0xc08c49ab # custom-1 plane B + .4byte 0xb605392b # custom-1 Plane A illegal func7 + .4byte 0xf072acfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0xaf3838ab # custom-1 Plane A illegal func7 + .4byte 0x881b452b # custom-1 plane B + .4byte 0x4ad1337b # custom-3 + .4byte 0xf9c2b87b # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x0f60b1ab # custom-1 Plane A illegal func7 + .4byte 0xd9b85cfb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x3b1ab8fb # custom-3 + .4byte 0xc7588c5b # custom-2 + .4byte 0xdea4baab # custom-1 Plane A illegal func7 + .4byte 0xeb90015b # custom-2 + .4byte 0xf4b40cdb # custom-2 + .4byte 0xa0824fab # custom-1 plane B + .4byte 0xf21257fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x16794e2b # custom-1 plane B + .4byte 0xdd363aab # custom-1 Plane A illegal func7 + .4byte 0x6667f4fb # custom-3 cv.subrotmj block + la x16, test_done + jalr x0, x16, 0 + +#Start: Extracted from riscv_compliance_tests/riscv_test.h +test_done: + csrrci x0,mstatus,0x8 # Clear MSTATUS.MIE to avoid interrupts during test_done + lui s3,print_port>>12 + addi s6,zero,'\n' + sw s6,0(s3) + addi s6,zero,'C' + sw s6,0(s3) + addi s6,zero,'V' + sw s6,0(s3) + addi s6,zero,'3' + sw s6,0(s3) + addi s6,zero,'2' + sw s6,0(s3) + addi s6,zero,' ' + sw s6,0(s3) + addi s6,zero,'D' + sw s6,0(s3) + addi s6,zero,'O' + sw s6,0(s3) + addi s6,zero,'N' + sw s6,0(s3) + addi s6,zero,'E' + sw s6,0(s3) + addi s6,zero,'\n' + sw s6,0(s3) + sw s6,0(s3) + + li s3, test_ret_val + lw s6, test_results /* report result */ + sw s6,0(s3) + + csrrwi x0,mie,0 /* clear mie so that final wfi never awakens */ + wfi /* we are done */ +#End: Extracted from riscv_compliance_tests/riscv_test.h + +write_tohost: + sw gp, tohost, t5 + +_exit: + j write_tohost + +.section .debugger, "ax" +debug_rom: + dret + +.section .debugger_exception, "ax" +debug_exception: + dret + +.section text +instr_end: + nop + +.section .data +.align 6; .global tohost; tohost: .dword 0; +.align 6; .global fromhost; fromhost: .dword 0; +.section .region_0,"aw",@progbits; +region_0: +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.section .region_1,"aw",@progbits; +region_1: +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f +.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f +.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f +.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f +.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f +.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf +.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf +.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff +.section .user_stack,"aw",@progbits; +.align 2 +user_stack_start: +.rept 4999 +.4byte 0x0 +.endr +user_stack_end: +.4byte 0x0 +.align 2 +debugger_stack_start: +.rept 4999 +.4byte 0x0 +.endr +debugger_stack_end: +.4byte 0x0 +.align 2 +kernel_instr_start: +.text +mmode_intr_vector_1: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_2: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_3: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_4: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_5: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_6: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_7: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_8: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_9: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_10: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_11: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_12: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_13: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_14: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_15: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_16: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_17: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_18: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_19: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_20: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_21: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_22: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_23: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_24: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_25: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_26: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_27: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_28: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_29: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_30: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +mmode_intr_vector_31: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x342 # MCAUSE + srli x22, x22, 0x1f + beqz x22, 1f + j mmode_intr_handler + 1: la x16, test_done + jalr x16, 0 + +.align 8 +mtvec_handler: + .option norvc; + j mmode_exception_handler + j mmode_intr_vector_1 + j mmode_intr_vector_2 + j mmode_intr_vector_3 + j mmode_intr_vector_4 + j mmode_intr_vector_5 + j mmode_intr_vector_6 + j mmode_intr_vector_7 + j mmode_intr_vector_8 + j mmode_intr_vector_9 + j mmode_intr_vector_10 + j mmode_intr_vector_11 + j mmode_intr_vector_12 + j mmode_intr_vector_13 + j mmode_intr_vector_14 + j mmode_intr_vector_15 + j mmode_intr_vector_16 + j mmode_intr_vector_17 + j mmode_intr_vector_18 + j mmode_intr_vector_19 + j mmode_intr_vector_20 + j mmode_intr_vector_21 + j mmode_intr_vector_22 + j mmode_intr_vector_23 + j mmode_intr_vector_24 + j mmode_intr_vector_25 + j mmode_intr_vector_26 + j mmode_intr_vector_27 + j mmode_intr_vector_28 + j mmode_intr_vector_29 + j mmode_intr_vector_30 + j mmode_intr_vector_31 + .option rvc; + +mmode_exception_handler: + csrrw x2, 0x340, x2 + add x2, x31, zero + 1: addi x2, x2, -124 + sw x1, 0(x2) + sw x2, 4(x2) + sw x3, 8(x2) + sw x4, 12(x2) + sw x5, 16(x2) + sw x6, 20(x2) + sw x7, 24(x2) + sw x8, 28(x2) + sw x9, 32(x2) + sw x10, 36(x2) + sw x11, 40(x2) + sw x12, 44(x2) + sw x13, 48(x2) + sw x14, 52(x2) + sw x15, 56(x2) + sw x16, 60(x2) + sw x17, 64(x2) + sw x18, 68(x2) + sw x19, 72(x2) + sw x20, 76(x2) + sw x21, 80(x2) + sw x22, 84(x2) + sw x23, 88(x2) + sw x24, 92(x2) + sw x25, 96(x2) + sw x26, 100(x2) + sw x27, 104(x2) + sw x28, 108(x2) + sw x29, 112(x2) + sw x30, 116(x2) + sw x31, 120(x2) + csrr x22, 0x341 # MEPC + csrr x22, 0x342 # MCAUSE + li x21, 0x3 # BREAKPOINT + beq x22, x21, ebreak_handler + li x21, 0x8 # ECALL_UMODE + beq x22, x21, ecall_handler + li x21, 0x9 # ECALL_SMODE + beq x22, x21, ecall_handler + li x21, 0xb # ECALL_MMODE + beq x22, x21, ecall_handler + li x21, 0x1 + beq x22, x21, instr_fault_handler + li x21, 0x5 + beq x22, x21, load_fault_handler + li x21, 0x7 + beq x22, x21, store_fault_handler + li x21, 0xc + beq x22, x21, pt_fault_handler + li x21, 0xd + beq x22, x21, pt_fault_handler + li x21, 0xf + beq x22, x21, pt_fault_handler + li x21, 0x2 # ILLEGAL_INSTRUCTION + beq x22, x21, illegal_instr_handler + csrr x21, 0x343 # MTVAL + 1: la x16, test_done + jalr x1, x16, 0 + +ecall_handler: + csrr x22, 0xcc6 + li x21, 1 + bge x22, x21, 1f + 2: csrr x22, 0xcc2 + li x21, 1 + bge x22, x21, 3f + beqz x0, 4f + 1: csrr x22, 0x341 + csrr x21, 0xcc5 + addi x21, x21, -4 + bne x22, x21, 2b + csrr x21, 0xcc6 + addi x21, x21, -1 + cv.count 1, x21 + csrr x21, 0xcc6 + beqz x21, 4f + csrr x22, 0xcc4 + beqz x0, 5f + 3: csrr x22, 0x341 + csrr x21, 0xcc1 + addi x21, x21, -4 + bne x22, x21, 4f + csrr x21, 0xcc2 + addi x21, x21, -1 + cv.count 0, x21 + csrr x21, 0xcc2 + beqz x21, 4f + csrr x22, 0xcc0 + beqz x0, 5f + 4: csrr x22, 0x341 + addi x22, x22, 4 + 5: csrw 0x341, x22 + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +instr_fault_handler: + li x22, 0 + csrw 0x340, x22 + li x3, 0 + 0: csrr x22, 0x340 + mv x16, x22 + li x16, 0 + beq x22, x16, 1f + 1: csrr x21, 0x3b0 + csrr x24, 0x3a0 + j 17f + 17: li x20, 4 + csrr x22, 0x340 + slli x22, x22, 30 + srli x22, x22, 30 + sub x16, x20, x22 + addi x16, x16, -1 + slli x16, x16, 3 + sll x20, x24, x16 + slli x22, x22, 3 + add x16, x16, x22 + srl x20, x20, x16 + slli x16, x20, 27 + srli x16, x16, 30 + beqz x16, 20f + li x22, 1 + beq x16, x22, 21f + li x22, 2 + beq x16, x22, 25f + li x22, 3 + beq x16, x22, 27f + la x22, test_done + jalr x0, x22, 0 + 18: csrr x22, 0x340 + mv x3, x21 + addi x22, x22, 1 + csrw 0x340, x22 + li x21, 1 + ble x21, x22, 19f + j 0b + 19: la x22, test_done + jalr x0, x22, 0 + 20: j 18b + 21: csrr x22, 0x340 + csrr x16, 0x343 + srli x16, x16, 2 + bnez x22, 22f + bltz x16, 18b + j 23f + 22: bgtu x3, x16, 18b + 23: bleu x21, x16, 18b + andi x16, x20, 128 + beqz x16, 24f + la x22, test_done + jalr x0, x22, 0 + 24: j 29f + 25: csrr x22, 0x343 + srli x22, x22, 2 + slli x16, x21, 2 + srli x16, x16, 2 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 26f + la x22, test_done + jalr x0, x22, 0 + 26: j 29f + 27: csrr x22, 0x343 + srli x22, x22, 2 + srli x22, x22, 0 + slli x22, x22, 0 + slli x16, x21, 2 + srli x16, x16, 2 + srli x16, x16, 0 + slli x16, x16, 0 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 29f + la x22, test_done + jalr x0, x22, 0 + 28: j 29f + 29: ori x20, x20, 4 + csrr x22, 0x340 + li x16, 30 + sll x22, x22, x16 + srl x22, x22, x16 + slli x16, x22, 3 + sll x20, x20, x16 + or x24, x24, x20 + csrr x22, 0x340 + srli x22, x22, 2 + beqz x22, 30f + li x16, 1 + beq x22, x16, 31f + li x16, 2 + beq x22, x16, 32f + li x16, 3 + beq x22, x16, 33f + 30: csrw 0x3a0, x24 + j 34f + 31: csrw 0x3a1, x24 + j 34f + 32: csrw 0x3a2, x24 + j 34f + 33: csrw 0x3a3, x24 + 34: nop + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +load_fault_handler: + li x22, 0 + csrw 0x340, x22 + li x3, 0 + 0: csrr x22, 0x340 + mv x16, x22 + li x16, 0 + beq x22, x16, 1f + 1: csrr x21, 0x3b0 + csrr x24, 0x3a0 + j 17f + 17: li x20, 4 + csrr x22, 0x340 + slli x22, x22, 30 + srli x22, x22, 30 + sub x16, x20, x22 + addi x16, x16, -1 + slli x16, x16, 3 + sll x20, x24, x16 + slli x22, x22, 3 + add x16, x16, x22 + srl x20, x20, x16 + slli x16, x20, 27 + srli x16, x16, 30 + beqz x16, 20f + li x22, 1 + beq x16, x22, 21f + li x22, 2 + beq x16, x22, 25f + li x22, 3 + beq x16, x22, 27f + la x22, test_done + jalr x0, x22, 0 + 18: csrr x22, 0x340 + mv x3, x21 + addi x22, x22, 1 + csrw 0x340, x22 + li x21, 1 + ble x21, x22, 19f + j 0b + 19: la x22, test_done + jalr x0, x22, 0 + 20: j 18b + 21: csrr x22, 0x340 + csrr x16, 0x343 + srli x16, x16, 2 + bnez x22, 22f + bltz x16, 18b + j 23f + 22: bgtu x3, x16, 18b + 23: bleu x21, x16, 18b + andi x16, x20, 128 + beqz x16, 24f + la x22, test_done + jalr x0, x22, 0 + 24: j 29f + 25: csrr x22, 0x343 + srli x22, x22, 2 + slli x16, x21, 2 + srli x16, x16, 2 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 26f + la x22, test_done + jalr x0, x22, 0 + 26: j 29f + 27: csrr x22, 0x343 + srli x22, x22, 2 + srli x22, x22, 0 + slli x22, x22, 0 + slli x16, x21, 2 + srli x16, x16, 2 + srli x16, x16, 0 + slli x16, x16, 0 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 29f + la x22, test_done + jalr x0, x22, 0 + 28: j 29f + 29: ori x20, x20, 1 + csrr x22, 0x340 + li x16, 30 + sll x22, x22, x16 + srl x22, x22, x16 + slli x16, x22, 3 + sll x20, x20, x16 + or x24, x24, x20 + csrr x22, 0x340 + srli x22, x22, 2 + beqz x22, 30f + li x16, 1 + beq x22, x16, 31f + li x16, 2 + beq x22, x16, 32f + li x16, 3 + beq x22, x16, 33f + 30: csrw 0x3a0, x24 + j 34f + 31: csrw 0x3a1, x24 + j 34f + 32: csrw 0x3a2, x24 + j 34f + 33: csrw 0x3a3, x24 + 34: nop + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +store_fault_handler: + li x22, 0 + csrw 0x340, x22 + li x3, 0 + 0: csrr x22, 0x340 + mv x16, x22 + li x16, 0 + beq x22, x16, 1f + 1: csrr x21, 0x3b0 + csrr x24, 0x3a0 + j 17f + 17: li x20, 4 + csrr x22, 0x340 + slli x22, x22, 30 + srli x22, x22, 30 + sub x16, x20, x22 + addi x16, x16, -1 + slli x16, x16, 3 + sll x20, x24, x16 + slli x22, x22, 3 + add x16, x16, x22 + srl x20, x20, x16 + slli x16, x20, 27 + srli x16, x16, 30 + beqz x16, 20f + li x22, 1 + beq x16, x22, 21f + li x22, 2 + beq x16, x22, 25f + li x22, 3 + beq x16, x22, 27f + la x22, test_done + jalr x0, x22, 0 + 18: csrr x22, 0x340 + mv x3, x21 + addi x22, x22, 1 + csrw 0x340, x22 + li x21, 1 + ble x21, x22, 19f + j 0b + 19: la x22, test_done + jalr x0, x22, 0 + 20: j 18b + 21: csrr x22, 0x340 + csrr x16, 0x343 + srli x16, x16, 2 + bnez x22, 22f + bltz x16, 18b + j 23f + 22: bgtu x3, x16, 18b + 23: bleu x21, x16, 18b + andi x16, x20, 128 + beqz x16, 24f + la x22, test_done + jalr x0, x22, 0 + 24: j 29f + 25: csrr x22, 0x343 + srli x22, x22, 2 + slli x16, x21, 2 + srli x16, x16, 2 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 26f + la x22, test_done + jalr x0, x22, 0 + 26: j 29f + 27: csrr x22, 0x343 + srli x22, x22, 2 + srli x22, x22, 0 + slli x22, x22, 0 + slli x16, x21, 2 + srli x16, x16, 2 + srli x16, x16, 0 + slli x16, x16, 0 + bne x22, x16, 18b + andi x16, x20, 128 + beqz x16, 29f + la x22, test_done + jalr x0, x22, 0 + 28: j 29f + 29: ori x20, x20, 3 + csrr x22, 0x340 + li x16, 30 + sll x22, x22, x16 + srl x22, x22, x16 + slli x16, x22, 3 + sll x20, x20, x16 + or x24, x24, x20 + csrr x22, 0x340 + srli x22, x22, 2 + beqz x22, 30f + li x16, 1 + beq x22, x16, 31f + li x16, 2 + beq x22, x16, 32f + li x16, 3 + beq x22, x16, 33f + 30: csrw 0x3a0, x24 + j 34f + 31: csrw 0x3a1, x24 + j 34f + 32: csrw 0x3a2, x24 + j 34f + 33: csrw 0x3a3, x24 + 34: nop + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +ebreak_handler: + csrr x22, 0xcc6 + li x21, 1 + bge x22, x21, 1f + 2: csrr x22, 0xcc2 + li x21, 1 + bge x22, x21, 3f + beqz x0, 4f + 1: csrr x22, 0x341 + csrr x21, 0xcc5 + addi x21, x21, -4 + bne x22, x21, 2b + csrr x21, 0xcc6 + addi x21, x21, -1 + cv.count 1, x21 + csrr x21, 0xcc6 + beqz x21, 4f + csrr x22, 0xcc4 + beqz x0, 5f + 3: csrr x22, 0x341 + csrr x21, 0xcc1 + addi x21, x21, -4 + bne x22, x21, 4f + csrr x21, 0xcc2 + addi x21, x21, -1 + cv.count 0, x21 + csrr x21, 0xcc2 + beqz x21, 4f + csrr x22, 0xcc0 + beqz x0, 5f + 4: csrr x22, 0x341 + addi x22, x22, 4 + 5: csrw 0x341, x22 + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +illegal_instr_handler: + csrr x22, 0xcc6 + li x21, 1 + bge x22, x21, 1f + 2: csrr x22, 0xcc2 + li x21, 1 + bge x22, x21, 3f + beqz x0, 4f + 1: csrr x22, 0x341 + csrr x21, 0xcc5 + addi x21, x21, -4 + bne x22, x21, 2b + csrr x21, 0xcc6 + addi x21, x21, -1 + cv.count 1, x21 + csrr x21, 0xcc6 + beqz x21, 4f + csrr x22, 0xcc4 + beqz x0, 5f + 3: csrr x22, 0x341 + csrr x21, 0xcc1 + addi x21, x21, -4 + bne x22, x21, 4f + csrr x21, 0xcc2 + addi x21, x21, -1 + cv.count 0, x21 + csrr x21, 0xcc2 + beqz x21, 4f + csrr x22, 0xcc0 + beqz x0, 5f + 4: csrr x22, 0x341 + addi x22, x22, 4 + 5: csrw 0x341, x22 + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret + +pt_fault_handler: + nop + +.align 2 +mmode_intr_handler: + csrr x22, 0x300 # MSTATUS; + csrr x22, 0x304 # MIE; + lw x1, 0(x2) + lw x2, 4(x2) + lw x3, 8(x2) + lw x4, 12(x2) + lw x5, 16(x2) + lw x6, 20(x2) + lw x7, 24(x2) + lw x8, 28(x2) + lw x9, 32(x2) + lw x10, 36(x2) + lw x11, 40(x2) + lw x12, 44(x2) + lw x13, 48(x2) + lw x14, 52(x2) + lw x15, 56(x2) + lw x16, 60(x2) + lw x17, 64(x2) + lw x18, 68(x2) + lw x19, 72(x2) + lw x20, 76(x2) + lw x21, 80(x2) + lw x22, 84(x2) + lw x23, 88(x2) + lw x24, 92(x2) + lw x25, 96(x2) + lw x26, 100(x2) + lw x27, 104(x2) + lw x28, 108(x2) + lw x29, 112(x2) + lw x30, 116(x2) + lw x31, 120(x2) + addi x2, x2, 124 + add x31, x2, zero + csrrw x2, 0x340, x2 + mret; + +kernel_instr_end: nop +.section .kernel_stack,"aw",@progbits; +.align 2 +kernel_stack_start: +.rept 3999 +.4byte 0x0 +.endr +kernel_stack_end: +.4byte 0x0 diff --git a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/test.yaml b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/test.yaml new file mode 100644 index 0000000000..8406783652 --- /dev/null +++ b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/test.yaml @@ -0,0 +1,6 @@ +# Test definition YAML for test + +name: custom_opcode_illegal_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Script-generated test to exercise all illegal instruction types in custom opcode spaces for CV32E40Pv2 From 04b9d3849f4522d5e469ee375681b12a35223e35 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Fri, 19 Jan 2024 15:10:11 +0100 Subject: [PATCH 84/97] fixed typo in filename --- ...{custom_ocpode_illegal_test.S => custom_opcode_illegal_test.S} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename cv32e40p/tests/programs/custom/custom_opcode_illegal_test/{custom_ocpode_illegal_test.S => custom_opcode_illegal_test.S} (100%) diff --git a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_ocpode_illegal_test.S b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S similarity index 100% rename from cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_ocpode_illegal_test.S rename to cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S From 21c5419755526e1d5a94d0ff4b51b730c8b98ec8 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Fri, 19 Jan 2024 15:44:02 +0100 Subject: [PATCH 85/97] added custom opcodes test to the pulp regression list --- cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index 0765af4896..e98dd04993 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -84,6 +84,14 @@ tests: cmd: make test COREV=YES TEST=pulp_hardware_loop_interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" num: 1 + custom_opcode_illegal_test: + build: uvmt_cv32e40p + description: custom_opcode_illegal_test directed test, for illegal instructions inside custom-[0-3] opcodes + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=custom_opcode_illegal_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000" + num: 1 + + # pulp_hardware_loop_debug_test: # build: uvmt_cv32e40p # description: pulp_hardware_loop directed test From 01c120127889fcc803357cc01691874e3e6d548a Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Mon, 22 Jan 2024 15:47:10 +0100 Subject: [PATCH 86/97] added missings cases inside custom-3 opcodes (cv.sub) --- .../custom_opcode_illegal_test.S | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S index 9a61ddcf60..3fb665c20f 100644 --- a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S +++ b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S @@ -167,6 +167,7 @@ main: fence.i .4byte 0xca413e0b # cv.elw .4byte 0x21bd452b # custom-1 plane B .4byte 0xe2a0c1fb # custom-3 cv.shuffleI(1-3) blocks + .4byte 0x7659c37b # custom-3 cv.sub.div .4byte 0xfcbf0e5b # custom-2 .4byte 0xbfe4caab # custom-1 plane B .4byte 0x6b3d3eab # custom-1 Plane A illegal func7 @@ -183,6 +184,7 @@ main: fence.i .4byte 0x338b9efb # custom-3 .4byte 0x3202257b # custom-3 .4byte 0x503deaab # custom-1 func3 = 110 + .4byte 0x752290fb # custom-3 cv.sub.div .4byte 0x794274fb # all the groups of 8 illegal instr in custom-3 .4byte 0xed218d5b # custom-2 .4byte 0x54f6957b # custom-3 cv.cplxmul block @@ -196,12 +198,14 @@ main: fence.i .4byte 0x4a4e5b7b # custom-3 .4byte 0xfaba2c7b # custom-3 cv.shuffleI(1-3) blocks .4byte 0xf32bb72b # custom-1 Plane A illegal func7 + .4byte 0x778c567b # custom-3 cv.sub.div .4byte 0xae4fc3ab # custom-1 plane B .4byte 0xeac39a7b # all the groups of 8 illegal instr in custom-3 .4byte 0x93df50fb # custom-3 .4byte 0xf0c65d7b # custom-3 cv.shuffleI(1-3) blocks .4byte 0xaa7c4efb # custom-3 .4byte 0x6bdcbd7b # custom-3 + .4byte 0x76bb9b7b # custom-3 cv.sub.div .4byte 0xd1c442ab # custom-1 plane B .4byte 0x4fad05fb # custom-3 .4byte 0x477c157b # custom-3 @@ -262,6 +266,7 @@ main: fence.i .4byte 0x074dbefb # custom-3 .4byte 0xd0434dfb # custom-3 cv.shuffleI(1-3) blocks .4byte 0x82a022fb # custom-3 + .4byte 0x76283d7b # custom-3 cv.sub.div .4byte 0x1bf15f7b # custom-3 .4byte 0xd1bcd9fb # custom-3 cv.shuffleI(1-3) blocks .4byte 0xd85888fb # custom-3 cv.shuffleI(1-3) blocks @@ -291,6 +296,7 @@ main: fence.i .4byte 0x5e3fe8fb # custom-3 cv.cplxconj block .4byte 0x07afa9fb # custom-3 .4byte 0x6af8227b # custom-3 + .4byte 0x7441847b # custom-3 cv.sub.div .4byte 0x32be3a7b # custom-3 .4byte 0x569f1e7b # custom-3 cv.cplxmul block .4byte 0x1a8fbc7b # custom-3 @@ -300,6 +306,7 @@ main: fence.i .4byte 0x94754e2b # custom-1 plane B .4byte 0x80d54fab # custom-1 plane B .4byte 0xf0ce3d2b # custom-1 Plane A illegal func7 + .4byte 0x75ffb4fb # custom-3 cv.sub.div .4byte 0xcddc00db # custom-2 .4byte 0x42a1beab # legal func7 but non-zero value for rs2 .4byte 0xe7debc2b # custom-1 Plane A illegal func7 @@ -322,6 +329,7 @@ main: fence.i .4byte 0x2211aafb # custom-3 .4byte 0xce96855b # custom-2 .4byte 0x9247c87b # custom-3 + .4byte 0x7467537b # custom-3 cv.sub.div .4byte 0x7b824bab # custom-1 plane B .4byte 0xfeffc82b # custom-1 plane B .4byte 0xd8c235fb # custom-3 cv.shuffleI(1-3) blocks @@ -336,6 +344,7 @@ main: fence.i .4byte 0x07a2537b # custom-3 .4byte 0x2bdf11fb # custom-3 .4byte 0xc05e422b # custom-1 plane B + .4byte 0x76a022fb # custom-3 cv.sub.div .4byte 0xfc454e2b # custom-1 plane B .4byte 0x3f895afb # custom-3 .4byte 0x1fc79efb # custom-3 @@ -370,6 +379,7 @@ main: fence.i .4byte 0x3a351efb # custom-3 .4byte 0xb862115b # custom-2 .4byte 0xe7f24cab # custom-1 plane B + .4byte 0x7738e07b # custom-3 cv.sub.div .4byte 0x7318f9fb # custom-3 cv.abs(.h/.b) & below .4byte 0xd2bf25fb # custom-3 cv.shuffleI(1-3) blocks .4byte 0xe993175b # custom-2 bitrev 29:27 @@ -395,6 +405,7 @@ main: fence.i .4byte 0x5289827b # custom-3 .4byte 0x26114c7b # custom-3 .4byte 0x64394eab # custom-1 plane B + .4byte 0x765675fb # custom-3 cv.sub.div .4byte 0xcde78edb # custom-2 .4byte 0x7dcab4fb # all the groups of 8 illegal instr in custom-3 .4byte 0x87e91adb # custom-2 @@ -412,6 +423,7 @@ main: fence.i .4byte 0x0e0f967b # custom-3 .4byte 0x92e1aefb # custom-3 .4byte 0x4e1754fb # custom-3 + .4byte 0x7694847b # custom-3 cv.sub.div .4byte 0x1632d6fb # custom-3 .4byte 0x279423fb # custom-3 .4byte 0x6e47f27b # custom-3 cv.add/sub.div blocks @@ -456,6 +468,7 @@ main: fence.i .4byte 0xd28313fb # custom-3 cv.shuffleI(1-3) blocks .4byte 0xe15fd87b # custom-3 cv.shuffleI(1-3) blocks .4byte 0xa1bb9bdb # custom-2 + .4byte 0x750f777b # custom-3 cv.sub.div .4byte 0x8bb891fb # custom-3 .4byte 0x3e4f307b # custom-3 .4byte 0x7f75eb7b # all the groups of 8 illegal instr in custom-3 From 56ba26f69e258181a07033c0685a8a9c1a47ad11 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 23 Jan 2024 12:29:27 +0800 Subject: [PATCH 87/97] Prevent post increment store from corrupting the main code Signed-off-by: dd-baoshan --- .../instr_lib/cv32e40p_float_instr_lib.sv | 34 +++++++++++++++---- .../corev_rand_fp_instr_debug/corev-dv.yaml | 2 +- 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv index 6e8dbf1464..7c608cdc0f 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv @@ -1554,6 +1554,7 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b load_store_opt_t load_store_option=NULL; bit use_load_store_w_sp_only; bit use_compress_load_store_only; + bit use_post_inc_load_store; int unsigned num_of_load_store_instr; bit post_fp_src_is_load_dest; int unsigned cnt, cnt_limit=100; @@ -1575,8 +1576,18 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b en_clr_fflags_af_instr = 0; include_load_store_base_sp = 0; // do not reserved SP reserved_rd = new[reserved_rd.size()+1] ({reserved_rd, ZERO}); + use_post_inc_load_store = $urandom_range(1); endfunction: pre_randomize + virtual function void rand_fp_val(output logic [31:0] val); + if (!use_post_inc_load_store) super.rand_fp_val(val); + else begin + void'(std::randomize(val) with { + val[31:23] == 0; val[22:18] != 0; val[17:13] == 0; val[12:8] == 0; val[7:0] == 0; + }); + end + endfunction : rand_fp_val + virtual function void update_current_instr_arg_list(int idx=0); endfunction: update_current_instr_arg_list @@ -1668,8 +1679,8 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b rand_avail_fp_regs[j] inside {[FS0:FA5]}; } }); - avail_gp_regs[i] = rand_avail_gp_regs; - avail_fp_regs[i] = rand_avail_fp_regs; + avail_gp_regs[i] = rand_avail_gp_regs; // override c_avail_gp_regs + avail_fp_regs[i] = rand_avail_fp_regs; // override c_avail_gp_regs end @@ -1717,11 +1728,20 @@ class cv32e40p_fp_op_fwd_instr_w_loadstore_stream extends cv32e40p_float_zfinx_b else exclude_instr = new[8] ({C_LW, C_SW, C_FLW, C_FSW, C_LWSP, C_SWSP, C_FLWSP, C_FSWSP}); if (use_load_store_w_sp_only && !is_zfinx) include_instr = new[4] ({C_LWSP, C_SWSP, C_FLWSP, C_FSWSP}); else if (use_load_store_w_sp_only && is_zfinx) include_instr = new[2] ({C_LWSP, C_SWSP}); - unique case (load_store_option) - STORE_ONLY : include_category = new[2] ({STORE, POST_INC_STORE}); - LOAD_ONLY : include_category = new[2] ({LOAD, POST_INC_LOAD}); - LOAD_STORE : include_category = new[4] ({LOAD, POST_INC_LOAD, STORE, POST_INC_STORE}); - endcase + if (use_post_inc_load_store) begin : INCLUDE_CV_LOAD_STORE + unique case (load_store_option) + STORE_ONLY : include_category = new[2] ({STORE, POST_INC_STORE}); + LOAD_ONLY : include_category = new[2] ({LOAD, POST_INC_LOAD}); + LOAD_STORE : include_category = new[4] ({LOAD, POST_INC_LOAD, STORE, POST_INC_STORE}); + endcase + end + else begin : EXCLUDE_CV_LOAD_STORE + unique case (load_store_option) + STORE_ONLY : include_category = new[1] ({STORE}); + LOAD_ONLY : include_category = new[1] ({LOAD}); + LOAD_STORE : include_category = new[2] ({LOAD, STORE}); + endcase + end // note: include_category cannot mixed with inclue_group else it will have no effect (group override cat) // if (!is_zfinx) include_group = new[4] ({RV32I, RV32C, RV32F, RV32FC}); // else include_group = new[3] ({RV32I, RV32C, RV32ZFINX}); diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml index 2cbfb1fa66..c7c4d3e3b8 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_fp_instr_debug/corev-dv.yaml @@ -10,7 +10,7 @@ description: > plusargs: > +instr_cnt=1000 +num_of_sub_program=0 - +insert_rand_directed_instr_stream=1 + +insert_rand_directed_instr_stream=2 +test_rand_directed_instr_stream_num=8 +directed_instr_0=cv32e40p_constraint_mc_fp_instr_stream,2 +directed_instr_1=cv32e40p_fp_op_fwd_instr_stream,2 From d76e6b68ac9fd4366ee0dee41671e2584ea0ce93 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 23 Jan 2024 19:38:57 +0800 Subject: [PATCH 88/97] To prevent compress store sp from corrupting the main code Signed-off-by: dd-baoshan --- cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv | 1 + cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_instr_lib.sv | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv b/cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv index 514c86a0fb..d62c51aa3b 100644 --- a/cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv +++ b/cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv @@ -415,6 +415,7 @@ class riscv_instr_gen_config extends uvm_object; if (fix_sp) { sp == SP; } + sp dist {SP := 15, [TP:T6] := 1}; // higher change assign to reg x2 sp != tp; !(sp inside {GP, RA, ZERO}); !(tp inside {GP, RA, ZERO}); diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_instr_lib.sv index d5672c9d3b..cf4531a8a4 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_instr_lib.sv @@ -223,6 +223,10 @@ class cv32e40p_xpulp_rand_stream extends cv32e40p_base_instr_stream; if(no_floating_point_instr) riscv_exclude_group = {riscv_exclude_group, RV32F, RV32ZFINX}; + if(cfg.sp != SP) begin // prevent corruption due to sw(sp) + riscv_exclude_instr = {riscv_exclude_instr, C_SWSP, C_FSWSP}; + end + `uvm_info("cv32e40p_xpulp_rand_stream", $sformatf("Total XPULP+RISCV instr gen in test %0d + %0d",num_of_xpulp_instr,num_of_riscv_instr),UVM_HIGH) @@ -285,6 +289,7 @@ class cv32e40p_xpulp_rand_stream extends cv32e40p_base_instr_stream; end endcase + instr_list[$].comment = {$sformatf(" Inserted %0s - idx[%0d]", get_name(), i)}; i++; From 929164e5f08f106903dcbe82a1478d3e0bb24ae4 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Thu, 25 Jan 2024 12:09:08 +0800 Subject: [PATCH 89/97] Improve simtime by reducing hwloop counts; Add directed class for larger hwloop counts Signed-off-by: dd-baoshan --- .../cv32e40p_pulp_hwloop_instr_lib.sv | 164 +++++++++++++----- 1 file changed, 123 insertions(+), 41 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index edc6b1a4b2..91c7db6157 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -73,7 +73,6 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; localparam MAX_HWLOOP_INSTR_GEN = 4095; - rand riscv_reg_t hwloop_avail_regs[]; rand bit[1:0] num_loops_active; rand bit gen_nested_loop; //nested or not-nested hwloop @@ -155,14 +154,43 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; } constraint gen_hwloop_count_c { + solve num_loops_active before gen_nested_loop; + solve gen_nested_loop before hwloop_count, hwloop_counti; + + num_loops_active inside {1,2}; + + if (num_loops_active > 1) { + // num_loops_active == 2 + if (gen_nested_loop) { + // nested loop + foreach (hwloop_count[i]) { + hwloop_count[i] inside {[0:10]}; // max 100*2 + hwloop_counti[i] inside {[0:10]}; + } + } else { + // single loop + foreach (hwloop_count[i]) { + hwloop_count[i] inside {[0:50]}; // max 50*2 + hwloop_counti[i] inside {[0:50]}; + } + } + } else { + // num_loops_active == 1 + if (gen_nested_loop) { + // nested loop + foreach (hwloop_count[i]) { + hwloop_count[i] inside {[0:15]}; // max 225 + hwloop_counti[i] inside {[0:15]}; + } + } else { + // single loop + foreach (hwloop_count[i]) { + hwloop_count[i] inside {[51:100]}; // max 100 + hwloop_counti[i] inside {[51:100]}; + } + } + } // num_loops_active - num_loops_active inside {1,2,3}; - - foreach(hwloop_counti[i]) - hwloop_counti[i] inside {[0:64]}; - - foreach(hwloop_count[i]) - hwloop_count[i] inside {[0:64]}; } constraint num_hwloop_instr_c { @@ -1078,9 +1106,10 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; endclass : cv32e40p_xpulp_hwloop_base_stream -//Class: cv32e40p_xpulp_short_hwloop_stream +//Class: cv32e40p_xpulp_short_hwloop_stream[_directed] //Running with <= 20 instructions in HWLOOP -//Increase Loop Count range to excersize upto 4095 (12-bit) uimmL value +//Increase Loop Count range to excersize upto 1024 +//Cover high Loop Count upto 4096 (12-bit) uimmL value [for _directed] class cv32e40p_xpulp_short_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stream; rand bit loop0_high_count; @@ -1111,39 +1140,26 @@ class cv32e40p_xpulp_short_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stre num_loops_active inside {1}; + // For rs1 32 bit count (long setup), not planned to exercise whole range in these streams + // due to long run times if(gen_nested_loop) { if(loop0_high_count) { - hwloop_counti[0] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; - - hwloop_count[0] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; - - hwloop_counti[1] inside {[0:5]}; - hwloop_count[1] inside {[0:5]}; + hwloop_counti[0] dist {[0:400] := 50, [401:1023] := 5}; + hwloop_count[0] dist {[0:400] := 50, [401:1023] := 5}; + hwloop_counti[1] inside {[0:3]}; + hwloop_count[1] inside {[0:3]}; } else { - hwloop_counti[0] inside {[0:5]}; - hwloop_count[0] inside {[0:5]}; - - hwloop_counti[1] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; - - hwloop_count[1] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; + hwloop_counti[0] inside {[0:3]}; + hwloop_count[0] inside {[0:3]}; + hwloop_counti[1] dist {[0:400] := 50, [401:1023] := 5}; + hwloop_count[1] dist {[0:400] := 50, [401:1023] := 5}; } - - } else { foreach(hwloop_counti[i]) - hwloop_counti[i] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; - - //For rs1 32 bit count, not planned to exercise whole range in these streams - //due to long run times + hwloop_counti[i] dist {[0:400] := 50, [401:1023] := 5}; foreach(hwloop_count[i]) - hwloop_count[i] dist {[0:400] := 10, [401:1023] := 300, [1024:2047] := 150, - [2048:4094] := 50, 4095 := 300}; + hwloop_count[i] dist {[0:400] := 50, [401:1023] := 5}; } } @@ -1233,13 +1249,70 @@ class cv32e40p_xpulp_short_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stre endfunction : post_randomize endclass : cv32e40p_xpulp_short_hwloop_stream +// directed test for higher count/counti +class cv32e40p_xpulp_short_hwloop_stream_directed extends cv32e40p_xpulp_short_hwloop_stream; + + `uvm_object_utils_begin(cv32e40p_xpulp_short_hwloop_stream_directed) + `uvm_field_int(num_loops_active, UVM_DEFAULT) + `uvm_field_int(gen_nested_loop, UVM_DEFAULT) + `uvm_field_sarray_int(use_setup_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_counti_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_starti_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_endi_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_setupi_inst, UVM_DEFAULT) + `uvm_field_sarray_int(hwloop_count, UVM_DEFAULT) + `uvm_field_sarray_int(hwloop_counti, UVM_DEFAULT) + `uvm_field_sarray_int(num_hwloop_instr, UVM_DEFAULT) + `uvm_field_sarray_int(num_hwloop_ctrl_instr, UVM_DEFAULT) + `uvm_field_sarray_int(num_fill_instr_loop_ctrl_to_loop_start, UVM_DEFAULT) + `uvm_field_int(num_fill_instr_in_loop1_till_loop0_setup, UVM_DEFAULT) + `uvm_field_int(setup_l0_before_l1_start, UVM_DEFAULT) + `uvm_field_sarray_int(num_instr_cv_start_to_loop_start_label, UVM_DEFAULT) + `uvm_field_int(loop0_high_count, UVM_DEFAULT) + `uvm_object_utils_end + + constraint gen_hwloop_count_c { + + solve gen_nested_loop, loop0_high_count before hwloop_count, hwloop_counti; + solve gen_nested_loop before loop0_high_count; + + num_loops_active inside {1}; + + // higher count/counti will be covered in directed test to improve simtime + // For rs1 32 bit count (long setup), not planned to exercise whole range in these streams + // due to long run times + if(gen_nested_loop) { + if(loop0_high_count) { + hwloop_counti[0] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_count[0] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_counti[1] inside {[1:2]}; + hwloop_count[1] inside {[1:2]}; + } else { + hwloop_counti[0] inside {[1:2]}; + hwloop_count[0] inside {[1:2]}; + hwloop_counti[1] dist {[1024:4094] := 50, 4095 := 5}; + hwloop_count[1] dist {[1024:4094] := 50, 4095 := 5}; + } + } else { + foreach(hwloop_counti[i]) + hwloop_counti[i] dist {[1024:4094] := 50, 4095 := 5}; + foreach(hwloop_count[i]) + hwloop_count[i] dist {[1024:4094] := 50, 4095 := 5}; + } + } + + function new(string name = "cv32e40p_xpulp_short_hwloop_stream_directed"); + super.new(name); + endfunction : new + +endclass : cv32e40p_xpulp_short_hwloop_stream_directed //Class: cv32e40p_xpulp_long_hwloop_stream //Running with large instruction number in HWLOOP upto 4094 corresponding to 12-bit uimmL for end label. //Max num inside HWLOOP body can be 4094 only as End label is on instruction after last instr of HWLOOP. -//Reduce Loop Count range to upto 50. -class cv32e40p_xpulp_long_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stream; +//Reduce Loop Count range to upto 25. +class cv32e40p_xpulp_long_hwloop_stream extends cv32e40p_xpulp_hwloop_base_stream; // fixme `uvm_object_utils_begin(cv32e40p_xpulp_long_hwloop_stream) `uvm_field_int(num_loops_active, UVM_DEFAULT) @@ -1260,12 +1333,21 @@ class cv32e40p_xpulp_long_hwloop_stream extends cv32e40p_xpulp_hwloop_base_strea `uvm_object_utils_end constraint gen_hwloop_count_c { + solve num_hwloop_instr before hwloop_count, hwloop_counti; num_loops_active inside {1}; - foreach(hwloop_counti[i]) - hwloop_counti[i] inside {[0:25]}; + foreach(hwloop_counti[i]) { + if (num_hwloop_instr[i] < 200) hwloop_counti[i] inside {[0:25]}; + if (num_hwloop_instr[i] >= 200 && num_hwloop_instr[i] < 1000) hwloop_counti[i] inside {[0:10]}; + if (num_hwloop_instr[i] >= 1000 && num_hwloop_instr[i] < 1500) hwloop_counti[i] inside {[0:3]}; + if (num_hwloop_instr[i] >= 1500 ) hwloop_counti[i] inside {[0:2]}; + } - foreach(hwloop_count[i]) - hwloop_count[i] inside {[0:25]}; + foreach(hwloop_count[i]) { + if (num_hwloop_instr[i] < 200) hwloop_count[i] inside {[0:25]}; + if (num_hwloop_instr[i] >= 200 && num_hwloop_instr[i] < 1000) hwloop_count[i] inside {[0:10]}; + if (num_hwloop_instr[i] >= 1000 && num_hwloop_instr[i] < 1500) hwloop_count[i] inside {[0:3]}; + if (num_hwloop_instr[i] >= 1500 ) hwloop_count[i] inside {[0:2]}; + } } From 87d4b0c23e230e74093150c71405c0f90807ca20 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Thu, 25 Jan 2024 12:09:55 +0800 Subject: [PATCH 90/97] Edit and Add cover points for cp_lpcount Signed-off-by: dd-baoshan --- cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index ddc178e558..8f37686830 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -148,10 +148,10 @@ class uvme_rv32x_hwloop_covg # ( } \ cp_lpcount_``LOOP_IDX : coverpoint (csr_hwloop.lp_count[``LOOP_IDX``]) iff (csr_hwloop.lp_start_wb[``LOOP_IDX``] && csr_hwloop.lp_end_wb[``LOOP_IDX``] && csr_hwloop.lp_count_wb[``LOOP_IDX``]) { \ // bins lpcount_zero = {32'h0}; // valid CSR writes to sample should be when lpcount{0/1}.value != 0 \ - bins lpcount_range_low_1 = {[32'h0000_00FF : 32'h0000_0001]}; // 1 <= x <255 \ - bins lpcount_range_low_2 = {[32'h0000_1FFF : 32'h0000_0100]}; // 256 <= x < 4K \ - // bins lpcount_range_middle = {[32'h00FF_FFFF : 32'h0000_1000]}; // 4K <= x < 16M \ - // bins lpcount_range_high = {[32'hFFFF_FFFF : 32'h0100_0000]}; // 16M <= x < 4G \ + bins lpcount_range_low_1 = {[32'h0000_0190 : 32'h0000_0001]}; // count 0-400 \ + bins lpcount_range_low_2 = {[32'h0000_03FF : 32'h0000_0191]}; // count 401-1023 \ + bins lpcount_range_low_3 = {[32'h0000_0FFE : 32'h0000_0400]}; // count 1024-4094 \ + bins lpcount_range_low_4 = {32'h0000_0FFF}; // 4095 \ // higher counts are not covered now to reduced simtime (amend if needed) \ } \ ccp_lpstart_0_lpend_lpcount_``LOOP_IDX : cross cp_lpstart_``LOOP_IDX``, cp_lpend_``LOOP_IDX``, cp_lpcount_``LOOP_IDX`` { \ From 4361141d67a3ae7fcb35432f427c6b10c09cf488 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Thu, 25 Jan 2024 12:11:01 +0800 Subject: [PATCH 91/97] Add hwloop directed tests and regression yaml files Signed-off-by: dd-baoshan --- .../regress/cv32e40pv2_interrupt_debug.yaml | 98 +++++++++++++++- .../cv32e40pv2_interrupt_debug_long.yaml | 44 +++++++ .../cv32e40pv2_interrupt_debug_short.yaml | 111 ++++++++++++++++-- .../corev-dv.yaml | 31 +++++ .../test.yaml | 10 ++ .../corev-dv.yaml | 29 +++++ .../corev_directed_pulp_hwloop_test/test.yaml | 9 ++ 7 files changed, 323 insertions(+), 9 deletions(-) create mode 100644 cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml create mode 100644 cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/test.yaml create mode 100644 cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml create mode 100644 cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/test.yaml diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml index e4c7aaaa5b..576ec53a3f 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug.yaml @@ -187,6 +187,8 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=5000000" test_cfg: gen_rand_int +# list of corev_rand_pulp_hwloop_debug - START + corev_rand_pulp_hwloop_debug: build: uvmt_cv32e40p description: hwloop debug random test @@ -260,7 +262,92 @@ tests: test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en num: 1 - corev_rand_pulp_hwloop_interrupt_test: +# list of corev_rand_pulp_hwloop_debug - END + +# list of corev_directed_pulp_hwloop_debug - START + + corev_directed_pulp_hwloop_debug: + build: uvmt_cv32e40p + description: hwloop debug random test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + num: 1 + + corev_directed_pulp_hwloop_debug_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop ebreak debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop single-step debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_single_step_en + num: 1 + + corev_directed_pulp_hwloop_debug_trigger: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger on instr addr match + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_trigger_basic + num: 1 + + corev_directed_pulp_hwloop_debug_trigger_with_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_trigger_basic,debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_trigger_with_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: debug_trigger_basic,debug_single_step_en + num: 1 + + corev_directed_pulp_hwloop_debug_with_interrupt: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt and debug trigger random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int,debug_trigger_basic + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and single step random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + num: 1 + +# list of corev_directed_pulp_hwloop_debug - END + + corev_rand_pulp_hwloop_test_interrupt: testname: corev_rand_pulp_hwloop_test description: hwloop test with random interrupts build: uvmt_cv32e40p @@ -268,6 +355,15 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=40000000" test_cfg: gen_rand_int + corev_directed_pulp_hwloop_test_with_interrupt: + testname: corev_directed_pulp_hwloop_test + description: hwloop test with random interrupts + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=40000000" + test_cfg: gen_rand_int + num: 1 + corev_rand_pulp_hwloop_exception_single_step_debug: testname: corev_rand_pulp_hwloop_exception description: hwloop exception test with single step debug diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml index 62571b23b7..abacae938b 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml @@ -87,6 +87,8 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000" +# list of corev_rand_pulp_hwloop_debug - START + corev_rand_pulp_hwloop_debug_single_step: testname: corev_rand_pulp_hwloop_debug description: hwloop single-step debug random test @@ -119,6 +121,48 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en +# list of corev_rand_pulp_hwloop_debug - END + +# list of corev_directed_pulp_hwloop_debug - START + + corev_directed_pulp_hwloop_debug_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop single-step debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_single_step_en + num: 1 + + corev_directed_pulp_hwloop_debug_trigger_with_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and single step + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_trigger_basic,debug_single_step_en + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger_and_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and ebreak random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger_single_step: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt, debug trigger and single step random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic,debug_single_step_en + num: 1 + +# list of corev_directed_pulp_hwloop_debug - END + corev_rand_pulp_hwloop_exception_single_step_debug: testname: corev_rand_pulp_hwloop_exception description: hwloop exception test with single step debug diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml index 2a263fcde2..e2a074e6d9 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml @@ -208,20 +208,14 @@ tests: # Add corev_rand_fp_instr_debug similar to corev_rand_pulp_instr_debug with f/zfinx insn included - END +# list of corev_rand_pulp_hwloop_debug - START + corev_rand_pulp_hwloop_debug: build: uvmt_cv32e40p description: hwloop debug random test dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" - corev_rand_pulp_hwloop_test_with_random_debug: - testname: corev_rand_pulp_hwloop_test - description: hwloop random debug req test - build: uvmt_cv32e40p - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" - test_cfg: gen_rand_debug_req - corev_rand_pulp_hwloop_debug_ebreak: testname: corev_rand_pulp_hwloop_debug description: hwloop ebreak debug random test @@ -270,6 +264,83 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int,debug_ebreak +# list of corev_rand_pulp_hwloop_debug - END + +# list of corev_directed_pulp_hwloop_debug - START + + corev_directed_pulp_hwloop_debug: + build: uvmt_cv32e40p + description: hwloop debug random test + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + num: 1 + + corev_directed_pulp_hwloop_debug_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop ebreak debug random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_trigger: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger on instr addr match + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_trigger_basic + num: 1 + + corev_directed_pulp_hwloop_debug_trigger_with_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug random test with debug trigger and ebreak + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: debug_trigger_basic,debug_ebreak + num: 1 + + corev_directed_pulp_hwloop_debug_with_interrupt: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_trigger: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt and debug trigger random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_trigger_basic + num: 1 + + corev_directed_pulp_hwloop_debug_with_int_debug_ebreak: + testname: corev_directed_pulp_hwloop_debug + description: hwloop debug with interrupt and debug ebreak random test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_debug CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int,debug_ebreak + num: 1 + +# list of corev_directed_pulp_hwloop_debug - END + +# list of corev_rand_pulp_hwloop_test - START + + corev_rand_pulp_hwloop_test_with_random_debug: + testname: corev_rand_pulp_hwloop_test + description: hwloop random debug req test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_debug_req + corev_rand_pulp_hwloop_interrupt_test: testname: corev_rand_pulp_hwloop_test description: hwloop test with random interrupts @@ -278,6 +349,30 @@ tests: cmd: make gen_corev-dv test TEST=corev_rand_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" test_cfg: gen_rand_int +# list of corev_rand_pulp_hwloop_test - END + +# list of corev_directed_pulp_hwloop_test - START + + corev_directed_pulp_hwloop_test_with_random_debug: + testname: corev_directed_pulp_hwloop_test + description: hwloop random debug req test + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_debug_req + num: 1 + + corev_directed_pulp_hwloop_test_with_interrupt: + testname: corev_directed_pulp_hwloop_test + description: hwloop test with random interrupts + build: uvmt_cv32e40p + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test TEST=corev_directed_pulp_hwloop_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + test_cfg: gen_rand_int + num: 1 + +# list of corev_directed_pulp_hwloop_test - END + corev_rand_pulp_hwloop_exception_debug_trigger: testname: corev_rand_pulp_hwloop_exception description: hwloop exception test with debug trigger diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml new file mode 100644 index 0000000000..5aff998588 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml @@ -0,0 +1,31 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for corev-dv test generator +# corev-dv generator test +name: corev_directed_pulp_hwloop_debug +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated directed hwloop tests with random debug +plusargs: > + +instr_cnt=200 + +num_of_sub_program=0 + +insert_rand_directed_instr_stream=1 + +test_rand_directed_instr_stream_num=2 + +rand_directed_instr_0=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +rand_directed_instr_1=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +no_fence=1 + +no_data_page=0 + +randomize_csr=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +no_wfi=1 + +no_dret=1 + +enable_misaligned_instr=1 + +enable_ebreak_in_debug_rom=0 + +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 + +gen_debug_section=1 + +is_hwloop_test=1 + +include_xpulp_instr_in_debug_rom diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/test.yaml new file mode 100644 index 0000000000..148f7eed66 --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/test.yaml @@ -0,0 +1,10 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for random hwloop debug test +name: corev_directed_pulp_hwloop_debug +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Random debug in xpulp hwloop stream +plusargs: > + +gen_reduced_rand_dbg_req diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml new file mode 100644 index 0000000000..9589b79c1b --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml @@ -0,0 +1,29 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for corev-dv test generator +# corev-dv generator test +name: corev_directed_pulp_hwloop_test +uvm_test: $(CV_CORE_LC)_instr_base_test +description: > + RISCV-DV generated directed hwloop test +plusargs: > + +instr_cnt=1000 + +num_of_sub_program=0 + +insert_rand_directed_instr_stream=1 + +test_rand_directed_instr_stream_num=2 + +rand_directed_instr_0=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +rand_directed_instr_1=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +no_fence=0 + +no_data_page=0 + +randomize_csr=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +no_wfi=1 + +no_ebreak=1 + +no_dret=1 + +enable_misaligned_instr=0 + +set_dcsr_ebreak=0 + +test_override_riscv_instr_stream=1 + +test_override_riscv_instr_sequence=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/test.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/test.yaml new file mode 100644 index 0000000000..144234739d --- /dev/null +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/test.yaml @@ -0,0 +1,9 @@ +# Copyright 2023 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Test definition YAML for random pulp hwloop test +name: corev_directed_pulp_hwloop_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + xpulp hwloop stream +plusargs: > From a1116610253b6372b8ff3e1a6d65256b2b47a09d Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Fri, 26 Jan 2024 12:09:54 +0800 Subject: [PATCH 92/97] Increase debug rom space Signed-off-by: dd-baoshan --- cv32e40p/bsp/link.ld | 2 +- cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cv32e40p/bsp/link.ld b/cv32e40p/bsp/link.ld index 9ea197dbf5..824b30e2a6 100644 --- a/cv32e40p/bsp/link.ld +++ b/cv32e40p/bsp/link.ld @@ -34,7 +34,7 @@ SECTIONS { KEEP(*(.debugger)); } >dbg - .debugger_exception (0x1A111000): + .debugger_exception (0x1A111600): { KEEP(*(.debugger_exception)); } >dbg diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv index 5edb260838..d647f810d7 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv @@ -306,7 +306,7 @@ class uvme_cv32e40p_cfg_c extends uvma_core_cntrl_cfg_c; (!boot_addr_plusarg_valid) -> (boot_addr == 'h0000_0080); (!mtvec_addr_plusarg_valid) -> (mtvec_addr == 'h0000_0000); (!dm_halt_addr_plusarg_valid) -> (dm_halt_addr == 'h1A11_0800); - (!dm_exception_addr_plusarg_valid) -> (dm_exception_addr == 'h1A11_1000); + (!dm_exception_addr_plusarg_valid) -> (dm_exception_addr == 'h1A11_1600); } constraint agent_cfg_cons { From e1a8ab4826da1a0ba22a006aee4060a77b8f49da Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Fri, 26 Jan 2024 15:49:10 +0100 Subject: [PATCH 93/97] added 3 instructions that are not with OP=custom --- .../custom_opcode_illegal_test.S | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S index 3fb665c20f..c36b6e19ab 100644 --- a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S +++ b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S @@ -87,7 +87,14 @@ main: fence.i addi t2, t0, 337 sll t0, t2, t0 c.nop - # .4byte 0x80fe4c33 # manual: opcode = OP, func7 = 1000000 + + # Manual instructions + .4byte 0x80fe4c33 # manual: opcode = OP, func7 = 1000000 + .4byte 0x00200073 # manual: instr uret, opcode = SYSTEM, [31:20] = h002 + .4byte 0xb1600073 # manual: random [31:20], opcode = SYSTEM + + + # Generated instructions .4byte 0x3e0003fb # custom-3 .4byte 0xb286bdfb # all the groups of 8 illegal instr in custom-3 .4byte 0x5f57cbfb # custom-3 cv.cplxconj block From befb435ee2ba10aa64ad79e1cbb996dfd51aee40 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Sat, 27 Jan 2024 10:56:12 +0800 Subject: [PATCH 94/97] Revert previous changes Signed-off-by: dd-baoshan --- cv32e40p/bsp/link.ld | 2 +- cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cv32e40p/bsp/link.ld b/cv32e40p/bsp/link.ld index 824b30e2a6..9ea197dbf5 100644 --- a/cv32e40p/bsp/link.ld +++ b/cv32e40p/bsp/link.ld @@ -34,7 +34,7 @@ SECTIONS { KEEP(*(.debugger)); } >dbg - .debugger_exception (0x1A111600): + .debugger_exception (0x1A111000): { KEEP(*(.debugger_exception)); } >dbg diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv index d647f810d7..5edb260838 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_cfg.sv @@ -306,7 +306,7 @@ class uvme_cv32e40p_cfg_c extends uvma_core_cntrl_cfg_c; (!boot_addr_plusarg_valid) -> (boot_addr == 'h0000_0080); (!mtvec_addr_plusarg_valid) -> (mtvec_addr == 'h0000_0000); (!dm_halt_addr_plusarg_valid) -> (dm_halt_addr == 'h1A11_0800); - (!dm_exception_addr_plusarg_valid) -> (dm_exception_addr == 'h1A11_1600); + (!dm_exception_addr_plusarg_valid) -> (dm_exception_addr == 'h1A11_1000); } constraint agent_cfg_cons { From 7fcc2e5a166762d46533f51d77d0ef3b81daf72e Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 29 Jan 2024 13:29:46 +0800 Subject: [PATCH 95/97] Fix to handle corner case events - valid exception trap following by debug entry Signed-off-by: dd-baoshan --- .../env/uvme/cov/uvme_rv32x_hwloop_covg.sv | 56 +++++++++++-------- 1 file changed, 33 insertions(+), 23 deletions(-) diff --git a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv index 8f37686830..7e1360e621 100644 --- a/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv @@ -114,6 +114,7 @@ class uvme_rv32x_hwloop_covg # ( bit in_nested_loop0 = 0, in_nested_loop0_d1 = 0; bit is_ebreak = 0, is_ebreakm = 0, is_ecall = 0, is_illegal = 0, is_irq = 0, is_dbg_mode = 0, is_mc_insn = 0; bit is_trap = 0; // trap any period that is redundant due to handling entry which causes data flush + bit has_pending_trap_due2_dbg = 0; // trap pending due to debug mode entry bit enter_hwloop_sub = 0; int enter_hwloop_sub_cnt = 0; bit pending_irq = 0; @@ -919,20 +920,22 @@ class uvme_rv32x_hwloop_covg # ( if (enter_hwloop_sub) begin enter_hwloop_sub_cnt++; if (is_trap && is_dbg_mode && !cv32e40p_rvvi_vif.csr_dcsr_step && enter_hwloop_sub_cnt == 1) begin : TRAP_DUETO_DBG_ENTRY // exception trap and debug are b2b cycles (except debug step) - is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; - prev_pc_rdata_main = prev_pc_rdata_main-4; - for (int j=0; j= 0 && !temp_in_nested_loop0) begin - logic [31:0] discarded_insn; - if (!done_insn_list_capture_main[j]) begin - discarded_insn = insn_list_in_hwloop_main[j].pop_back(); - `uvm_info(_header, $sformatf("DEBUG - HWLOOP_NB_%0d Discarded insn %8h due to Trap triggered by Debug Entery", j, discarded_insn), UVM_DEBUG); - assert (discarded_insn inside {TB_INSTR_ECALL, TB_INSTR_EBREAK, INSN_ILLEGAL}); - end - `uvm_info(_header, $sformatf("DEBUG - HWLOOP_NB_%0d Trap due to Debug Entry detected", j), UVM_DEBUG); - end - end + has_pending_trap_due2_dbg = 1; enter_hwloop_sub = 0; + // todo: remove this when regression is stable + // todo is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0; enter_hwloop_sub = 0; + // todo prev_pc_rdata_main = prev_pc_rdata_main-4; + // todo for (int j=0; j= 0 && !temp_in_nested_loop0) begin + // todo logic [31:0] discarded_insn; + // todo if (!done_insn_list_capture_main[j]) begin + // todo discarded_insn = insn_list_in_hwloop_main[j].pop_back(); + // todo `uvm_info(_header, $sformatf("DEBUG - HWLOOP_NB_%0d Discarded insn %8h due to Trap triggered by Debug Entery", j, discarded_insn), UVM_DEBUG); + // todo assert (discarded_insn inside {TB_INSTR_ECALL, TB_INSTR_EBREAK, INSN_ILLEGAL}); + // todo end + // todo `uvm_info(_header, $sformatf("DEBUG - HWLOOP_NB_%0d Trap due to Debug Entry detected", j), UVM_DEBUG); + // todo end + // todo end end // TRAP_DUETO_DBG_ENTRY else if (pc_is_mtvec_addr() && !is_mcause_irq()) begin : EXCEPTION_ENTRY for (int i=0; i Date: Fri, 2 Feb 2024 10:52:04 +0100 Subject: [PATCH 96/97] simplified specific seed handling as requested --- bin/lib/cv_regression.py | 5 ----- bin/templates/regress_rmdb.j2 | 6 +++--- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/bin/lib/cv_regression.py b/bin/lib/cv_regression.py index d68b00a960..076175f676 100644 --- a/bin/lib/cv_regression.py +++ b/bin/lib/cv_regression.py @@ -96,11 +96,6 @@ def __init__(self, **kwargs): if not hasattr(self, 'log'): self.log = self.name - if hasattr(self, 'seed'): - self.seed_override = 1 - else: - self.seed_override = 0 - def set_cov(self): '''Set the coverage flag based on app setting. If cov already defined (from testlist), then ignore''' diff --git a/bin/templates/regress_rmdb.j2 b/bin/templates/regress_rmdb.j2 index ffc37bfe86..7fa6ce2c77 100644 --- a/bin/templates/regress_rmdb.j2 +++ b/bin/templates/regress_rmdb.j2 @@ -61,8 +61,8 @@ - proc getSeeds { num mode regr_name seed_override seed_value } { - if { $seed_override == "1" } { + proc getSeeds { num mode regr_name seed_value } { + if { $seed_value != "" } { return $seed_value } if {[string equal $mode "FIXED"]} { @@ -186,7 +186,7 @@ [getTestCfgName "(%t_test_cfg:%)"] [getParameterByPriorityYesOrNo "{{iss}}" "{{t.iss}}" "(%build_iss:%)"] [getParameterByPriorityYesOrNo "{{coverage}}" "{{t.cov}}" "(%build_cov:%)"] - [getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)" "{{t.seed_override}}" "{{t.seed}}"] + [getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)" "{{t.seed}}"] [file join "(%results_sim_path%)" "(%t_cfg%)" "{{t.testname}}" "(%t_test_cfg_name:%)" (%t_iteration%)] [getTestName "{{t.testname}}" "(%t_cfg%)" "(%t_test_cfg_name:%)" (%t_iteration%)] [getUCDBFilename "{{t.testname}}" "(%t_test_cfg_name:%)"] From 98ba6361b664c867784fd77fa7fd831cbedc2022 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Fri, 2 Feb 2024 11:03:32 +0100 Subject: [PATCH 97/97] added header --- .../custom_opcode_illegal_test/custom_opcode_illegal_test.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S index c36b6e19ab..3cb4f75898 100644 --- a/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S +++ b/cv32e40p/tests/programs/custom/custom_opcode_illegal_test/custom_opcode_illegal_test.S @@ -1,3 +1,6 @@ +# Copyright 2024 Dolphin Design +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + .include "user_define.h" .section .text.start @@ -92,7 +95,7 @@ main: fence.i .4byte 0x80fe4c33 # manual: opcode = OP, func7 = 1000000 .4byte 0x00200073 # manual: instr uret, opcode = SYSTEM, [31:20] = h002 .4byte 0xb1600073 # manual: random [31:20], opcode = SYSTEM - + # Generated instructions .4byte 0x3e0003fb # custom-3