From ba04d4557be01ae9fa35fbaaf0e1504e49dc29fa Mon Sep 17 00:00:00 2001 From: Mike Thompson Date: Wed, 5 Jul 2023 10:00:18 -0400 Subject: [PATCH 1/3] [skip ci] Version 2 RTD configuration file As per email from RTD: The Read the Docs build system will start requiring a configuration file v2 (.readthedocs.yaml) starting on September 25, 2023. This pull-request has no impact on v2 vs. v1 logical equivalence of the RTL, so the CI is skipped. --- .readthedocs.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 .readthedocs.yaml diff --git a/.readthedocs.yaml b/.readthedocs.yaml new file mode 100644 index 000000000..77f889197 --- /dev/null +++ b/.readthedocs.yaml @@ -0,0 +1,19 @@ +# Configuration file for ReadTheDocs, used to render the CV32E40P User Manual to +# https://docs.openhwgroup.org/projects/cv32e40p-user-manual +# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.1 + +version: 2 + +#build: +# os: "ubuntu-20.04" +# tools: +# python: "3.9" + +# Build from the docs/source directory with Sphinx +sphinx: + configuration: docs/source/conf.py + +# Explicitly set the Python requirements +python: + install: + - requirements: docs/requirements.txt From 9869e2430f60d4c562a50ffe782a76ced878ea25 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 18 Jul 2023 18:55:42 +0200 Subject: [PATCH 2/3] Issue #832 correction Signed-off-by: Pascal Gouedo --- docs/source/instruction_set_extensions.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/instruction_set_extensions.rst b/docs/source/instruction_set_extensions.rst index a0bb95090..edba6a248 100644 --- a/docs/source/instruction_set_extensions.rst +++ b/docs/source/instruction_set_extensions.rst @@ -1324,6 +1324,8 @@ Additionally, there are three modes that influence the second operand: x3[15: 0] = x2[15: 0] + 0xFFEA +And finally for all the SIMD Bit Manipulation instructions, Imm6 is zero-extended. + In the following tables, the index i ranges from 0 to 1 for 16-Bit operations and from 0 to 3 for 8-Bit operations: - The index 0 is 15:0 for 16-Bit operations or 7:0 for 8-Bit operations. From 51b762a1768a285bcab556433854d2ee1bf81f12 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 18 Jul 2023 18:57:27 +0200 Subject: [PATCH 3/3] Hexadecimal values are not supported by GNU binutils. Signed-off-by: Pascal Gouedo --- docs/source/instruction_set_extensions.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/instruction_set_extensions.rst b/docs/source/instruction_set_extensions.rst index edba6a248..d43ac1080 100644 --- a/docs/source/instruction_set_extensions.rst +++ b/docs/source/instruction_set_extensions.rst @@ -1318,7 +1318,7 @@ Additionally, there are three modes that influence the second operand: If not specified, the immediate is sign-extended with the exception of all cv.shuffle* where it is always unsigned. - e.g. cv.add.sci.h x3,x2,0x2A performs: + e.g. cv.add.sci.h x3,x2,-22 performs: x3[31:16] = x2[31:16] + 0xFFEA