CVFPU RTL updates for implementation tools #1001
Labels
Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
PARAM:FPU
Issue depends on the FPU parameter
Type:Enhancement
For feature requests and enhancements
Hi @MikeOpenHWGroup & @davideschiavone
A new CVFPU PR related to implementation tools has been opened.
Even if Synopsys Design Compiler didn't complain up to now, it seems Synopsys Fusion Compiler doesn't like those few SystemVerilog RTL lines.
As this is quite an important point to be implementation tools friendly and this PR is updating 4 of CVFPU files, do we need to import those modifications in CV32E40P before v2 RTL Freeze?
If yes, we have 2 solutions:
In both solutions we can make LEC with or without those modifications and create a new RTL tag if LEC is fine for all 7 configurations.
On verification side this new CV32E40P tag could be used on simulation non-regressions but couldn't be used for RISC-V ISA Formal Verification as it would mean killing 19 days jobs (still running!) and launch them again.
Thank you to give your thought about that.
Pascal.
PS: By the way we already did that kind of updates for Siemens EDA Tessent which didn't like some decoder RTL lines.
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