From 0aec609196d596d0eac7b7661694bab2fe7b7e60 Mon Sep 17 00:00:00 2001 From: Asim Ahsan Date: Wed, 23 Aug 2023 15:33:39 +0500 Subject: [PATCH] Update programmers view (#1259) --- docs/01_cva6_user/Programmer_View.rst | 33 +++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/docs/01_cva6_user/Programmer_View.rst b/docs/01_cva6_user/Programmer_View.rst index 57d6b8c361..fa2f8aebbe 100644 --- a/docs/01_cva6_user/Programmer_View.rst +++ b/docs/01_cva6_user/Programmer_View.rst @@ -24,13 +24,38 @@ RISC-V specifications allow many variations. This chapter provides more details RISC-V Extensions ----------------- -Need for step1 verification. -As CVA6 implements specified RISC-V extensions, this will be a short section, where we mention which extensions are always present or optional. +.. csv-table:: + :widths: auto + :align: left + :header: "Extension", "Optional", "RV32","RV64" + + "I- RV32i Base Integer Instruction Set", "No","✓","✓" + "A - Atomic Instructions", "Yes","✓","✓" + "Zb* - Bit-Manipulation", "Yes","✓","✓" + "C - Compressed Instructions ", "Yes","✓","✓" + "D - Double precsision floating-point", "Yes","✗ ","✓" + "F - Single precsision floating-point", "Yes","✓","✓" + "M - Integer Multiply/Divide", "No","✓","✓" + "Zicount - Performance Counters", "Yes","✓","✓" + "Zicsr - Control and Status Register Instructions", "No","✓","✓" + "Zifencei - Instruction-Fetch Fence", "No","✓","✓" + + RISC-V Privileges ----------------- -Need for step1 verification. -We identify the supported RISC-V privileges +.. csv-table:: + :widths: auto + :align: left + :header: "Mode" + + "M - Machine" + "S - Supervior" + "U - User" + + +Note: The addition of the H Extension is in the process. After that, HS, VS, and VU modes will also be available. + RISC-V Virtual Memory ---------------------