From 4fb073f91c18200c4bcc45d3be4d7629bd34ffbc Mon Sep 17 00:00:00 2001 From: Fatima Saleem <63645133+fatimasaleem@users.noreply.github.com> Date: Tue, 19 Sep 2023 02:39:26 +0500 Subject: [PATCH] [Docs] Adding Zicond in user and requirement specs (#1444) --- docs/01_cva6_user/Programmer_View.rst | 3 +- docs/01_cva6_user/RISCV_Instructions.rst | 38 +++++++++++++++++-- .../cva6_requirements_specification.rst | 6 +++ 3 files changed, 42 insertions(+), 5 deletions(-) diff --git a/docs/01_cva6_user/Programmer_View.rst b/docs/01_cva6_user/Programmer_View.rst index fa2f8aebbe..99b137d14b 100644 --- a/docs/01_cva6_user/Programmer_View.rst +++ b/docs/01_cva6_user/Programmer_View.rst @@ -20,7 +20,7 @@ Programmer’s View ================= -RISC-V specifications allow many variations. This chapter provides more details about RISC-V variants available for the programmer. +RISC-V specifications allow many variations. This chapter provides more details about RISC-V variants available for the programmer. RISC-V Extensions ----------------- @@ -39,6 +39,7 @@ RISC-V Extensions "Zicount - Performance Counters", "Yes","✓","✓" "Zicsr - Control and Status Register Instructions", "No","✓","✓" "Zifencei - Instruction-Fetch Fence", "No","✓","✓" + "Zicond - Integer Conditional Operations(Ratification pending)", "Yes","✓","✓" diff --git a/docs/01_cva6_user/RISCV_Instructions.rst b/docs/01_cva6_user/RISCV_Instructions.rst index 2626e0a8d2..28e7dcf43b 100644 --- a/docs/01_cva6_user/RISCV_Instructions.rst +++ b/docs/01_cva6_user/RISCV_Instructions.rst @@ -31,6 +31,7 @@ In this document, we present ISA (Instruction Set Architecture) for C32VA6_v5.0. * RV32C – Standard Extension for Compressed Instructions * RV32Zicsr – Standard Extension for CSR Instructions * RV32Zifencei – Standard Extension for Instruction-Fetch Fence +* RV32Zicond – Standard Extension for Integer Conditional Operations The base RISC-V ISA has fixed-length 32-bit instructions or 16-bit instructions (the C32VA6_v5.0.0 support C extension), so that must be naturally aligned on 4-byte boundary or 2-byte boundary. The C32VA6_v5.0.0 supports: @@ -451,7 +452,7 @@ Control Transfer Instructions **Format**: beq rs1, rs2, imm[12:1] **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are equal. - + **Pseudocode**: if (x[rs1] == x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 **Invalid values**: NONE @@ -465,7 +466,7 @@ Control Transfer Instructions **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are not equal. **Pseudocode**: if (x[rs1] != x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 - + **Invalid values**: NONE **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. @@ -479,7 +480,7 @@ Control Transfer Instructions **Pseudocode**: if (x[rs1] < x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 **Invalid values**: NONE - + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. - **BLTU**: Branch Less Than Unsigned @@ -513,7 +514,7 @@ Control Transfer Instructions **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using unsigned comparison). **Pseudocode**: if (x[rs1] >=u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 - + **Invalid values**: NONE **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. @@ -1343,6 +1344,35 @@ RV32Zifencei Instruction-Fetch Fence **Exception raised**: NONE +RV32Zicond Integer Conditional operations +------------------------------------------- + +The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destination operand). Using these instructions, branchless sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instructions, or other microarchitectural provisions. + +- **CZERO.EQZ**: Conditional zero, if condition is equal to zero + + **Format**: czero.eqz rd, rs1, rs2 + + **Description**: This instruction behaves as if there is a conditional branch dependent on rs2 being equal to zero, wherein it branches to code that writes a 0 into rd when the equivalence is true, and otherwise falls through to code that moves rs1 into rd. + + **Pseudocode**: if (x[rs2] == 0) x[rd] = 0 else x[rs1] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **CZERO.NEZ**: Conditional zero, if condition is nonzero + + **Format**: czero.nez rd, rs1, rs2 + + **Description**: This instruction behaves as if there is a conditional branch dependent on rs2 being not equal to zero, wherein it branches to code that writes a 0 into rd when the equivalence is true, and otherwise falls through to code that moves rs1 into rd + + **Pseudocode**: if (x[rs2] != 0) x[rd] = 0 else x[rs1] + + **Invalid values**: NONE + + **Exception raised**: NONE + Illegal Instruction --------------------------- diff --git a/docs/02_cva6_requirements/cva6_requirements_specification.rst b/docs/02_cva6_requirements/cva6_requirements_specification.rst index 53f5e0411f..57e15e58ae 100644 --- a/docs/02_cva6_requirements/cva6_requirements_specification.rst +++ b/docs/02_cva6_requirements/cva6_requirements_specification.rst @@ -311,6 +311,12 @@ independent requirements. | | **Zbc** and **Zbs** extensions | | | (bit manipulation), version 1.0. | +-----------------------------------+-----------------------------------+ +| ISA-130 | CVA6 should support as an | +| | **option** the **Zicond** | +| | extension(ratification pending) | +| | version 1.0. | ++-----------------------------------+-----------------------------------+ + Note to ISA-60 and ISA-70: CV64A6 cannot support the D extension with the F extension.