From 50c08657aa93eaa08e4bbb55f05a4e771ee4ff07 Mon Sep 17 00:00:00 2001 From: Jean-Roch Coulon Date: Wed, 19 Jul 2023 14:54:05 +0200 Subject: [PATCH] [HOT FIX] fix vcs_testharness target Signed-off-by: Jean-Roch Coulon --- corev_apu/tb/ariane_tb.sv | 36 ++++++++++++++++++++++++++++++++++++ corev_apu/tb/common/spike.sv | 14 +++++++------- 2 files changed, 43 insertions(+), 7 deletions(-) diff --git a/corev_apu/tb/ariane_tb.sv b/corev_apu/tb/ariane_tb.sv index 6b0803f78f..e6e1aedcd0 100644 --- a/corev_apu/tb/ariane_tb.sv +++ b/corev_apu/tb/ariane_tb.sv @@ -28,6 +28,37 @@ import "DPI-C" context function void read_section(input longint address, inout b module ariane_tb; +// cva6 configuration +// Pipeline +localparam int unsigned NrCommitPorts = cva6_config_pkg::CVA6ConfigNrCommitPorts; +// RVFI +localparam int unsigned IsRVFI = cva6_config_pkg::CVA6ConfigRvfiTrace; +localparam type rvfi_instr_t = struct packed { + logic [ariane_pkg::NRET-1:0] valid; + logic [ariane_pkg::NRET*64-1:0] order; + logic [ariane_pkg::NRET*ariane_pkg::ILEN-1:0] insn; + logic [ariane_pkg::NRET-1:0] trap; + logic [ariane_pkg::NRET*riscv::XLEN-1:0] cause; + logic [ariane_pkg::NRET-1:0] halt; + logic [ariane_pkg::NRET-1:0] intr; + logic [ariane_pkg::NRET*2-1:0] mode; + logic [ariane_pkg::NRET*2-1:0] ixl; + logic [ariane_pkg::NRET*5-1:0] rs1_addr; + logic [ariane_pkg::NRET*5-1:0] rs2_addr; + logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs1_rdata; + logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs2_rdata; + logic [ariane_pkg::NRET*5-1:0] rd_addr; + logic [ariane_pkg::NRET*riscv::XLEN-1:0] rd_wdata; + logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_rdata; + logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_wdata; + logic [ariane_pkg::NRET*riscv::VLEN-1:0] mem_addr; + logic [ariane_pkg::NRET*riscv::PLEN-1:0] mem_paddr; + logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask; + logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask; + logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_rdata; + logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_wdata; +}; + static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); localparam int unsigned CLOCK_PERIOD = 20ns; @@ -47,6 +78,10 @@ module ariane_tb; string binary = ""; ariane_testharness #( + .NrCommitPorts ( NrCommitPorts ), + .IsRVFI ( IsRVFI ), + .rvfi_instr_t ( rvfi_instr_t ), + // .NUM_WORDS ( NUM_WORDS ), .InclSimDTM ( 1'b1 ), .StallRandomOutput ( 1'b1 ), @@ -60,6 +95,7 @@ module ariane_tb; `ifdef SPIKE_TANDEM spike #( + .NrCommitPorts ( NrCommitPorts ), .Size ( NUM_WORDS * 8 ) ) i_spike ( .clk_i, diff --git a/corev_apu/tb/common/spike.sv b/corev_apu/tb/common/spike.sv index ee452cb196..0f414362ee 100644 --- a/corev_apu/tb/common/spike.sv +++ b/corev_apu/tb/common/spike.sv @@ -30,12 +30,12 @@ module spike #( input logic clk_i, input logic rst_ni, input logic clint_tick_i, - input ariane_pkg::scoreboard_entry_t [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_instr_i, - input logic [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_ack_i, - input ariane_pkg::exception_t exception_i, - input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][4:0] waddr_i, - input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][63:0] wdata_i, - input riscv::priv_lvl_t priv_lvl_i + input ariane_pkg::scoreboard_entry_t [NrCommitPorts-1:0] commit_instr_i, + input logic [NrCommitPorts-1:0] commit_ack_i, + input ariane_pkg::exception_t exception_i, + input logic [NrCommitPorts-1:0][4:0] waddr_i, + input logic [NrCommitPorts-1:0][63:0] wdata_i, + input riscv::priv_lvl_t priv_lvl_i ); static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); @@ -57,7 +57,7 @@ module spike #( always_ff @(posedge clk_i) begin if (rst_ni) begin - for (int i = 0; i < ariane_pkg::NR_COMMIT_PORTS; i++) begin + for (int i = 0; i < NrCommitPorts; i++) begin if ((commit_instr_i[i].valid && commit_ack_i[i]) || (commit_instr_i[i].valid && exception_i.valid)) begin spike_tick(commit_log); instr = (commit_log.instr[1:0] != 2'b11) ? {16'b0, commit_log.instr[15:0]} : commit_log.instr;