diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml index 789c2862043..6a18dddc3d0 100644 --- a/.gitlab-ci/expected_synth.yml +++ b/.gitlab-ci/expected_synth.yml @@ -3,4 +3,4 @@ cv64a6_imafdc_sv39: cv32a60x: gates: 160719 cv32a6_embedded: - gates: 127774 + gates: 127613 diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index a18d7078ea2..88b33025432 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -872,7 +872,7 @@ module csr_regfile import ariane_pkg::*; #( // index is specified by the last byte in the address automatic int index = csr_addr.csr_decode.address[3:0]; // check if the entry or the entry above is locked - if (!pmpcfg_q[index].locked && !(pmpcfg_q[index].locked && pmpcfg_q[index].addr_mode == riscv::TOR)) begin + if (!pmpcfg_q[index].locked && !(pmpcfg_q[index+1].locked && pmpcfg_q[index].addr_mode == riscv::TOR)) begin pmpaddr_d[index] = csr_wdata[riscv::PLEN-3:0]; end end diff --git a/core/cva6.sv b/core/cva6.sv index 60be5f6e692..e0f642d2434 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -929,7 +929,7 @@ module cva6 import ariane_pkg::*; #( // Cache Subsystem // ------------------- - if (DCACHE_TYPE == int'(cva6_config_pkg::WT)) begin + if (DCACHE_TYPE == int'(cva6_config_pkg::WT)) begin : gen_cache_wt // this is a cache subsystem that is compatible with OpenPiton wt_cache_subsystem #( .CVA6Cfg ( CVA6ExtendCfg ), @@ -971,7 +971,7 @@ module cva6 import ariane_pkg::*; #( .inval_valid_i ( inval_valid ), .inval_ready_o ( inval_ready ) ); - end else begin + end else begin : gen_cache_wb std_cache_subsystem #( // note: this only works with one cacheable region diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 8edfca4ed29..f3b921bdb03 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -126,22 +126,26 @@ module frontend import ariane_pkg::*; #( .addr_o ( addr ), .instr_o ( instr ) ); + // -------------------- // Branch Prediction // -------------------- // select the right branch prediction result // in case we are serving an unaligned instruction in instr[0] we need to take // the prediction we saved from the previous fetch - assign bht_prediction_shifted[0] = (serving_unaligned) ? bht_q : bht_prediction[addr[0][1]]; - assign btb_prediction_shifted[0] = (serving_unaligned) ? btb_q : btb_prediction[addr[0][1]]; - if (CVA6Cfg.RVC) begin : gen_btb_prediction_shifted + assign bht_prediction_shifted[0] = (serving_unaligned) ? bht_q : bht_prediction[addr[0][$clog2(INSTR_PER_FETCH):1]]; + assign btb_prediction_shifted[0] = (serving_unaligned) ? btb_q : btb_prediction[addr[0][$clog2(INSTR_PER_FETCH):1]]; + // for all other predictions we can use the generated address to index // into the branch prediction data structures for (genvar i = 1; i < INSTR_PER_FETCH; i++) begin : gen_prediction_address assign bht_prediction_shifted[i] = bht_prediction[addr[i][$clog2(INSTR_PER_FETCH):1]]; assign btb_prediction_shifted[i] = btb_prediction[addr[i][$clog2(INSTR_PER_FETCH):1]]; end + end else begin + assign bht_prediction_shifted[0] = (serving_unaligned) ? bht_q : bht_prediction[addr[0][1]]; + assign btb_prediction_shifted[0] = (serving_unaligned) ? btb_q : btb_prediction[addr[0][1]]; end; // for the return address stack it doens't matter as we have the @@ -394,7 +398,7 @@ module frontend import ariane_pkg::*; #( if (ArianeCfg.RASDepth == 0) begin assign ras_predict = '0; - end else begin + end else begin : ras_gen ras #( .DEPTH ( ArianeCfg.RASDepth ) ) i_ras ( @@ -415,7 +419,7 @@ module frontend import ariane_pkg::*; #( if (ArianeCfg.BTBEntries == 0) begin assign btb_prediction = '0; - end else begin + end else begin : btb_gen btb #( .NR_ENTRIES ( ArianeCfg.BTBEntries ) ) i_btb ( @@ -431,7 +435,7 @@ module frontend import ariane_pkg::*; #( if (ArianeCfg.BHTEntries == 0) begin assign bht_prediction = '0; - end else begin + end else begin : bht_gen bht #( .NR_ENTRIES ( ArianeCfg.BHTEntries ) ) i_bht (