diff --git a/docs/04_cv32a65x/tristan/tandem-verification/reference.adoc b/docs/04_cv32a65x/tristan/tandem-verification/reference.adoc
index 7100725f10..35109f8772 100644
--- a/docs/04_cv32a65x/tristan/tandem-verification/reference.adoc
+++ b/docs/04_cv32a65x/tristan/tandem-verification/reference.adoc
@@ -163,9 +163,8 @@ Depending on the prefix used (`/top/cores/` or `/top/core/<hartid>`) the core-le
 |`""`
 |Comma-separated list of Spike extensions to load. +
 Extensions currently supported: +
-+
-* `cvxif`: implements the CV-X-IF interface;
-* `cv32a60x`: implements CSRs specific to `CV32A6`*n*`X` cores.
+- `cvxif`: implements the CV-X-IF interface; +
+- `cv32a60x`: implements CSRs specific to the `CV32A6*X` cores.
 
 |`hide_csrs_based_on_priv`
 |bool
diff --git a/docs/04_cv32a65x/tristan/tandem-verification/tandem.adoc b/docs/04_cv32a65x/tristan/tandem-verification/tandem.adoc
index 2353447441..46a139f5d2 100644
--- a/docs/04_cv32a65x/tristan/tandem-verification/tandem.adoc
+++ b/docs/04_cv32a65x/tristan/tandem-verification/tandem.adoc
@@ -166,7 +166,7 @@ The configuration fragment above instructs the reference model that:
 * all cores:
 ** implement an RV32IMC ISA with extensions `Zicsr`, `Zcb`, `Zba`, `Zbb`, `Zbc` and `Zbs`;
 ** support only the Machine privilege level;
-** implement additional features modeled in Spike custom extensions `cv32a60x` (additional CSRs specific to `cv32a60x` family of cores) and `cvxif` (the CV-X-IF interface);
+** implement additional features modeled in Spike custom extensions `cv32a60x` (additional CSRs specific to `CV32A6*X` family of cores) and `cvxif` (the CV-X-IF interface);
 ** boot from address `0x80000000` (the start address of the DRAM memory);
 ** force the reset value of register `marchid` to value `0x3` (corresponding to the CVA6 architecture);
 ** discard writes into `misa` CSR register by marking all its bits as non-mutable.