From dd4b19285db5dbf729229885f8b93ca6721ec34d Mon Sep 17 00:00:00 2001 From: Florian Zaruba Date: Mon, 11 Sep 2023 15:27:09 +0200 Subject: [PATCH 1/3] Re-factor halt and exception address as parameter --- Bender.yml | 5 -- Flist.ariane | 1 - core/Flist.cva6 | 1 - core/Flist.cva6_gate | 1 - core/csr_regfile.sv | 8 ++-- core/cva6.sv | 4 +- core/frontend/frontend.sv | 2 +- core/include/ariane_dm_pkg.sv | 48 ------------------- core/include/ariane_pkg.sv | 26 ++++++++-- core/include/config_pkg.sv | 12 ++++- core/include/cv64a6_imafdc_sv39_config_pkg.sv | 4 +- util/config_pkg_generator.py | 6 +++ 12 files changed, 50 insertions(+), 68 deletions(-) delete mode 100644 core/include/ariane_dm_pkg.sv diff --git a/Bender.yml b/Bender.yml index c6bee48ddc..f33349737a 100644 --- a/Bender.yml +++ b/Bender.yml @@ -25,7 +25,6 @@ sources: files: - core/include/cv64a6_imafdcv_sv39_config_pkg.sv - core/include/riscv_pkg.sv - - core/include/ariane_dm_pkg.sv - core/include/ariane_pkg.sv - core/mmu_sv39/tlb.sv - core/mmu_sv39/mmu.sv @@ -36,7 +35,6 @@ sources: files: - core/include/cv64a6_imafdc_sv39_config_pkg.sv - core/include/riscv_pkg.sv - - core/include/ariane_dm_pkg.sv - core/include/ariane_pkg.sv - core/mmu_sv39/tlb.sv - core/mmu_sv39/mmu.sv @@ -47,7 +45,6 @@ sources: files: - core/include/cv32a6_imac_sv0_config_pkg.sv - core/include/riscv_pkg.sv - - core/include/ariane_dm_pkg.sv - core/include/ariane_pkg.sv - core/mmu_sv32/cva6_tlb_sv32.sv - core/mmu_sv32/cva6_mmu_sv32.sv @@ -58,7 +55,6 @@ sources: files: - core/include/cv32a6_imac_sv32_config_pkg.sv - core/include/riscv_pkg.sv - - core/include/ariane_dm_pkg.sv - core/include/ariane_pkg.sv - core/mmu_sv32/cva6_tlb_sv32.sv - core/mmu_sv32/cva6_mmu_sv32.sv @@ -69,7 +65,6 @@ sources: files: - core/include/cv32a6_imafc_sv32_config_pkg.sv - core/include/riscv_pkg.sv - - core/include/ariane_dm_pkg.sv - core/include/ariane_pkg.sv - core/mmu_sv32/cva6_tlb_sv32.sv - core/mmu_sv32/cva6_mmu_sv32.sv diff --git a/Flist.ariane b/Flist.ariane index 0d292be5e4..a1f4976382 100644 --- a/Flist.ariane +++ b/Flist.ariane @@ -22,7 +22,6 @@ core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv core/include/riscv_pkg.sv corev_apu/riscv-dbg/src/dm_pkg.sv -core/include/ariane_dm_pkg.sv vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv core/include/ariane_pkg.sv core/include/acc_pkg.sv diff --git a/core/Flist.cva6 b/core/Flist.cva6 index ed029ffb85..d4211c9060 100644 --- a/core/Flist.cva6 +++ b/core/Flist.cva6 @@ -58,7 +58,6 @@ ${CVA6_REPO_DIR}/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mv ${CVA6_REPO_DIR}/core/include/config_pkg.sv ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv -${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv // Note: depends on fpnew_pkg, above ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv diff --git a/core/Flist.cva6_gate b/core/Flist.cva6_gate index e51f2f3f14..fdf0385a22 100644 --- a/core/Flist.cva6_gate +++ b/core/Flist.cva6_gate @@ -11,7 +11,6 @@ ${CVA6_REPO_DIR}/core/include/config_pkg.sv ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv -${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index d2767a8c77..7fb1c47026 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -1037,7 +1037,7 @@ module csr_regfile import ariane_pkg::*; #( endcase // save PC of next this instruction e.g.: the next one to be executed dpc_d = {{riscv::XLEN-riscv::VLEN{pc_i[riscv::VLEN-1]}},pc_i}; - dcsr_d.cause = ariane_dm_pkg::CauseBreakpoint; + dcsr_d.cause = ariane_pkg::CauseBreakpoint; end // we've got a debug request @@ -1050,7 +1050,7 @@ module csr_regfile import ariane_pkg::*; #( // jump to the base address set_debug_pc_o = 1'b1; // save the cause as external debug request - dcsr_d.cause = ariane_dm_pkg::CauseRequest; + dcsr_d.cause = ariane_pkg::CauseRequest; end // single step enable and we just retired an instruction @@ -1072,7 +1072,7 @@ module csr_regfile import ariane_pkg::*; #( end debug_mode_d = 1'b1; set_debug_pc_o = 1'b1; - dcsr_d.cause = ariane_dm_pkg::CauseSingleStep; + dcsr_d.cause = ariane_pkg::CauseSingleStep; end end // go in halt-state again when we encounter an exception @@ -1269,7 +1269,7 @@ module csr_regfile import ariane_pkg::*; #( // if we are in debug mode jump to a specific address if (debug_mode_q) begin - trap_vector_base_o = DmBaseAddress[riscv::VLEN-1:0] + ariane_dm_pkg::ExceptionAddress[riscv::VLEN-1:0]; + trap_vector_base_o = DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.ExceptionAddress[riscv::VLEN-1:0]; end // check if we are in vectored mode, if yes then do BASE + 4 * cause we diff --git a/core/cva6.sv b/core/cva6.sv index 270211554d..818d7459c2 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -190,7 +190,9 @@ module cva6 import ariane_pkg::*; #( bit'(XF8Vec), unsigned'(NrRgprPorts), unsigned'(NrWbPorts), - bit'(EnableAccelerator) + bit'(EnableAccelerator), + CVA6Cfg.HaltAddress, + CVA6Cfg.ExceptionAddress }; diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 399e271ad6..22b69dd6c3 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -354,7 +354,7 @@ module frontend import ariane_pkg::*; #( end // 7. Debug // enter debug on a hard-coded base-address - if (set_debug_pc_i) npc_d = ArianeCfg.DmBaseAddress[riscv::VLEN-1:0] + ariane_dm_pkg::HaltAddress[riscv::VLEN-1:0]; + if (set_debug_pc_i) npc_d = ArianeCfg.DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.HaltAddress[riscv::VLEN-1:0]; icache_dreq_o.vaddr = fetch_address; end diff --git a/core/include/ariane_dm_pkg.sv b/core/include/ariane_dm_pkg.sv deleted file mode 100644 index 4553aeafae..0000000000 --- a/core/include/ariane_dm_pkg.sv +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright 2018 ETH Zurich and University of Bologna. - * Copyright and related rights are licensed under the Solderpad Hardware - * License, Version 0.51 (the “License”); you may not use this file except in - * compliance with the License. You may obtain a copy of the License at - * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law - * or agreed to in writing, software, hardware and materials distributed under - * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR - * CONDITIONS OF ANY KIND, either express or implied. See the License for the - * specific language governing permissions and limitations under the License. - * - * File: dm_pkg.sv - * Author: Florian Zaruba - * Date: 30.6.2018 - * - * Description: Debug-module package, contains common system definitions. - * - */ - -package ariane_dm_pkg; - - // amount of data count registers implemented - localparam logic [3:0] DataCount = 4'h2; - - // address where data0-15 is shadowed or if shadowed in a CSR - // address of the first CSR used for shadowing the data - localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here - - typedef struct packed { - logic [31:24] zero1; - logic [23:20] nscratch; - logic [19:17] zero0; - logic dataaccess; - logic [15:12] datasize; - logic [11:0] dataaddr; - } hartinfo_t; - - // address to which a hart should jump when it was requested to halt - localparam logic [63:0] HaltAddress = 64'h800; - localparam logic [63:0] ResumeAddress = HaltAddress + 4; - localparam logic [63:0] ExceptionAddress = HaltAddress + 8; - - // debug causes - localparam logic [2:0] CauseBreakpoint = 3'h1; - localparam logic [2:0] CauseTrigger = 3'h2; - localparam logic [2:0] CauseRequest = 3'h3; - localparam logic [2:0] CauseSingleStep = 3'h4; - -endpackage : ariane_dm_pkg diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 083f937e10..6abfe48a29 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -166,13 +166,33 @@ package ariane_pkg; localparam NR_RGPR_PORTS = 2; // static debug hartinfo - localparam ariane_dm_pkg::hartinfo_t DebugHartInfo = '{ + // debug causes + localparam logic [2:0] CauseBreakpoint = 3'h1; + localparam logic [2:0] CauseTrigger = 3'h2; + localparam logic [2:0] CauseRequest = 3'h3; + localparam logic [2:0] CauseSingleStep = 3'h4; + // amount of data count registers implemented + localparam logic [3:0] DataCount = 4'h2; + + // address where data0-15 is shadowed or if shadowed in a CSR + // address of the first CSR used for shadowing the data + localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here + typedef struct packed { + logic [31:24] zero1; + logic [23:20] nscratch; + logic [19:17] zero0; + logic dataaccess; + logic [15:12] datasize; + logic [11:0] dataaddr; + } hartinfo_t; + + localparam hartinfo_t DebugHartInfo = '{ zero1: '0, nscratch: 2, // Debug module needs at least two scratch regs zero0: '0, dataaccess: 1'b1, // data registers are memory mapped in the debugger - datasize: ariane_dm_pkg::DataCount, - dataaddr: ariane_dm_pkg::DataAddr + datasize: DataCount, + dataaddr: DataAddr }; // enables a commit log which matches spikes commit log format for easier trace comparison diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 565ff1fb5c..4390986a9c 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -44,6 +44,10 @@ package config_pkg; int unsigned NrRgprPorts; int unsigned NrWbPorts; bit EnableAccelerator; + // Debug Module + // address to which a hart should jump when it was requested to halt + logic [63:0] HaltAddress; + logic [63:0] ExceptionAddress; } cva6_cfg_t; localparam cva6_cfg_t cva6_cfg_default = { @@ -74,7 +78,9 @@ package config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; localparam cva6_cfg_t cva6_cfg_empty = { @@ -105,7 +111,9 @@ package config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h0, // HaltAddress + 64'h0 // ExceptionAddress } ; diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index 551900c747..aa240f1902 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress // EnableAccelerator } ; endpackage diff --git a/util/config_pkg_generator.py b/util/config_pkg_generator.py index c7a1f3ff2b..aabdbde000 100644 --- a/util/config_pkg_generator.py +++ b/util/config_pkg_generator.py @@ -103,6 +103,10 @@ def setup_parser_config_generator(): help="Cache type (WB or WT)") parser.add_argument("--MmuPresent", type=int, default=None, choices=[0, 1], help="Use an MMU ? 1 : enable, 0 : disable") + parser.add_argument("--HaltAddress", type=int, default=0x804, + help="Address which the core should jump in case of a debug request.") + parser.add_argument("--ExceptionAddress", type=int, default=0x808, + help="Address which the core should jump in case of an exception during debug mode.") parser.add_argument("--RvfiTrace", type=int, default=None, choices=[0, 1], help="Output an RVFI trace ? 1 : enable, 0 : disable") return parser @@ -156,6 +160,8 @@ def setup_parser_config_generator(): "MmuPresent": "CVA6ConfigMmuPresent", # Ignored parameters "ignored": "CVA6ConfigRvfiTrace", + "HaltAddress": "CVA6HaltAddress", + "ExceptionAddress": "CVA6ExceptionAddress", } MapParametersToArgs = {i:k for k, i in MapArgsToParameter.items()} #reverse map From 1c3bde4908939ab5807b941d7a42803c164fc66a Mon Sep 17 00:00:00 2001 From: Florian Zaruba Date: Wed, 13 Sep 2023 08:22:24 +0200 Subject: [PATCH 2/3] Add `HaltAddress` and `ExceptionAddress` to all configs --- core/include/cv32a60x_config_pkg.sv | 4 +++- core/include/cv32a6_embedded_config_pkg.sv | 4 +++- core/include/cv32a6_ima_sv32_fpga_config_pkg.sv | 4 +++- core/include/cv32a6_imac_sv0_config_pkg.sv | 4 +++- core/include/cv32a6_imac_sv32_config_pkg.sv | 4 +++- core/include/cv32a6_imafc_sv32_config_pkg.sv | 4 +++- core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv | 4 +++- core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 4 +++- core/include/cv64a6_imafdcv_sv39_config_pkg.sv | 4 +++- 9 files changed, 27 insertions(+), 9 deletions(-) diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index eb1e9d8afd..bd478f60c4 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_embedded_config_pkg.sv b/core/include/cv32a6_embedded_config_pkg.sv index 0a845f2aa6..afd84b22bc 100644 --- a/core/include/cv32a6_embedded_config_pkg.sv +++ b/core/include/cv32a6_embedded_config_pkg.sv @@ -102,7 +102,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 451f774604..6fc140d91f 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 52f645e0f4..81d493047e 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 4c6c98926c..2b36b7572b 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 71dab67b58..67d87c5e91 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index b24360fa9a..11d497f045 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 412fe2880b..9fd8921e69 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index a76a54cb3a..ee7da96375 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -103,7 +103,9 @@ package cva6_config_pkg; bit'(0), // XF8Vec unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts - bit'(0) // EnableAccelerator + bit'(0), // EnableAccelerator + 64'h804, // HaltAddress + 64'h808 // ExceptionAddress } ; endpackage From 272d417821fae5cab304d9fe79495e2efddeb0e5 Mon Sep 17 00:00:00 2001 From: Florian Zaruba Date: Wed, 13 Sep 2023 11:48:18 +0200 Subject: [PATCH 3/3] Fix HaltAddress --- core/include/config_pkg.sv | 2 +- core/include/cv32a60x_config_pkg.sv | 2 +- core/include/cv32a6_embedded_config_pkg.sv | 2 +- core/include/cv32a6_ima_sv32_fpga_config_pkg.sv | 2 +- core/include/cv32a6_imac_sv0_config_pkg.sv | 2 +- core/include/cv32a6_imac_sv32_config_pkg.sv | 2 +- core/include/cv32a6_imafc_sv32_config_pkg.sv | 2 +- core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv | 2 +- core/include/cv64a6_imafdc_sv39_config_pkg.sv | 2 +- core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 2 +- core/include/cv64a6_imafdcv_sv39_config_pkg.sv | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 4390986a9c..3be517913b 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -79,7 +79,7 @@ package config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ; diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index bd478f60c4..2d2660cb9f 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -104,7 +104,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ; diff --git a/core/include/cv32a6_embedded_config_pkg.sv b/core/include/cv32a6_embedded_config_pkg.sv index afd84b22bc..f52645a02a 100644 --- a/core/include/cv32a6_embedded_config_pkg.sv +++ b/core/include/cv32a6_embedded_config_pkg.sv @@ -103,7 +103,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ; diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 6fc140d91f..8ed9997614 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -104,7 +104,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ; diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 81d493047e..fd4b55b45e 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -104,7 +104,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ; diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 2b36b7572b..eabb27793c 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -104,7 +104,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ; diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 67d87c5e91..da9d356572 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -104,7 +104,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ; diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 11d497f045..167d501a6a 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -104,7 +104,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ; diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index aa240f1902..ea06072ef2 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -104,7 +104,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress // EnableAccelerator } ; diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 9fd8921e69..0a8546a6c4 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -104,7 +104,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ; diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index ee7da96375..d32c1818fa 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -104,7 +104,7 @@ package cva6_config_pkg; unsigned'(0), // NrRgprPorts unsigned'(0), // NrWbPorts bit'(0), // EnableAccelerator - 64'h804, // HaltAddress + 64'h800, // HaltAddress 64'h808 // ExceptionAddress } ;