diff --git a/verif/tb/uvmt/uvmt_cva6_axi_assert.sv b/verif/tb/uvmt/uvmt_cva6_axi_assert.sv
index e2758f37dc..ab3472d5d6 100644
--- a/verif/tb/uvmt/uvmt_cva6_axi_assert.sv
+++ b/verif/tb/uvmt/uvmt_cva6_axi_assert.sv
@@ -18,42 +18,42 @@ module  uvmt_cva6_axi_assert#(int HPDCache=2)
 
    //check if the CVA6 identify read transaction with an ID equal to 0 or 1
    property AXI4_CVA6_ARID;
-      @(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_id == 0 || axi_assert_if.ar_id == 1 || (axi_assert_if.ar_id == 3 && axi_assert_if.ar_lock == 1);
+      @(posedge axi_assert_if.clk && (HPDCache != 2) && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_id == 0 || axi_assert_if.ar_id == 1 || (axi_assert_if.ar_id == 3 && axi_assert_if.ar_lock == 1);
    endproperty
 
    //check if the CVA6 identify write transaction with an ID equal to 0 or 1
    property AXI4_CVA6_AWID;
-      @(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_id == 1 || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_atop != 0) || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_lock == 1);
+      @(posedge axi_assert_if.clk && (HPDCache != 2) && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_id == 1 || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_atop != 0) || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_lock == 1);
    endproperty
 
    //Check if user-defined extension for read address channel is equal to 0b00
    property AXI4_CVA6_ARUSER;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_user == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_user == 0;
    endproperty
 
    //Check if user-defined extension for write address channel is equal to 0b00
    property AXI4_CVA6_AWUSER;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_user == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_user == 0;
    endproperty
 
    //Check if Quality of Service identifier for write transaction is equal to 0b0000
    property AXI4_CVA6_AWQOS;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_qos == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_qos == 0;
    endproperty
 
    //Check if Quality of Service identifier for read transaction is equal to 0b0000
    property AXI4_CVA6_ARQOS;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_qos == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_qos == 0;
    endproperty
 
    //Check if Region indicator for write transaction is equal to 0b0000
    property AXI4_CVA6_AWREGION;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_region == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_region == 0;
    endproperty
 
    //Check if Region indicator for read transaction is equal to 0b0000
    property AXI4_CVA6_ARREGION;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_region == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_region == 0;
    endproperty
 
    //Check if AWCACHE is always equal to 0b0000
@@ -63,42 +63,42 @@ module  uvmt_cva6_axi_assert#(int HPDCache=2)
 
    //Check if ARCACHE is always equal to 0b0000
    property AXI4_CVA6_ARCACHE;
-      @(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_cache == 2;
+      @(posedge axi_assert_if.clk && (HPDCache != 2) && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_cache == 2;
    endproperty
 
    //Check if Protection attributes for write transaction always take the 0b000
    property AXI4_CVA6_AWPROT;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_prot == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_prot == 0;
    endproperty
 
    //Check if Protection attributes for read transaction always take the 0b000
    property AXI4_CVA6_ARPROT;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_prot == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_prot == 0;
    endproperty
 
    //Check if all write transaction performed by CVA6 are of type INCR
    property AXI4_CVA6_AWBURST;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_burst == 1;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_burst == 1;
    endproperty
 
    //Check if all read transaction performed by CVA6 are of type INCR
    property AXI4_CVA6_ARBURST;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_burst == 1;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_burst == 1;
    endproperty
 
    //Check if all write transaction performed by CVA6 are equal to 0
    property AXI4_CVA6_AWLEN;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_len == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_len == 0;
    endproperty
 
    //Check if all Read transaction performed by CVA6 are equal to 0 or 1
    property AXI4_CVA6_ARLEN;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_len == 0 || axi_assert_if.ar_len == 1;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_len == 0 || axi_assert_if.ar_len == 1;
    endproperty
 
    //Check if all Write transaction performed by CVA6 are of type Non atomic, AtomicLoad or AtomicSwap
    property AXI4_CVA6_AWATOP;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> (axi_assert_if.aw_atop[5:4] == 0 || axi_assert_if.aw_atop[5:4] == 2 || axi_assert_if.aw_atop[5:4] == 3) && axi_assert_if.aw_atop[3] == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> (axi_assert_if.aw_atop[5:4] == 0 || axi_assert_if.aw_atop[5:4] == 2 || axi_assert_if.aw_atop[5:4] == 3) && axi_assert_if.aw_atop[3] == 0;
    endproperty
 
 /********************************************** Assert Property ******************************************************/
diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv
index 39da6022d7..79c2de73d7 100644
--- a/verif/tb/uvmt/uvmt_cva6_tb.sv
+++ b/verif/tb/uvmt/uvmt_cva6_tb.sv
@@ -350,17 +350,28 @@ module uvmt_cva6_tb;
     * Test bench entry point.
     */
    initial begin : test_bench_entry_point
+     bit axi_assert_on;
 
      // Specify time format for simulation (units_number, precision_number, suffix_string, minimum_field_width)
      $timeformat(-9, 3, " ns", 8);
 
-     axi_if.aw_assertion_enabled      = 1;
-     axi_if.w_assertion_enabled       = 1;
-     axi_if.b_assertion_enabled       = 1;
-     axi_if.ar_assertion_enabled      = 1;
-     axi_if.r_assertion_enabled       = 1;
-     axi_if.axi_assertion_enabled     = 1;
-     axi_if.axi_amo_assertion_enabled = 1;
+     if($value$plusargs("uvmt_set_axi_assert_cfg=%0d", axi_assert_on)) begin
+        axi_if.aw_assertion_enabled      = axi_assert_on;
+        axi_if.w_assertion_enabled       = axi_assert_on;
+        axi_if.b_assertion_enabled       = axi_assert_on;
+        axi_if.ar_assertion_enabled      = axi_assert_on;
+        axi_if.r_assertion_enabled       = axi_assert_on;
+        axi_if.axi_assertion_enabled     = axi_assert_on;
+        axi_if.axi_amo_assertion_enabled = axi_assert_on;
+     end else begin
+        axi_if.aw_assertion_enabled      = 1;
+        axi_if.w_assertion_enabled       = 1;
+        axi_if.b_assertion_enabled       = 1;
+        axi_if.ar_assertion_enabled      = 1;
+        axi_if.r_assertion_enabled       = 1;
+        axi_if.axi_assertion_enabled     = 1;
+        axi_if.axi_amo_assertion_enabled = 1;
+     end
 
      // Add interfaces handles to uvm_config_db
      uvm_config_db#(virtual uvma_clknrst_if )::set(.cntxt(null), .inst_name("*.env.clknrst_agent"), .field_name("vif"),       .value(clknrst_if));