From 48d32b4625667b1686c87f6b70ae965275fb3dbe Mon Sep 17 00:00:00 2001 From: Christian Herber Date: Thu, 7 Sep 2023 10:41:21 +0200 Subject: [PATCH 1/3] Fixed wrong OBI version referenced - substituted with explicit reference - removed the redundanst section on memory interfaces --- doc/01_specification/index.rst | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/doc/01_specification/index.rst b/doc/01_specification/index.rst index 36e38b6583..60f36e151c 100644 --- a/doc/01_specification/index.rst +++ b/doc/01_specification/index.rst @@ -91,7 +91,8 @@ As displayed in the above figure, the IP comprises: - The CV32E20 processor core with dual 32-bit Harvard memory interfaces - - Instruction fetch bus, data load/store bus + - Instruction fetch bus, data load/store bus. Protocol is protocol is + [OPENHW-OBI]_ - Support for both RV32I (32 x 32b GPRs) and RV32E (16 x 32b GPRs) @@ -100,11 +101,6 @@ As displayed in the above figure, the IP comprises: - Support for basic set of Configuration & Status Registers (CSRs) -- Dual 32-bit Harvard memory interfaces - - - Supported core protocol is OBI_1_v1.2 (Open Bus Interface) - definition - At the coreplex design level, the following functions are added to the processor core: From 4eab586b790444fc3f58d216bf9eb862069a6c09 Mon Sep 17 00:00:00 2001 From: Christian Herber Date: Thu, 7 Sep 2023 10:41:59 +0200 Subject: [PATCH 2/3] Removing interrupt controller from coreplex components - CLINT is completely implemented at the core level --- doc/01_specification/index.rst | 2 -- 1 file changed, 2 deletions(-) diff --git a/doc/01_specification/index.rst b/doc/01_specification/index.rst index 60f36e151c..c7477a0184 100644 --- a/doc/01_specification/index.rst +++ b/doc/01_specification/index.rst @@ -106,8 +106,6 @@ processor core: - Debug module including the :term:`DTM` -- Interrupt module - - System bus wrappers to convert from OBI [OPENHW-OBI]_ to the :term:`AMBA`-:term:`AHB` (Advanced Microcontroller Bus Architecture, Advanced High-performance Bus) protocol [AMBA-AHB]_ From c63271c5cf55de8a3c0a28b1b41966fb2e4fbef7 Mon Sep 17 00:00:00 2001 From: Christian Herber Date: Thu, 7 Sep 2023 10:48:52 +0200 Subject: [PATCH 3/3] Removing requirement to encode supervisor mode in AHB as supervisor mode is not supported --- doc/01_specification/index.rst | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/doc/01_specification/index.rst b/doc/01_specification/index.rst index c7477a0184..4c113a5abb 100644 --- a/doc/01_specification/index.rst +++ b/doc/01_specification/index.rst @@ -242,7 +242,7 @@ Operating modes (Privilege Levels) | PVL-10 | CV32E20 shall support only little-endian memory | | | organizations. | +--------+--------------------------------------------------------------+ -| PVL-20 | CV32E20 shall support **machine** and **unprivileged** | +| PVL-20 | CV32E20 shall support **machine** and **user** | | | privilege modes. | +--------+--------------------------------------------------------------+ | PVL-30 | CV32E20 shall export the CPU's operating mode as an address | @@ -388,13 +388,13 @@ The implemented set of CSRs includes the following registers: | | | | | *0xb8c mpmcounter12h // HPM-20: upper word of mpmcounter12* | | | | -| | 0xc00 cycle // unprivileged mode cycle, lower 32b | +| | 0xc00 cycle // user mode cycle, lower 32b | | | | -| | 0xc02 instret // unprivileged mode instret, lower 32b | +| | 0xc02 instret // user mode instret, lower 32b | | | | -| | 0xc80 cycleh // unprivileged mode cycle, upper 32b | +| | 0xc80 cycleh // user mode cycle, upper 32b | | | | -| | 0xc82 instreth // unprivileged mode instret, upper 32b | +| | 0xc82 instreth // user mode instret, upper 32b | | | | | | 0xf11 mvendorid // machine vendor ID | | | | @@ -436,13 +436,13 @@ lower order 32-bit register. | | | | | 0xb82 minstreth // machine mode instret, upper 32 bits | | | | -| | 0xc00 cycle // unprivileged mode cycle, lower 32b | +| | 0xc00 cycle // user mode cycle, lower 32b | | | | -| | 0xc02 instret // unprivileged mode instret, lower 32b | +| | 0xc02 instret // user mode instret, lower 32b | | | | -| | 0xc80 cycleh // unprivileged mode cycle, upper 32b | +| | 0xc80 cycleh // user mode cycle, upper 32b | | | | -| | 0xc82 instreth // unprivileged mode instret, upper 32b | +| | 0xc82 instreth // user mode instret, upper 32b | +--------+---------------------------------------------------------------+ | HPM-20 | CV32E20 should support 10 optional event counters | | | (mhpmcounterX{h}) and their associated event selector | @@ -661,9 +661,6 @@ CV32E20 coreplex memory bus | | if E20 core mode = user, then {HNONSECURE, HPROT[1]} = | | | 2'b10 | | | | -| | if E20 core mode = supervisor, then {HNONSECURE, HPROT[1]} | -| | = 2'b11 | -| | | | | if E20 core mode = machine, then {HNONSECURE, HPROT[1]} = | | | 2'b01 | +--------+-------------------------------------------------------------+