From d6ea672e953b9b9d5ef7c1530138154628bc0ab0 Mon Sep 17 00:00:00 2001
From: dberenguer <dberenguer@usapiens.com>
Date: Wed, 7 Jun 2017 11:32:19 +0200
Subject: [PATCH] Cores prepared for 20 MHz MCU clock

---
 cores/panstamp/cc430core.h | 19 +++++++++++++++++--
 cores/panstamp/wiring.h    |  7 ++++++-
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/cores/panstamp/cc430core.h b/cores/panstamp/cc430core.h
index 4485a6a..bc135ac 100644
--- a/cores/panstamp/cc430core.h
+++ b/cores/panstamp/cc430core.h
@@ -38,7 +38,7 @@
  * MCLK config macros with fixed VCORE
  */
 #define _SET_MCLK_12MHZ()   _SET_VCORE_12MHZ(2)
-#define _SET_MCLK_20MHZ()   setVcoreMCLK(3, DCORSEL_4, 0x262)
+#define _SET_MCLK_20MHZ()   setVcoreMCLK(3, DCORSEL_7, 0x262)
 
 /**
  * Class: CC430CORE
@@ -88,6 +88,17 @@ class CC430CORE
      */
     void init(uint8_t vCore=2, uint16_t dcorsel=DCORSEL_5, uint16_t flln=0x16E);
 
+    /**
+     * init20mhz
+     * 
+     * Initialize CC430 core at VCORE = 2 and SCLK = 20 MHz
+     *
+     */
+    inline void init20mhz(void)
+    {
+      init(3, DCORSEL_7, 0x262);
+    }
+
     /**
      * setLowPowerMode
      *
@@ -112,6 +123,9 @@ class CC430CORE
      */
     inline void begin(void)
     {
+      #if (SYSTEM_CLK_FREQ == CLK_FREQ_20MHZ)
+      init20mhz();
+      #else
       // Initialize MCU core with minimum COREV
       init(0);
       // Read Vcc
@@ -121,6 +135,7 @@ class CC430CORE
         init(2);
       else if (vcc > 2000)
         init(1);
+      #endif
     }
 
     /**
@@ -184,7 +199,7 @@ class CC430CORE
      *
      * Read internal temperature from CC430 MCU
      *
-     * @return voltage in 0.1 ºC
+     * @return temperature in 0.1 ºC
      */
     inline int getTemp(void)
     {
diff --git a/cores/panstamp/wiring.h b/cores/panstamp/wiring.h
index cf95f7b..49cd1df 100644
--- a/cores/panstamp/wiring.h
+++ b/cores/panstamp/wiring.h
@@ -36,7 +36,12 @@
 /**
  * System clock
  */
-#define SYSTEM_CLK_FREQ 12000000L
+#define CLK_FREQ_12MHZ  12000000L
+#define CLK_FREQ_20MHZ  20000000L
+
+#define SYSTEM_CLK_FREQ CLK_FREQ_12MHZ
+//#define SYSTEM_CLK_FREQ CLK_FREQ_20MHZ
+
 #ifndef F_CPU
 #define F_CPU  SYSTEM_CLK_FREQ
 #endif