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lab1.map.rpt
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Analysis & Synthesis report for lab1
Wed Aug 03 00:09:01 2016
Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. User-Specified and Inferred Latches
9. General Register Statistics
10. Inverted Register Statistics
11. Multiplexer Restructuring Statistics (Restructuring Performed)
12. Parameter Settings for User Entity Instance: Top-level Entity: |lab1
13. Post-Synthesis Netlist Statistics for Top Partition
14. Elapsed Time Per Partition
15. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Aug 03 00:09:01 2016 ;
; Quartus Prime Version ; 15.1.0 Build 185 10/21/2015 SJ Lite Edition ;
; Revision Name ; lab1 ;
; Top-level Entity Name ; lab1 ;
; Family ; Cyclone IV E ;
; Total logic elements ; 1,086 ;
; Total combinational functions ; 1,086 ;
; Dedicated logic registers ; 371 ;
; Total registers ; 371 ;
; Total pins ; 63 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP4CE30F23C7 ; ;
; Top-level entity name ; lab1 ; lab1 ;
; Family name ; Cyclone IV E ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------+---------+
; lab1.vhd ; yes ; User VHDL File ; C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd ; ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------+---------+
+-----------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------------------+
; Resource ; Usage ;
+---------------------------------------------+-------------------+
; Estimated Total logic elements ; 1,086 ;
; ; ;
; Total combinational functions ; 1086 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 523 ;
; -- 3 input functions ; 96 ;
; -- <=2 input functions ; 467 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 746 ;
; -- arithmetic mode ; 340 ;
; ; ;
; Total registers ; 371 ;
; -- Dedicated logic registers ; 371 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 63 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Maximum fan-out node ; CLOCK_50MHz~input ;
; Maximum fan-out ; 371 ;
; Total fan-out ; 4613 ;
; Average fan-out ; 2.91 ;
+---------------------------------------------+-------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |lab1 ; 1086 (1086) ; 371 (371) ; 0 ; 0 ; 0 ; 0 ; 63 ; 0 ; |lab1 ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; PROGRAMA[0] ; KEY[1] ; yes ;
; PROGRAMA[3] ; KEY[1] ; yes ;
; PROGRAMA[2] ; KEY[1] ; yes ;
; PROGRAMA[1] ; KEY[1] ; yes ;
; Number of user-specified and inferred latches = 4 ; ; ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 371 ;
; Number of registers using Synchronous Clear ; 224 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 259 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; ESTADO[4] ; 43 ;
; ESTADO[3] ; 52 ;
; ESTADO[2] ; 68 ;
; Total number of inverted registers = 3 ; ;
+----------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |lab1|ESTADO_R1V[1] ;
; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |lab1|ESTADO_AGITACAO[1] ;
; 6:1 ; 32 bits ; 128 LEs ; 32 LEs ; 96 LEs ; Yes ; |lab1|COUNTER_SECONDS_R1_V[20] ;
; 7:1 ; 32 bits ; 128 LEs ; 32 LEs ; 96 LEs ; Yes ; |lab1|COUNTER_CENTISECONDS_AGITACAO[0] ;
; 7:1 ; 32 bits ; 128 LEs ; 32 LEs ; 96 LEs ; Yes ; |lab1|COUNTER_R1_V[11] ;
; 8:1 ; 32 bits ; 160 LEs ; 32 LEs ; 128 LEs ; Yes ; |lab1|COUNTER_AGITACAO[11] ;
; 15:1 ; 4 bits ; 40 LEs ; 32 LEs ; 8 LEs ; Yes ; |lab1|ESTADO_R1C[1] ;
; 16:1 ; 32 bits ; 320 LEs ; 32 LEs ; 288 LEs ; Yes ; |lab1|COUNTER_R1[1] ;
; 54:1 ; 32 bits ; 1152 LEs ; 32 LEs ; 1120 LEs ; Yes ; |lab1|COUNTER_SECONDS[10] ;
; 54:1 ; 32 bits ; 1152 LEs ; 32 LEs ; 1120 LEs ; Yes ; |lab1|COUNTER[26] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |lab1 ;
+----------------+----------+------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+----------+------------------------------------------+
; a0 ; 00111111 ; Unsigned Binary ;
; a1 ; 00000110 ; Unsigned Binary ;
; a2 ; 01011011 ; Unsigned Binary ;
; a3 ; 01001111 ; Unsigned Binary ;
; a4 ; 01100110 ; Unsigned Binary ;
; a5 ; 01101101 ; Unsigned Binary ;
; a6 ; 01111101 ; Unsigned Binary ;
; a7 ; 00000111 ; Unsigned Binary ;
; a8 ; 01111111 ; Unsigned Binary ;
; a9 ; 01101111 ; Unsigned Binary ;
; err ; 10000000 ; Unsigned Binary ;
+----------------+----------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 63 ;
; cycloneiii_ff ; 371 ;
; ENA ; 67 ;
; ENA SCLR ; 192 ;
; SCLR ; 32 ;
; plain ; 80 ;
; cycloneiii_lcell_comb ; 1096 ;
; arith ; 340 ;
; 2 data inputs ; 337 ;
; 3 data inputs ; 3 ;
; normal ; 756 ;
; 0 data inputs ; 2 ;
; 1 data inputs ; 19 ;
; 2 data inputs ; 119 ;
; 3 data inputs ; 93 ;
; 4 data inputs ; 523 ;
; ; ;
; Max LUT depth ; 13.00 ;
; Average LUT depth ; 6.39 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:10 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
Info: Processing started: Wed Aug 03 00:08:33 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab1 -c lab1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 2 design units, including 1 entities, in source file lab1.vhd
Info (12022): Found design unit 1: lab1-rtl File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 38
Info (12023): Found entity 1: lab1 File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 7
Info (12127): Elaborating entity "lab1" for the top level hierarchy
Warning (10541): VHDL Signal Declaration warning at lab1.vhd(29): used implicit default value for signal "GPIO_0" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (10631): VHDL Process Statement warning at lab1.vhd(258): inferring latch(es) for signal or variable "PROGRAMA", which holds its previous value in one or more paths through the process File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 258
Warning (10492): VHDL Process Statement warning at lab1.vhd(311): signal "ESTADO_R1C" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 311
Warning (10492): VHDL Process Statement warning at lab1.vhd(312): signal "ESTADO_R1C" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 312
Warning (10492): VHDL Process Statement warning at lab1.vhd(325): signal "ESTADO_R1C" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 325
Warning (10492): VHDL Process Statement warning at lab1.vhd(326): signal "ESTADO_R1C" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 326
Info (10041): Inferred latch for "PROGRAMA[0]" at lab1.vhd(258) File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 258
Info (10041): Inferred latch for "PROGRAMA[1]" at lab1.vhd(258) File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 258
Info (10041): Inferred latch for "PROGRAMA[2]" at lab1.vhd(258) File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 258
Info (10041): Inferred latch for "PROGRAMA[3]" at lab1.vhd(258) File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 258
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "LEDM_C[0]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 26
Warning (13410): Pin "LEDM_C[1]" is stuck at VCC File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 26
Warning (13410): Pin "LEDM_C[2]" is stuck at VCC File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 26
Warning (13410): Pin "LEDM_C[3]" is stuck at VCC File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 26
Warning (13410): Pin "LEDM_C[4]" is stuck at VCC File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 26
Warning (13410): Pin "LEDM_R[6]" is stuck at VCC File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 27
Warning (13410): Pin "LEDM_R[7]" is stuck at VCC File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 27
Warning (13410): Pin "GPIO_0[0]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[1]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[2]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[3]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[4]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[5]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[6]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[7]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[8]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[9]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[10]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[11]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[12]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[13]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[14]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[15]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Warning (13410): Pin "GPIO_0[16]" is stuck at GND File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 29
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 10 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "KEY[2]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Warning (15610): No output dependent on input pin "KEY[3]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Warning (15610): No output dependent on input pin "KEY[4]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Warning (15610): No output dependent on input pin "KEY[5]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Warning (15610): No output dependent on input pin "KEY[6]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Warning (15610): No output dependent on input pin "KEY[7]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Warning (15610): No output dependent on input pin "KEY[8]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Warning (15610): No output dependent on input pin "KEY[9]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Warning (15610): No output dependent on input pin "KEY[10]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Warning (15610): No output dependent on input pin "KEY[11]" File: C:/Users/PedroHenrique/Desktop/Projeto/vhdl01/lab1.vhd Line: 30
Info (21057): Implemented 1150 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 17 input pins
Info (21059): Implemented 46 output pins
Info (21061): Implemented 1087 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 43 warnings
Info: Peak virtual memory: 864 megabytes
Info: Processing ended: Wed Aug 03 00:09:01 2016
Info: Elapsed time: 00:00:28
Info: Total CPU time (on all processors): 00:00:49