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OptionProcessor.cpp
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#include "pch.h"
// Filename: Processor.cpp
// =======================
// Author: Benjamin Jurke
// File history: 27.02.2002 - File created. Support for Intel and AMD processors
// 05.03.2002 - Fixed the CPUID bug: On Pre-Pentium CPUs the CPUID
// command is not available
// - The CProcessor::WriteInfoTextFile function do not
// longer use Win32 file functions (-> os independend)
// - Optional include of the windows.h header which is
// still need for CProcessor::GetCPUFrequency.
//////////////////////////////////////////////////////////////////////////////////
/*
I was wondering why we get such strange CPU-Speeds. I found out that it seems to be a problem of the Sleep() function being unappropriate.
I have updated the CProcessor::GetCPUFrequency function to use timeGetTime() to avoid giving up the time slice. It seems to be a bad idea to claim for REALTIME_PRIORITY_CLASS and then just calling Sleep().
<cpp>
// unsigned __int64 CProcessor::GetCPUFrequency(unsigned int uiMeasureMSecs)
// =========================================================================
// Function to measure the current CPU frequency
////////////////////////////////////////////////////////////////////////////
unsigned __int64 CProcessor::GetCPUFrequency(unsigned int uiMeasureMSecs)
{
#ifndef PROCESSOR_FREQUENCY_MEASURE_AVAILABLE
return 0;
#else
// If there are invalid measure time parameters, zero msecs for example,
// we've to exit the function
if (uiMeasureMSecs < 1)
{
// If theres already a measured frequency available, we return it
if (uqwFrequency > 0)
return uqwFrequency;
else
return 0;
}
// Now we check if the CPUID command is available
if (!CheckCPUIDPresence())
return 0;
// First we get the CPUID standard level 0x00000001
unsigned long reg;
__asm
{
mov eax, 1
cpuid
mov reg, edx
}
// Then we check, if the RDTSC (Real Date Time Stamp Counter) is available.
// This function is necessary for our measure process.
if (!(reg & (1 << 4)))
return 0;
// After that we declare some vars and check the frequency of the high
// resolution timer for the measure process.
// If there's no high-res timer, we exit.
__int64 starttime, endtime, timedif, freq, start, end, dif;
bool hasperformancecounter=TRUE;
if (!QueryPerformanceFrequency((LARGE_INTEGER *) &freq))
hasperformancecounter=FALSE;
// Now we can init the measure process. We set the process and thread priority
// to the highest available level (Realtime priority). Also we focus the
// first processor in the multiprocessor system.
HANDLE hProcess = GetCurrentProcess();
HANDLE hThread = GetCurrentThread();
unsigned long dwCurPriorityClass = GetPriorityClass(hProcess);
int iCurThreadPriority = GetThreadPriority(hThread);
unsigned long dwProcessMask, dwSystemMask, dwNewMask = 1;
GetProcessAffinityMask(hProcess, &dwProcessMask, &dwSystemMask);
SetProcessAffinityMask(hProcess, dwNewMask);
SetPriorityClass(hProcess, REALTIME_PRIORITY_CLASS);
SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL);
// Now we call a CPUID to ensure, that all other prior called functions are
// completed now (serialization)
DWORD tm=timeGetTime(),tms;
if (tm>0xffffffff-(uiMeasureMSecs+1000))//just about to overlap
//(happens once every 47 days, so no trouble here
{
Sleep(uiMeasureMSecs+2000);//Wait some time.
}
if (hasperformancecounter)
{
__asm cpuid
// We ask the high-res timer for the start time
QueryPerformanceCounter((LARGE_INTEGER *) &starttime);
// Then we get the current cpu clock and store it
__asm
{
rdtsc
mov dword ptr [start+4], edx
mov dword ptr [start], eax
}
// Now we wait for some msecs
//Sleep(uiMeasureMSecs);
tm=timeGetTime();
tms=uiMeasureMSecs+tm;
while (tms>timeGetTime());
// We ask for the end time
QueryPerformanceCounter((LARGE_INTEGER *) &endtime);
// And also for the end cpu clock
__asm
{
rdtsc
mov dword ptr [end+4], edx
mov dword ptr [end], eax
}
}
else
{
DWORD tm=timeGetTime(),tms;
if (tm>0xffffffff-(uiMeasureMSecs+1000))//just about to overlap
//(happens once every 47 days, so no trouble here
{
Sleep(uiMeasureMSecs+2000);//Wait some time.
}
__asm cpuid
//use timeGetTime instead of the performance counter
starttime=timeGetTime();
while(timeGetTime()==starttime);//start when timer flips
// Then we get the current cpu clock and store it
__asm
{
rdtsc
mov dword ptr [start+4], edx
mov dword ptr [start], eax
}
// Now we wait for some msecs
//Sleep(uiMeasureMSecs);
tm=timeGetTime();
tms=uiMeasureMSecs+tm;
while (tms>timeGetTime());
// We ask for the end time
endtime=timeGetTime();
// And also for the end cpu clock
__asm
{
rdtsc
mov dword ptr [end+4], edx
mov dword ptr [end], eax
}
freq=1000; //resolution is ms
}
// Now we can restore the default process and thread priorities
SetProcessAffinityMask(hProcess, dwProcessMask);
SetThreadPriority(hThread, iCurThreadPriority);
SetPriorityClass(hProcess, dwCurPriorityClass);
// Then we calculate the time and clock differences
dif = end - start;
timedif = endtime - starttime;
// And finally the frequency is the clock difference divided by the time
// difference.
uqwFrequency = (__int64) (((double) dif) / (((double) timedif) / freq));
// At last we just return the frequency that is also stored in the call
// member var uqwFrequency
return uqwFrequency;
#endif
}
</cpp>
This new implementation also works if the high-res performance timer is not available.
My measures show that it is much more appropriate than the original version. Please verify.
PS: I had to change unsigned __int64 to __int64 because MSVC complained otherwise.
PPS: Remember: If you actually exspect that the target system cannot use cpuid you can call GetSystemInfo() to get at least the cpu type.
PPPS: Don't forget to link winmm.lib now, or you'll run into linker errors.
*/
#include <stdio.h>
#include <string.h>
#include <memory.h>
#include "x86_proc.h"
#ifdef PROCESSOR_FREQUENCY_MEASURE_AVAILABLE
#include <windows.h>
// We need the QueryPerformanceCounter and Sleep functions
#endif
// Some macros we often need
////////////////////////////
#define CheckBit(var, bit) ((var & (1 << bit)) ? true : false)
// CProcessor::CProcessor
// ======================
// Class constructor:
/////////////////////////
CProcessor::CProcessor()
{
uqwFrequency = 0;
memset(&CPUInfo, 0, sizeof(CPUInfo));
}
// unsigned __int64 CProcessor::GetCPUFrequency(unsigned int uiMeasureMSecs)
// =========================================================================
// Function to measure the current CPU frequency
////////////////////////////////////////////////////////////////////////////
unsigned __int64 CProcessor::GetCPUFrequency(unsigned int uiMeasureMSecs)
{
#ifndef PROCESSOR_FREQUENCY_MEASURE_AVAILABLE
return 0;
#else
// If there are invalid measure time parameters, zero msecs for example,
// we've to exit the function
if (uiMeasureMSecs < 1)
{
// If theres already a measured frequency available, we return it
if (uqwFrequency > 0)
{
return uqwFrequency;
}
else
{
return 0;
}
}
// Now we check if the CPUID command is available
if (!CheckCPUIDPresence())
{
return 0;
}
// First we get the CPUID standard level 0x00000001
unsigned long reg;
__asm
{
mov eax, 1
cpuid
mov reg, edx
}
// Then we check, if the RDTSC (Real Date Time Stamp Counter) is available.
// This function is necessary for our measure process.
if (!(reg & (1 << 4)))
{
return 0;
}
// After that we declare some vars and check the frequency of the high
// resolution timer for the measure process.
// If there's no high-res timer, we exit.
__int64 starttime, endtime, timedif, freq, start, end, dif;
bool hasperformancecounter=TRUE;
if (!QueryPerformanceFrequency((LARGE_INTEGER *) &freq))
{
hasperformancecounter=FALSE;
}
// Now we can init the measure process. We set the process and thread priority
// to the highest available level (Realtime priority). Also we focus the
// first processor in the multiprocessor system.
HANDLE hProcess = GetCurrentProcess();
HANDLE hThread = GetCurrentThread();
unsigned long dwCurPriorityClass = GetPriorityClass(hProcess);
int iCurThreadPriority = GetThreadPriority(hThread);
unsigned long dwProcessMask, dwSystemMask, dwNewMask = 1;
GetProcessAffinityMask(hProcess, &dwProcessMask, &dwSystemMask);
SetProcessAffinityMask(hProcess, dwNewMask);
SetPriorityClass(hProcess, REALTIME_PRIORITY_CLASS);
SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL);
// Now we call a CPUID to ensure, that all other prior called functions are
// completed now (serialization)
DWORD tm=timeGetTime(),tms;
if (tm>0xffffffff-(uiMeasureMSecs+1000)) //just about to overlap
//(happens once every 47 days, so no trouble here
{
Sleep(uiMeasureMSecs+2000); //Wait some time.
}
if (hasperformancecounter)
{
__asm cpuid
// We ask the high-res timer for the start time
QueryPerformanceCounter((LARGE_INTEGER *) &starttime);
// Then we get the current cpu clock and store it
__asm
{
rdtsc
mov dword ptr [start+4], edx
mov dword ptr [start], eax
}
// Now we wait for some msecs
//Sleep(uiMeasureMSecs);
tm=timeGetTime();
tms=uiMeasureMSecs+tm;
while (tms>timeGetTime()) ;
// We ask for the end time
QueryPerformanceCounter((LARGE_INTEGER *) &endtime);
// And also for the end cpu clock
__asm
{
rdtsc
mov dword ptr [end+4], edx
mov dword ptr [end], eax
}
}
else
{
DWORD tm=timeGetTime(),tms;
if (tm>0xffffffff-(uiMeasureMSecs+1000)) //just about to overlap
//(happens once every 47 days, so no trouble here
{
Sleep(uiMeasureMSecs+2000); //Wait some time.
}
__asm cpuid
//use timeGetTime instead of the performance counter
starttime=timeGetTime();
while(timeGetTime()==starttime) ;
//start when timer flips
// Then we get the current cpu clock and store it
__asm
{
rdtsc
mov dword ptr [start+4], edx
mov dword ptr [start], eax
}
// Now we wait for some msecs
//Sleep(uiMeasureMSecs);
tm=timeGetTime();
tms=uiMeasureMSecs+tm;
while (tms>timeGetTime()) ;
// We ask for the end time
endtime=timeGetTime();
// And also for the end cpu clock
__asm
{
rdtsc
mov dword ptr [end+4], edx
mov dword ptr [end], eax
}
freq=1000; //resolution is ms
}
// Now we can restore the default process and thread priorities
SetProcessAffinityMask(hProcess, dwProcessMask);
SetThreadPriority(hThread, iCurThreadPriority);
SetPriorityClass(hProcess, dwCurPriorityClass);
// Then we calculate the time and clock differences
dif = end - start;
timedif = endtime - starttime;
// And finally the frequency is the clock difference divided by the time
// difference.
uqwFrequency = (__int64) (((double) dif) / (((double) timedif) / freq));
// At last we just return the frequency that is also stored in the call
// member var uqwFrequency
return uqwFrequency;
#endif
}
// bool CProcessor::AnalyzeIntelProcessor()
// ========================================
// Private class function for analyzing an Intel processor
//////////////////////////////////////////////////////////
bool CProcessor::AnalyzeIntelProcessor()
{
unsigned long eaxreg, ebxreg, edxreg;
// First we check if the CPUID command is available
if (!CheckCPUIDPresence())
{
return false;
}
// Now we get the CPUID standard level 0x00000001
__asm
{
mov eax, 1
cpuid
mov eaxreg, eax
mov ebxreg, ebx
mov edxreg, edx
}
// Then get the cpu model, family, type, stepping and brand id by masking
// the eax and ebx register
CPUInfo.uiStepping = eaxreg & 0xF;
CPUInfo.uiModel = (eaxreg >> 4) & 0xF;
CPUInfo.uiFamily = (eaxreg >> 8) & 0xF;
CPUInfo.uiType = (eaxreg >> 12) & 0x3;
CPUInfo.uiBrandID = ebxreg & 0xF;
// Now we can translate the type number to a more understandable string format
switch (CPUInfo.uiType)
{
case 0: // Type = 0: Original OEM processor
strcpy(CPUInfo.strType, "Original OEM");
strcpy(strCPUName, CPUInfo.strType);
strcat(strCPUName, " ");
break;
case 1: // Type = 1: Overdrive processor
strcpy(CPUInfo.strType, "Overdrive");
strcpy(strCPUName, CPUInfo.strType);
strcat(strCPUName, " ");
break;
case 2: // Type = 2: Dual-capable processor
strcpy(CPUInfo.strType, "Dual-capable");
strcpy(strCPUName, CPUInfo.strType);
strcat(strCPUName, " ");
break;
case 3: // Type = 3: Reserved for future use
strcpy(CPUInfo.strType, "Reserved");
break;
default: // This should be never called, cause we just mask 2 bits --> [0..3]
strcpy(CPUInfo.strType, "Unknown");
break;
}
// Then we translate the brand id:
switch (CPUInfo.uiBrandID)
{
case 0: // Brand id = 0: Brand id not supported on this processor
strcpy(CPUInfo.strBrandID, "Not supported");
break;
case 1: // Brand id = 1: Intel Celeron (0.18 µm) processor
strcpy(CPUInfo.strBrandID, "0.18 µm Intel Celeron");
break;
case 2: // Brand id = 2: Intel Pentium III (0.18 µm) processor
strcpy(CPUInfo.strBrandID, "0.18 µm Intel Pentium III");
break;
case 3: // Brand id = 3: Model dependent
if (CPUInfo.uiModel == 6)
{
// If the cpu model is Celeron (well, I'm NOT SURE!!!)
strcpy(CPUInfo.strBrandID, "0.13 µm Intel Celeron");
}
else
{
strcpy(CPUInfo.strBrandID, "0.18 µm Intel Pentium III Xeon");
}
break;
case 4: // Brand id = 4: Intel Pentium III Tualatin (0.13 µm) processor
strcpy(CPUInfo.strBrandID, "0.13 µm Intel Pentium III");
break;
case 6: // Brand id = 6: Intel Pentium III mobile (0.13 µm) processor
strcpy(CPUInfo.strBrandID, "0.13 µm Intel Pentium III mobile");
break;
case 7: // Brand id = 7: Intel Celeron mobile (0.13 µm) processor
strcpy(CPUInfo.strBrandID, "0.13 µm Intel Celeron mobile");
break;
case 8: // Brand id = 8: Intel Pentium 4 Willamette (0.18 µm) processor
strcpy(CPUInfo.strBrandID, "0.18 µm Intel Pentium 4");
break;
case 9: // Brand id = 9: Intel Pentium 4 Northwood (0.13 µm) processor
strcpy(CPUInfo.strBrandID, "0.13 µm Intel Pentium 4");
break;
case 0xA: // Brand id = 0xA: Intel Pentium 4 Northwood (0.13 µm processor)
strcpy(CPUInfo.strBrandID, "0.13 µm Intel Pentium 4");
break; // No idea, where the difference to id=9 is
case 0xB: // Brand id = 0xB: Intel Pentium 4 Northwood Xeon (0.13 µm processor)
strcpy(CPUInfo.strBrandID, "0.13 µm Intel Pentium 4 Xeon");
break;
case 0xE: // Brand id = 0xE: Intel Pentium 4 Willamette Xeon (0.18 µm processor)
strcpy(CPUInfo.strBrandID, "0.18 µm Intel Pentium 4 Xeon");
break;
default: // Should be never called, but sure is sure
strcpy(CPUInfo.strBrandID, "Unknown");
break;
}
// Then we translate the cpu family
switch (CPUInfo.uiFamily)
{
case 3: // Family = 3: i386 (80386) processor family
strcpy(CPUInfo.strFamily, "Intel i386");
break;
case 4: // Family = 4: i486 (80486) processor family
strcpy(CPUInfo.strFamily, "Intel i486");
break;
case 5: // Family = 5: Pentium (80586) processor family
strcpy(CPUInfo.strFamily, "Intel Pentium");
break;
case 6: // Family = 6: Pentium Pro (80686) processor family
strcpy(CPUInfo.strFamily, "Intel Pentium Pro");
break;
case 15: // Family = 15: Extended family specific
// Masking the extended family
CPUInfo.uiExtendedFamily = (eaxreg >> 20) & 0xFF;
switch (CPUInfo.uiExtendedFamily)
{
case 0: // Family = 15, Ext. Family = 0: Pentium 4 (80786 ??) processor family
strcpy(CPUInfo.strFamily, "Intel Pentium 4");
break;
case 1: // Family = 15, Ext. Family = 1: McKinley (64-bit) processor family
strcpy(CPUInfo.strFamily, "Intel McKinley (IA-64)");
break;
default: // Sure is sure
strcpy(CPUInfo.strFamily, "Unknown Intel Pentium 4+");
break;
}
break;
default: // Failsave
strcpy(CPUInfo.strFamily, "Unknown");
break;
}
// Now we come to the big deal, the exact model name
switch (CPUInfo.uiFamily)
{
case 3: // i386 (80386) processor family
strcpy(CPUInfo.strModel, "Unknown Intel i386");
strcat(strCPUName, "Intel i386");
break;
case 4: // i486 (80486) processor family
switch (CPUInfo.uiModel)
{
case 0: // Model = 0: i486 DX-25/33 processor model
strcpy(CPUInfo.strModel, "Intel i486 DX-25/33");
strcat(strCPUName, "Intel i486 DX-25/33");
break;
case 1: // Model = 1: i486 DX-50 processor model
strcpy(CPUInfo.strModel, "Intel i486 DX-50");
strcat(strCPUName, "Intel i486 DX-50");
break;
case 2: // Model = 2: i486 SX processor model
strcpy(CPUInfo.strModel, "Intel i486 SX");
strcat(strCPUName, "Intel i486 SX");
break;
case 3: // Model = 3: i486 DX2 (with i487 numeric coprocessor) processor model
strcpy(CPUInfo.strModel, "Intel i486 487/DX2");
strcat(strCPUName, "Intel i486 DX2 with i487 numeric coprocessor");
break;
case 4: // Model = 4: i486 SL processor model (never heard ?!?)
strcpy(CPUInfo.strModel, "Intel i486 SL");
strcat(strCPUName, "Intel i486 SL");
break;
case 5: // Model = 5: i486 SX2 processor model
strcpy(CPUInfo.strModel, "Intel i486 SX2");
strcat(strCPUName, "Intel i486 SX2");
break;
case 7: // Model = 7: i486 write-back enhanced DX2 processor model
strcpy(CPUInfo.strModel, "Intel i486 write-back enhanced DX2");
strcat(strCPUName, "Intel i486 write-back enhanced DX2");
break;
case 8: // Model = 8: i486 DX4 processor model
strcpy(CPUInfo.strModel, "Intel i486 DX4");
strcat(strCPUName, "Intel i486 DX4");
break;
case 9: // Model = 9: i486 write-back enhanced DX4 processor model
strcpy(CPUInfo.strModel, "Intel i486 write-back enhanced DX4");
strcat(strCPUName, "Intel i486 DX4");
break;
default: // ...
strcpy(CPUInfo.strModel, "Unknown Intel i486");
strcat(strCPUName, "Intel i486 (Unknown model)");
break;
}
break;
case 5: // Pentium (80586) processor family
switch (CPUInfo.uiModel)
{
case 0: // Model = 0: Pentium (P5 A-Step) processor model
strcpy(CPUInfo.strModel, "Intel Pentium (P5 A-Step)");
strcat(strCPUName, "Intel Pentium (P5 A-Step core)");
break; // Famous for the DIV bug, as far as I know
case 1: // Model = 1: Pentium 60/66 processor model
strcpy(CPUInfo.strModel, "Intel Pentium 60/66 (P5)");
strcat(strCPUName, "Intel Pentium 60/66 (P5 core)");
break;
case 2: // Model = 2: Pentium 75-200 (P54C) processor model
strcpy(CPUInfo.strModel, "Intel Pentium 75-200 (P54C)");
strcat(strCPUName, "Intel Pentium 75-200 (P54C core)");
break;
case 3: // Model = 3: Pentium overdrive for 486 systems processor model
strcpy(CPUInfo.strModel, "Intel Pentium for 486 system (P24T Overdrive)");
strcat(strCPUName, "Intel Pentium for 486 (P24T overdrive core)");
break;
case 4: // Model = 4: Pentium MMX processor model
strcpy(CPUInfo.strModel, "Intel Pentium MMX (P55C)");
strcat(strCPUName, "Intel Pentium MMX (P55C core)");
break;
case 7: // Model = 7: Pentium processor model (don't know difference to Model=2)
strcpy(CPUInfo.strModel, "Intel Pentium (P54C)");
strcat(strCPUName, "Intel Pentium (P54C core)");
break;
case 8: // Model = 8: Pentium MMX (0.25 µm) processor model
strcpy(CPUInfo.strModel, "Intel Pentium MMX (P55C), 0.25 µm");
strcat(strCPUName, "Intel Pentium MMX (P55C core), 0.25 µm");
break;
default: // ...
strcpy(CPUInfo.strModel, "Unknown Intel Pentium");
strcat(strCPUName, "Intel Pentium (Unknown P5-model)");
break;
}
break;
case 6: // Pentium Pro (80686) processor family
switch (CPUInfo.uiModel)
{
case 0: // Model = 0: Pentium Pro (P6 A-Step) processor model
strcpy(CPUInfo.strModel, "Intel Pentium Pro (P6 A-Step)");
strcat(strCPUName, "Intel Pentium Pro (P6 A-Step core)");
break;
case 1: // Model = 1: Pentium Pro
strcpy(CPUInfo.strModel, "Intel Pentium Pro (P6)");
strcat(strCPUName, "Intel Pentium Pro (P6 core)");
break;
case 3: // Model = 3: Pentium II (66 MHz FSB, I think) processor model
strcpy(CPUInfo.strModel, "Intel Pentium II Model 3, 0.28 µm");
strcat(strCPUName, "Intel Pentium II (Model 3 core, 0.28 µm process)");
break;
case 5: // Model = 5: Pentium II/Xeon/Celeron (0.25 µm) processor model
strcpy(CPUInfo.strModel, "Intel Pentium II Model 5/Xeon/Celeron, 0.25 µm");
strcat(strCPUName, "Intel Pentium II/Xeon/Celeron (Model 5 core, 0.25 µm process)");
break;
case 6: // Model = 6: Celoron (on-die L2 cache) processor model
strcpy(CPUInfo.strModel, "Intel Celeron - internal L2 cache");
strcat(strCPUName, "Intel Celeron with internal L2 cache");
break;
case 7: // Model = 7: Pentium III/Xeon (extern L2 cache) processor model
strcpy(CPUInfo.strModel, "Intel Pentium III/Pentium III Xeon - external L2 cache, 0.25 µm");
strcat(strCPUName, "Intel Pentium III/Pentium III Xeon (0.25 µm process) with external L2 cache");
break;
case 8: // Model = 8: Pentium III/Xeon/Celeron (256 KB on-die L2 cache) processor model
strcpy(CPUInfo.strModel, "Intel Pentium III/Celeron/Pentium III Xeon - internal L2 cache, 0.18 µm");
// We want to know it exactly:
switch (CPUInfo.uiBrandID)
{
case 1: // Model = 8, Brand id = 1: Celeron (on-die L2 cache) processor model
strcat(strCPUName, "Intel Celeron (0.18 µm process) with internal L2 cache");
break;
case 2: // Model = 8, Brand id = 2: Pentium III (on-die L2 cache) processor model (my current cpu :-))
strcat(strCPUName, "Intel Pentium III (0.18 µm process) with internal L2 cache");
break;
case 3: // Model = 8, Brand id = 3: Pentium III Xeon (on-die L2 cache) processor model
strcat(strCPUName, "Intel Pentium III Xeon (0.18 µm process) with internal L2 cache");
break;
default: // ...²
strcat(strCPUName, "Intel Pentium III core (unknown model, 0.18 µm process) with internal L2 cache");
break;
}
break;
case 0xA: // Model = 0xA: Pentium III/Xeon/Celeron (1 or 2 MB on-die L2 cache) processor model
strcpy(CPUInfo.strModel, "Intel Pentium III/Celeron/Pentium III Xeon - internal L2 cache, 0.18 µm");
// Exact detection:
switch (CPUInfo.uiBrandID)
{
case 1: // Model = 0xA, Brand id = 1: Celeron (1 or 2 MB on-die L2 cache (does it exist??)) processor model
strcat(strCPUName, "Intel Celeron (0.18 µm process) with internal L2 cache");
break;
case 2: // Model = 0xA, Brand id = 2: Pentium III (1 or 2 MB on-die L2 cache (never seen...)) processor model
strcat(strCPUName, "Intel Pentium III (0.18 µm process) with internal L2 cache");
break;
case 3: // Model = 0xA, Brand id = 3: Pentium III Xeon (1 or 2 MB on-die L2 cache) processor model
strcat(strCPUName, "Intel Pentium III Xeon (0.18 µm process) with internal L2 cache");
break;
default: // Getting bored of this............
strcat(strCPUName, "Intel Pentium III core (unknown model, 0.18 µm process) with internal L2 cache");
break;
}
break;
case 0xB: // Model = 0xB: Pentium III/Xeon/Celeron (Tualatin core, on-die cache) processor model
strcpy(CPUInfo.strModel, "Intel Pentium III/Celeron/Pentium III Xeon - internal L2 cache, 0.13 µm");
// Omniscient: ;-)
switch (CPUInfo.uiBrandID)
{
case 3: // Model = 0xB, Brand id = 3: Celeron (Tualatin core) processor model
strcat(strCPUName, "Intel Celeron (Tualatin core, 0.13 µm process) with internal L2 cache");
break;
case 4: // Model = 0xB, Brand id = 4: Pentium III (Tualatin core) processor model
strcat(strCPUName, "Intel Pentium III (Tualatin core, 0.13 µm process) with internal L2 cache");
break;
case 7: // Model = 0xB, Brand id = 7: Celeron mobile (Tualatin core) processor model
strcat(strCPUName, "Intel Celeron mobile (Tualatin core, 0.13 µm process) with internal L2 cache");
break;
default: // *bored*
strcat(strCPUName, "Intel Pentium III Tualatin core (unknown model, 0.13 µm process) with internal L2 cache");
break;
}
break;
default: // *more bored*
strcpy(CPUInfo.strModel, "Unknown Intel Pentium Pro");
strcat(strCPUName, "Intel Pentium Pro (Unknown model)");
break;
}
break;
case 15: // Extended processor family
// Masking the extended model
CPUInfo.uiExtendedModel = (eaxreg >> 16) & 0xFF;
switch (CPUInfo.uiModel)
{
case 0: // Model = 0: Pentium 4 Willamette (A-Step) core
if ((CPUInfo.uiBrandID) == 8) // Brand id = 8: P4 Willamette
{
strcpy(CPUInfo.strModel, "Intel Pentium 4 Willamette (A-Step)");
strcat(strCPUName, "Intel Pentium 4 Willamette (A-Step)");
}
else // else Xeon
{
strcpy(CPUInfo.strModel, "Intel Pentium 4 Willamette Xeon (A-Step)");
strcat(strCPUName, "Intel Pentium 4 Willamette Xeon (A-Step)");
}
break;
case 1: // Model = 1: Pentium 4 Willamette core
if ((CPUInfo.uiBrandID) == 8) // Brand id = 8: P4 Willamette
{
strcpy(CPUInfo.strModel, "Intel Pentium 4 Willamette");
strcat(strCPUName, "Intel Pentium 4 Willamette");
}
else // else Xeon
{
strcpy(CPUInfo.strModel, "Intel Pentium 4 Willamette Xeon");
strcat(strCPUName, "Intel Pentium 4 Willamette Xeon");
}
break;
case 2: // Model = 2: Pentium 4 Northwood core
if (((CPUInfo.uiBrandID) == 9) || ((CPUInfo.uiBrandID) == 0xA)) // P4 Willamette
{
strcpy(CPUInfo.strModel, "Intel Pentium 4 Northwood");
strcat(strCPUName, "Intel Pentium 4 Northwood");
}
else // Xeon
{
strcpy(CPUInfo.strModel, "Intel Pentium 4 Northwood Xeon");
strcat(strCPUName, "Intel Pentium 4 Northwood Xeon");
}
break;
default: // Silly stupid never used failsave option
strcpy(CPUInfo.strModel, "Unknown Intel Pentium 4");
strcat(strCPUName, "Intel Pentium 4 (Unknown model)");
break;
}
break;
default: // *grmpf*
strcpy(CPUInfo.strModel, "Unknown Intel model");
strcat(strCPUName, "Intel (Unknown model)");
break;
}
// After the long processor model block we now come to the processors serial
// number.
// First of all we check if the processor supports the serial number
if (CPUInfo.MaxSupportedLevel >= 3)
{
// If it supports the serial number CPUID level 0x00000003 we read the data
unsigned long sig1, sig2, sig3;
__asm
{
mov eax, 1
cpuid
mov sig1, eax
mov eax, 3
cpuid
mov sig2, ecx
mov sig3, edx
}
// Then we convert the data to an readable string
sprintf(CPUInfo.strProcessorSerial, "%04lX-%04lX-%04lX-%04lX-%04lX-%04lX", sig1 >> 16, sig1 & 0xFFFF, sig3 >> 16, sig3 & 0xFFFF, sig2 >> 16, sig2 & 0xFFFF);
}
else
{
// If there's no serial number support we just mark put "No serial number"
strcpy(CPUInfo.strProcessorSerial, "No Processor Serial Number");
}
// Now we get the standard processor extensions
GetStandardProcessorExtensions();
// And finally the processor configuration (caches, TLBs, ...) and translate
// the data to readable strings
GetStandardProcessorConfiguration();
TranslateProcessorConfiguration();
// At last...
return true;
}
// bool CProcessor::AnalyzeAMDProcessor()
// ======================================
// Private class function for analyzing an AMD processor
////////////////////////////////////////////////////////
bool CProcessor::AnalyzeAMDProcessor()
{
unsigned long eaxreg, ebxreg, ecxreg, edxreg;
// First of all we check if the CPUID command is available
if (!CheckCPUIDPresence())
{
return 0;
}
// Now we get the CPUID standard level 0x00000001
__asm
{
mov eax, 1
cpuid
mov eaxreg, eax
mov ebxreg, ebx
mov edxreg, edx
}
// Then we mask the model, family, stepping and type (AMD does not support brand id)
CPUInfo.uiStepping = eaxreg & 0xF;
CPUInfo.uiModel = (eaxreg >> 4) & 0xF;
CPUInfo.uiFamily = (eaxreg >> 8) & 0xF;
CPUInfo.uiType = (eaxreg >> 12) & 0x3;
// After that, we translate the processor type (see CProcessor::AnalyzeIntelProcessor()
// for further comments on this)
switch (CPUInfo.uiType)
{
case 0:
strcpy(CPUInfo.strType, "Original OEM");
strcpy(strCPUName, CPUInfo.strType);
strcat(strCPUName, " ");
break;
case 1:
strcpy(CPUInfo.strType, "Overdrive");
strcpy(strCPUName, CPUInfo.strType);
strcat(strCPUName, " ");
break;
case 2:
strcpy(CPUInfo.strType, "Dual-capable");
strcpy(strCPUName, CPUInfo.strType);
strcat(strCPUName, " ");
break;
case 3:
strcpy(CPUInfo.strType, "Reserved");
break;
default:
strcpy(CPUInfo.strType, "Unknown");
break;
}
// Now we check if the processor supports the brand id string extended CPUID level
if (CPUInfo.MaxSupportedExtendedLevel >= 0x80000004)
{
// If it supports the extended CPUID level 0x80000004 we read the data
char tmp[52];
memset(tmp, 0, sizeof(tmp));
__asm
{
mov eax, 0x80000002
cpuid
mov dword ptr [tmp], eax
mov dword ptr [tmp+4], ebx
mov dword ptr [tmp+8], ecx
mov dword ptr [tmp+12], edx
mov eax, 0x80000003
cpuid
mov dword ptr [tmp+16], eax
mov dword ptr [tmp+20], ebx
mov dword ptr [tmp+24], ecx
mov dword ptr [tmp+28], edx
mov eax, 0x80000004
cpuid
mov dword ptr [tmp+32], eax
mov dword ptr [tmp+36], ebx
mov dword ptr [tmp+40], ecx
mov dword ptr [tmp+44], edx
}
// And copy it to the brand id string
strcpy(CPUInfo.strBrandID, tmp);
}
else
{
// Or just tell there is no brand id string support
strcpy(CPUInfo.strBrandID, "Not supported");
}
// After that we translate the processor family
switch(CPUInfo.uiFamily)
{
case 4: // Family = 4: 486 (80486) or 5x86 (80486) processor family
switch (CPUInfo.uiModel)
{
case 3: // Thanks to AMD for this nice form of family
case 7: // detection.... *grmpf*
case 8:
case 9:
strcpy(CPUInfo.strFamily, "AMD 80486");
break;
case 0xE:
case 0xF:
strcpy(CPUInfo.strFamily, "AMD 5x86");
break;
default:
strcpy(CPUInfo.strFamily, "Unknown family");
break;
}
break;
case 5: // Family = 5: K5 or K6 processor family
switch (CPUInfo.uiModel)
{
case 0:
case 1:
case 2:
case 3:
strcpy(CPUInfo.strFamily, "AMD K5");
break;
case 6:
case 7:
case 8:
case 9:
strcpy(CPUInfo.strFamily, "AMD K6");
break;
default:
strcpy(CPUInfo.strFamily, "Unknown family");
break;
}
break;
case 6: // Family = 6: K7 (Athlon, ...) processor family
strcpy(CPUInfo.strFamily, "AMD K7");
break;
default: // For security
strcpy(CPUInfo.strFamily, "Unknown family");
break;
}
// After the family detection we come to the specific processor model
// detection
switch (CPUInfo.uiFamily)
{
case 4: // Family = 4: 486 (80486) or 5x85 (80486) processor family
switch (CPUInfo.uiModel)
{
case 3: // Model = 3: 80486 DX2
strcpy(CPUInfo.strModel, "AMD 80486 DX2");
strcat(strCPUName, "AMD 80486 DX2");
break;
case 7: // Model = 7: 80486 write-back enhanced DX2
strcpy(CPUInfo.strModel, "AMD 80486 write-back enhanced DX2");
strcat(strCPUName, "AMD 80486 write-back enhanced DX2");
break;
case 8: // Model = 8: 80486 DX4
strcpy(CPUInfo.strModel, "AMD 80486 DX4");
strcat(strCPUName, "AMD 80486 DX4");
break;
case 9: // Model = 9: 80486 write-back enhanced DX4
strcpy(CPUInfo.strModel, "AMD 80486 write-back enhanced DX4");
strcat(strCPUName, "AMD 80486 write-back enhanced DX4");
break;
case 0xE: // Model = 0xE: 5x86
strcpy(CPUInfo.strModel, "AMD 5x86");
strcat(strCPUName, "AMD 5x86");
break;
case 0xF: // Model = 0xF: 5x86 write-back enhanced (oh my god.....)
strcpy(CPUInfo.strModel, "AMD 5x86 write-back enhanced");
strcat(strCPUName, "AMD 5x86 write-back enhanced");
break;
default: // ...
strcpy(CPUInfo.strModel, "Unknown AMD 80486 or 5x86 model");
strcat(strCPUName, "AMD 80486 or 5x86 (Unknown model)");
break;
}
break;
case 5: // Family = 5: K5 / K6 processor family