RISC-V without Ztso?

[kleinesfilmroellchen]

Since I couldn't find info on this in the docs, I wanted to ask directly: How do you work around the relaxed memory models of ARM and RISC-V, specifically RVMO? Since x86 provides TSO (Total Store Ordering), parallel applications will not run correctly unless box64 enforces a stricter memory model than what the ISA itself provides. Since RISC-V hardware with the Ztso extension (that provides hardware support for x86's memory model) doesn't exist yet (to my knowledge), how is it currently done? And what benefits could box64 get from leveraging Ztso support?

[ptitSeb]

There is a "strong model emulation" in box64, that can be enabled with BOX64_DYNAREC_STRONGMEM env. var. it's 0 by default (no tso emulation), because it's the fastest and many games just work fine with that, but can take value from 1 to 3. In that case, box64 will introduce memory barrier in sequence or read/write to simulate tso (roughly). Look in dynarec_rv64_helper.h with the SMDMB() macro for more details.
It's not perfect, but help run most things, with a reasonable loss of performances.