How do I measure I/D Cache Misses?

[HidetaroTanaka]

I want to measure I/D Cache Misses of CVA6+Ara, but i have no idea.

I tried to write mhpmevent3 and mhpmevent4 in apps/common/crt0.S like this:

    // Enable Vector Extension
    li      t0, (MSTATUS_VS & (MSTATUS_VS >> 1))
    csrs    mstatus, t0
    // Enable the counters
    csrsi   mcounteren, 1
    csrsi   scounteren, 1
++    // select performance counter events
++    csrwi mhpmevent3, 1
++    csrwi mhpmevent4, 2
    // Call the RISC-V Test initialization function, if it exists
    la t0, rvtest_init
    beqz t0, 1f
    jalr t0
1:  // Return to _eoc
    la      ra, _eoc
    // Call main
    la      t0, main
    csrw    mepc, t0
    mret

And the code is compiled like this:

800000a2: 93 02 00 20  	li	t0, 512
800000a6: 73 a0 02 30  	csrs	mstatus, t0
800000aa: 73 e0 60 30  	csrsi	mcounteren, 1
800000ae: 73 e0 60 10  	csrsi	scounteren, 1
800000b2: 73 d0 30 32  	csrwi	mhpmevent3, 1
800000b6: 73 50 41 32  	csrwi	mhpmevent4, 2
800000ba: 97 02 00 80  	auipc	t0, 524288
800000be: 93 82 62 f4  	addi	t0, t0, -186
800000c2: 63 83 02 00  	beqz	t0, 0x800000c8 <reset_vector+0xbe>
800000c6: 82 92        	jalr	t0
800000c8: 97 00 00 00  	auipc	ra, 0
800000cc: 93 80 00 03  	addi	ra, ra, 48
800000d0: 97 02 00 00  	auipc	t0, 0
800000d4: 93 82 82 04  	addi	t0, t0, 72
800000d8: 73 90 12 34  	csrw	mepc, t0
800000dc: 73 00 20 30  	mret	

but this code generates error below when I do RTL simulation with Verilator.

Simulation of Ara
=================


Simulation running, end by pressing CTRL-c.
[632] %Warning: ara_tb_verilator.sv:45: TOP.ara_tb_verilator: Core Test *** FAILED *** (tohost = 2)
- /home/hidetaro/github/ara/hardware/tb/ara_tb_verilator.sv:52: Verilog $finish
Received $finish() from Verilog, shutting down simulation.

Simulation statistics
=====================
Executed cycles:  13c
Wallclock time:   0.022 s
Simulation speed: 14363.6 cycles/s (14.3636 kHz)
make: *** [Makefile:210: simv] Error 2

Does this means that csrwi mhpmevent{3,4} causes illegal instruction exception? If so, does CVA6+Ara not support cache performance counters?

I read this CVA6 manual for reference of measuring Performance Counters.
https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_Performance_Counters.html

[HidetaroTanaka]

I forgot to mention, but the commit index of my pulled repo is ec0e379 (latest of main branch in Nov 28).

[mp-17]

Hello @HidetaroTanaka,

I am fixing a PR (#265) that will allow measuring d$ and i$ stalls also in the main branch :-)
In the meantime, you can have a look at this commit: 264c7bf

Let me know!
Matteo

[HidetaroTanaka]

Dear @mp-17

Thanks! I will have a look later.

Hidetaro