From 46bc380deb13474756e78ffc52ac8bcdb662b0f8 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Thu, 28 Jul 2022 18:45:58 +0200 Subject: [PATCH 01/50] dpi: Fix symlink Signed-off-by: Nils Wistoff --- hardware/tb/dpi/elfloader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/tb/dpi/elfloader.cc b/hardware/tb/dpi/elfloader.cc index 60f06c358..7e0528f54 120000 --- a/hardware/tb/dpi/elfloader.cc +++ b/hardware/tb/dpi/elfloader.cc @@ -1 +1 @@ -../../deps/cva6/tb/dpi/elfloader.cc \ No newline at end of file +../../deps/cva6/corev_apu/tb/dpi/elfloader.cc \ No newline at end of file From 936d5532575bb9f5a78ed26796680bbc6c9b369a Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 15 Nov 2022 19:00:13 +0100 Subject: [PATCH 02/50] ara_soc: Fix Ariane config param Signed-off-by: Nils Wistoff --- hardware/src/ara_soc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/src/ara_soc.sv b/hardware/src/ara_soc.sv index f65d37160..d1330d4ee 100644 --- a/hardware/src/ara_soc.sv +++ b/hardware/src/ara_soc.sv @@ -457,7 +457,7 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( CachedRegionAddrBase : {DRAMBase}, CachedRegionLength : {DRAMLength}, // cache config - Axi64BitCompliant : 1'b1, + AxiCompliant : 1'b1, SwapEndianess : 1'b0, // debug DmBaseAddress : 64'h0, From 428ad33089553a1936254fda324333d73e94852b Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 21 Dec 2022 02:44:45 +0100 Subject: [PATCH 03/50] tech_cells_generic: Bump Signed-off-by: Nils Wistoff --- hardware/Makefile | 2 +- hardware/deps/tech_cells_generic | 2 +- .../0001-tc_sram-Add-memory-preloader.patch | 78 ++++++++++++ .../0001-tech-cells-generic-sram.patch | 115 ------------------ 4 files changed, 80 insertions(+), 117 deletions(-) create mode 100644 hardware/patches/0001-tc_sram-Add-memory-preloader.patch delete mode 100644 hardware/patches/0001-tech-cells-generic-sram.patch diff --git a/hardware/Makefile b/hardware/Makefile index 0625fcc28..5dcb7ee8b 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -120,7 +120,7 @@ bender: # Patches .PHONY: apply-patches apply-patches: patches - cd deps/tech_cells_generic && git apply ../../patches/0001-tech-cells-generic-sram.patch + cd deps/tech_cells_generic && git apply ../../patches/0001-tc_sram-Add-memory-preloader.patch # Library .PHONY: lib diff --git a/hardware/deps/tech_cells_generic b/hardware/deps/tech_cells_generic index 203038f85..8283d6c02 160000 --- a/hardware/deps/tech_cells_generic +++ b/hardware/deps/tech_cells_generic @@ -1 +1 @@ -Subproject commit 203038f857158ae4634c47ce0281f402cc2a1344 +Subproject commit 8283d6c020d38a032f972988cfd79a952b54d309 diff --git a/hardware/patches/0001-tc_sram-Add-memory-preloader.patch b/hardware/patches/0001-tc_sram-Add-memory-preloader.patch new file mode 100644 index 000000000..296cf2609 --- /dev/null +++ b/hardware/patches/0001-tc_sram-Add-memory-preloader.patch @@ -0,0 +1,78 @@ +From cbf4f71b44a99176af037a0ed755fdf4d8c5e60b Mon Sep 17 00:00:00 2001 +From: Nils Wistoff +Date: Wed, 21 Dec 2022 02:42:01 +0100 +Subject: [PATCH] tc_sram: Add memory preloader + +Signed-off-by: Nils Wistoff +--- + src/rtl/tc_sram.sv | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 55 insertions(+) + +diff --git a/src/rtl/tc_sram.sv b/src/rtl/tc_sram.sv +index 91a29e7..a414dd9 100644 +--- a/src/rtl/tc_sram.sv ++++ b/src/rtl/tc_sram.sv +@@ -239,5 +239,60 @@ module tc_sram #( + + `endif + `endif ++ ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++/** ++ * Memory loader for simulation ++ * ++ * Include this file in a memory primitive to load a memory array from ++ * simulation. ++ * ++ * Requirements: ++ * - A memory array named `sram`. ++ * - A parameter `DataWidth` giving the memory width (word size) in bit. ++ * - A parameter `NumWords` giving the memory depth in words. ++ */ ++ ++`ifndef SYNTHESIS ++// Task for loading 'sram' with SystemVerilog system task $readmemh() ++export "DPI-C" task simutil_memload; ++ ++task simutil_memload; ++ input string file; ++ $readmemh(file, sram); ++endtask ++ ++// Function for setting a specific element in |sram| ++// Returns 1 (true) for success, 0 (false) for errors. ++export "DPI-C" function simutil_set_mem; ++function int simutil_set_mem(input int index, input bit [511:0] val); ++ // Function will only work for memories <= 512 bits ++ if (DataWidth > 512) ++ return 0; ++ if (index >= NumWords) ++ return 0; ++ ++ sram[index] = val[DataWidth-1:0]; ++ return 1; ++endfunction ++ ++// Function for getting a specific element in |sram| ++export "DPI-C" function simutil_get_mem; ++function int simutil_get_mem(input int index, output bit [511:0] val); ++ // Function will only work for memories <= 512 bits ++ if (DataWidth > 512) ++ return 0; ++ if (index >= NumWords) ++ return 0; ++ ++ val = 0; ++ val[DataWidth-1:0] = sram[index]; ++ return 1; ++endfunction ++`endif ++ + // pragma translate_on + endmodule +-- +2.16.5 + diff --git a/hardware/patches/0001-tech-cells-generic-sram.patch b/hardware/patches/0001-tech-cells-generic-sram.patch deleted file mode 100644 index dc1e1a99b..000000000 --- a/hardware/patches/0001-tech-cells-generic-sram.patch +++ /dev/null @@ -1,115 +0,0 @@ -diff --git a/src/rtl/tc_sram.sv b/src/rtl/tc_sram.sv -index 53530e0..075dcea 100644 ---- a/src/rtl/tc_sram.sv -+++ b/src/rtl/tc_sram.sv -@@ -124,9 +124,11 @@ module tc_sram #( - // write memory array - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin -+ `ifndef VERILATOR - for (int unsigned i = 0; i < NumWords; i++) begin - sram[i] <= init_val[i]; - end -+ `endif - for (int i = 0; i < NumPorts; i++) begin - r_addr_q[i] <= {AddrWidth{1'b0}}; - // initialize the read output register for each port -@@ -149,12 +151,14 @@ module tc_sram #( - for (int unsigned i = 0; i < NumPorts; i++) begin - if (req_i[i]) begin - if (we_i[i]) begin -+ `ifndef VERILATOR - // update value when write is set at clock - for (int unsigned j = 0; j < DataWidth; j++) begin - if (be_i[i][j/ByteWidth]) begin - sram[addr_i[i]][j] <= wdata_i[i][j]; - end - end -+ `endif - end else begin - // otherwise update read address for subsequent non request cycles - r_addr_q[i] <= addr_i[i]; -@@ -164,6 +168,23 @@ module tc_sram #( - end // if !rst_ni - end - -+ `ifdef VERILATOR -+ for (genvar i = 0; i < NumPorts; i++) begin -+ // update value when write is set at clock -+ for (genvar j = 0; j < DataWidth; j++) begin -+ always_ff @(posedge clk_i or negedge rst_ni) begin -+ if (!rst_ni) begin -+ end else begin -+ if (req_i[i]) -+ if (we_i[i]) -+ if (be_i[i][j/ByteWidth]) -+ sram[addr_i[i]][j] <= wdata_i[i][j]; -+ end -+ end -+ end -+ end -+ `endif -+ - // Validate parameters. - // pragma translate_off - `ifndef VERILATOR -@@ -204,4 +225,59 @@ module tc_sram #( - `endif - `endif - // pragma translate_on -+ -+ // Copyright lowRISC contributors. -+ // Licensed under the Apache License, Version 2.0, see LICENSE for details. -+ // SPDX-License-Identifier: Apache-2.0 -+ -+ /** -+ * Memory loader for simulation -+ * -+ * Include this file in a memory primitive to load a memory array from -+ * simulation. -+ * -+ * Requirements: -+ * - A memory array named `sram`. -+ * - A parameter `DataWidth` giving the memory width (word size) in bit. -+ * - A parameter `NumWords` giving the memory depth in words. -+ */ -+ -+ `ifndef SYNTHESIS -+ // Task for loading 'sram' with SystemVerilog system task $readmemh() -+ export "DPI-C" task simutil_memload; -+ -+ task simutil_memload; -+ input string file; -+ $readmemh(file, sram); -+ endtask -+ -+ // Function for setting a specific element in |sram| -+ // Returns 1 (true) for success, 0 (false) for errors. -+ export "DPI-C" function simutil_set_mem; -+ function int simutil_set_mem(input int index, input bit [511:0] val); -+ // Function will only work for memories <= 512 bits -+ if (DataWidth > 512) -+ return 0; -+ if (index >= NumWords) -+ return 0; -+ -+ sram[index] = val[DataWidth-1:0]; -+ return 1; -+ endfunction -+ -+ // Function for getting a specific element in |sram| -+ export "DPI-C" function simutil_get_mem; -+ function int simutil_get_mem(input int index, output bit [511:0] val); -+ // Function will only work for memories <= 512 bits -+ if (DataWidth > 512) -+ return 0; -+ if (index >= NumWords) -+ return 0; -+ -+ val = 0; -+ val[DataWidth-1:0] = sram[index]; -+ return 1; -+ endfunction -+ `endif -+ - endmodule From 01f946dc8611e75d414d2b601e55a5cb482b2e9f Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 21 Dec 2022 03:01:35 +0100 Subject: [PATCH 04/50] Makefile: Demote verilate warnings Signed-off-by: Nils Wistoff --- hardware/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hardware/Makefile b/hardware/Makefile index 5dcb7ee8b..1ade80a81 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -169,6 +169,8 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi $(veril_path)/verilator -f $(veril_library)/bender_script_$(config) \ -GNrLanes=$(nr_lanes) \ -O3 \ + -Wno-fatal \ + -Wno-PINCONNECTEMPTY \ -Wno-BLKANDNBLK \ -Wno-CASEINCOMPLETE \ -Wno-CMPCONST \ @@ -180,7 +182,9 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi -Wno-WIDTH \ -Wno-WIDTHCONCAT \ -Wno-ENUMVALUE \ - -Wno-COMBDLY \ + -Wno-COMBDLY + \ + -Wall \ --hierarchical \ tb/verilator/waiver.vlt \ --Mdir $(veril_library) \ From fe315c1b87a61d16edf4fa1afc6858e260981322 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 21 Dec 2022 03:42:05 +0100 Subject: [PATCH 05/50] ara_system: Propatage AXI parameters to CVA6 Signed-off-by: Nils Wistoff --- hardware/src/ara_system.sv | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hardware/src/ara_system.sv b/hardware/src/ara_system.sv index f8c32d44e..16d480def 100644 --- a/hardware/src/ara_system.sv +++ b/hardware/src/ara_system.sv @@ -106,7 +106,14 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( ); `else ariane #( - .ArianeCfg(ArianeCfg) + .ArianeCfg(ArianeCfg), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiNarrowDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .axi_ar_chan_t (ariane_axi_ar_t), + .axi_aw_chan_t (ariane_axi_aw_t), + .axi_req_t (ariane_axi_req_t), + .axi_rsp_t (ariane_axi_resp_t) ) i_ariane ( .clk_i (clk_i ), .rst_ni (rst_ni ), From f4c75ff81391d0579ba2c288a33846e643f5998f Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Wed, 21 Dec 2022 18:53:14 +0100 Subject: [PATCH 06/50] Revert "tech_cells_generic: Bump" This reverts commit 304e4f8b333a0904d1fbf2548c881569cf1c4d26. --- hardware/Makefile | 2 +- hardware/deps/tech_cells_generic | 2 +- .../0001-tc_sram-Add-memory-preloader.patch | 78 ------------ .../0001-tech-cells-generic-sram.patch | 115 ++++++++++++++++++ 4 files changed, 117 insertions(+), 80 deletions(-) delete mode 100644 hardware/patches/0001-tc_sram-Add-memory-preloader.patch create mode 100644 hardware/patches/0001-tech-cells-generic-sram.patch diff --git a/hardware/Makefile b/hardware/Makefile index 1ade80a81..752da3579 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -120,7 +120,7 @@ bender: # Patches .PHONY: apply-patches apply-patches: patches - cd deps/tech_cells_generic && git apply ../../patches/0001-tc_sram-Add-memory-preloader.patch + cd deps/tech_cells_generic && git apply ../../patches/0001-tech-cells-generic-sram.patch # Library .PHONY: lib diff --git a/hardware/deps/tech_cells_generic b/hardware/deps/tech_cells_generic index 8283d6c02..203038f85 160000 --- a/hardware/deps/tech_cells_generic +++ b/hardware/deps/tech_cells_generic @@ -1 +1 @@ -Subproject commit 8283d6c020d38a032f972988cfd79a952b54d309 +Subproject commit 203038f857158ae4634c47ce0281f402cc2a1344 diff --git a/hardware/patches/0001-tc_sram-Add-memory-preloader.patch b/hardware/patches/0001-tc_sram-Add-memory-preloader.patch deleted file mode 100644 index 296cf2609..000000000 --- a/hardware/patches/0001-tc_sram-Add-memory-preloader.patch +++ /dev/null @@ -1,78 +0,0 @@ -From cbf4f71b44a99176af037a0ed755fdf4d8c5e60b Mon Sep 17 00:00:00 2001 -From: Nils Wistoff -Date: Wed, 21 Dec 2022 02:42:01 +0100 -Subject: [PATCH] tc_sram: Add memory preloader - -Signed-off-by: Nils Wistoff ---- - src/rtl/tc_sram.sv | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 55 insertions(+) - -diff --git a/src/rtl/tc_sram.sv b/src/rtl/tc_sram.sv -index 91a29e7..a414dd9 100644 ---- a/src/rtl/tc_sram.sv -+++ b/src/rtl/tc_sram.sv -@@ -239,5 +239,60 @@ module tc_sram #( - - `endif - `endif -+ -+// Copyright lowRISC contributors. -+// Licensed under the Apache License, Version 2.0, see LICENSE for details. -+// SPDX-License-Identifier: Apache-2.0 -+ -+/** -+ * Memory loader for simulation -+ * -+ * Include this file in a memory primitive to load a memory array from -+ * simulation. -+ * -+ * Requirements: -+ * - A memory array named `sram`. -+ * - A parameter `DataWidth` giving the memory width (word size) in bit. -+ * - A parameter `NumWords` giving the memory depth in words. -+ */ -+ -+`ifndef SYNTHESIS -+// Task for loading 'sram' with SystemVerilog system task $readmemh() -+export "DPI-C" task simutil_memload; -+ -+task simutil_memload; -+ input string file; -+ $readmemh(file, sram); -+endtask -+ -+// Function for setting a specific element in |sram| -+// Returns 1 (true) for success, 0 (false) for errors. -+export "DPI-C" function simutil_set_mem; -+function int simutil_set_mem(input int index, input bit [511:0] val); -+ // Function will only work for memories <= 512 bits -+ if (DataWidth > 512) -+ return 0; -+ if (index >= NumWords) -+ return 0; -+ -+ sram[index] = val[DataWidth-1:0]; -+ return 1; -+endfunction -+ -+// Function for getting a specific element in |sram| -+export "DPI-C" function simutil_get_mem; -+function int simutil_get_mem(input int index, output bit [511:0] val); -+ // Function will only work for memories <= 512 bits -+ if (DataWidth > 512) -+ return 0; -+ if (index >= NumWords) -+ return 0; -+ -+ val = 0; -+ val[DataWidth-1:0] = sram[index]; -+ return 1; -+endfunction -+`endif -+ - // pragma translate_on - endmodule --- -2.16.5 - diff --git a/hardware/patches/0001-tech-cells-generic-sram.patch b/hardware/patches/0001-tech-cells-generic-sram.patch new file mode 100644 index 000000000..dc1e1a99b --- /dev/null +++ b/hardware/patches/0001-tech-cells-generic-sram.patch @@ -0,0 +1,115 @@ +diff --git a/src/rtl/tc_sram.sv b/src/rtl/tc_sram.sv +index 53530e0..075dcea 100644 +--- a/src/rtl/tc_sram.sv ++++ b/src/rtl/tc_sram.sv +@@ -124,9 +124,11 @@ module tc_sram #( + // write memory array + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin ++ `ifndef VERILATOR + for (int unsigned i = 0; i < NumWords; i++) begin + sram[i] <= init_val[i]; + end ++ `endif + for (int i = 0; i < NumPorts; i++) begin + r_addr_q[i] <= {AddrWidth{1'b0}}; + // initialize the read output register for each port +@@ -149,12 +151,14 @@ module tc_sram #( + for (int unsigned i = 0; i < NumPorts; i++) begin + if (req_i[i]) begin + if (we_i[i]) begin ++ `ifndef VERILATOR + // update value when write is set at clock + for (int unsigned j = 0; j < DataWidth; j++) begin + if (be_i[i][j/ByteWidth]) begin + sram[addr_i[i]][j] <= wdata_i[i][j]; + end + end ++ `endif + end else begin + // otherwise update read address for subsequent non request cycles + r_addr_q[i] <= addr_i[i]; +@@ -164,6 +168,23 @@ module tc_sram #( + end // if !rst_ni + end + ++ `ifdef VERILATOR ++ for (genvar i = 0; i < NumPorts; i++) begin ++ // update value when write is set at clock ++ for (genvar j = 0; j < DataWidth; j++) begin ++ always_ff @(posedge clk_i or negedge rst_ni) begin ++ if (!rst_ni) begin ++ end else begin ++ if (req_i[i]) ++ if (we_i[i]) ++ if (be_i[i][j/ByteWidth]) ++ sram[addr_i[i]][j] <= wdata_i[i][j]; ++ end ++ end ++ end ++ end ++ `endif ++ + // Validate parameters. + // pragma translate_off + `ifndef VERILATOR +@@ -204,4 +225,59 @@ module tc_sram #( + `endif + `endif + // pragma translate_on ++ ++ // Copyright lowRISC contributors. ++ // Licensed under the Apache License, Version 2.0, see LICENSE for details. ++ // SPDX-License-Identifier: Apache-2.0 ++ ++ /** ++ * Memory loader for simulation ++ * ++ * Include this file in a memory primitive to load a memory array from ++ * simulation. ++ * ++ * Requirements: ++ * - A memory array named `sram`. ++ * - A parameter `DataWidth` giving the memory width (word size) in bit. ++ * - A parameter `NumWords` giving the memory depth in words. ++ */ ++ ++ `ifndef SYNTHESIS ++ // Task for loading 'sram' with SystemVerilog system task $readmemh() ++ export "DPI-C" task simutil_memload; ++ ++ task simutil_memload; ++ input string file; ++ $readmemh(file, sram); ++ endtask ++ ++ // Function for setting a specific element in |sram| ++ // Returns 1 (true) for success, 0 (false) for errors. ++ export "DPI-C" function simutil_set_mem; ++ function int simutil_set_mem(input int index, input bit [511:0] val); ++ // Function will only work for memories <= 512 bits ++ if (DataWidth > 512) ++ return 0; ++ if (index >= NumWords) ++ return 0; ++ ++ sram[index] = val[DataWidth-1:0]; ++ return 1; ++ endfunction ++ ++ // Function for getting a specific element in |sram| ++ export "DPI-C" function simutil_get_mem; ++ function int simutil_get_mem(input int index, output bit [511:0] val); ++ // Function will only work for memories <= 512 bits ++ if (DataWidth > 512) ++ return 0; ++ if (index >= NumWords) ++ return 0; ++ ++ val = 0; ++ val[DataWidth-1:0] = sram[index]; ++ return 1; ++ endfunction ++ `endif ++ + endmodule From 3030882a73ecf5dc71c23f60f7297e145e1d15e3 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Fri, 23 Dec 2022 19:52:12 +0100 Subject: [PATCH 07/50] hw/Makefile: Update CVA6 target and defines Signed-off-by: Nils Wistoff --- hardware/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hardware/Makefile b/hardware/Makefile index 752da3579..a3c08784c 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -102,7 +102,7 @@ vlog_args += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 vlog_args += -work $(library) # Defines -bender_defs += --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen) --define RVV_ARIANE=1 +bender_defs += --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen) --define ARIANE_ACCELERATOR_PORT=1 # Default target all: compile @@ -132,7 +132,7 @@ $(buildpath)/$(library): .PHONY: compile compile: dpi lib $(buildpath) bender $(buildpath)/compile_$(config).tcl $(buildpath)/compile_$(config).tcl: $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) - ./bender script vsim --vlog-arg="$(vlog_args)" -t rtl -t asic -t ara_test -t cva6_test $(bender_defs) > $(buildpath)/compile_$(config).tcl + ./bender script vsim --vlog-arg="$(vlog_args)" -t rtl -t asic -t ara_test -t cva6_test -t cv64a6v $(bender_defs) > $(buildpath)/compile_$(config).tcl echo "exit" >> $(buildpath)/compile_$(config).tcl cd $(buildpath) && $(questa_cmd) vsim -work $(library) -c -do compile_$(config).tcl # Remove the file if compilation did not succeed @@ -164,7 +164,7 @@ verilate: $(buildpath) bender $(veril_library)/V$(veril_top) $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) rm -rf $(veril_library); mkdir -p $(veril_library) - ./bender script verilator -t rtl -t ara_test -t cva6_test -t verilator $(bender_defs) > $(veril_library)/bender_script_$(config) + ./bender script verilator -t rtl -t ara_test -t cva6_test -t cv64a6v -t verilator $(bender_defs) > $(veril_library)/bender_script_$(config) # Verilate the design $(veril_path)/verilator -f $(veril_library)/bender_script_$(config) \ -GNrLanes=$(nr_lanes) \ @@ -228,7 +228,7 @@ lint: spyglass/tmp/files spyglass/sdc/func.sdc spyglass/scripts/run_lint.tcl spyglass/tmp/files: $(bender) mkdir -p spyglass/tmp - ./bender script verilator -t rtl -t spyglass -t cva6_test $(bender_defs) --define SPYGLASS > spyglass/tmp/files + ./bender script verilator -t rtl -t spyglass -t cva6_test -t cv64a6v $(bender_defs) --define SPYGLASS > spyglass/tmp/files # DPIs .PHONY: dpi From 55b1bf7a7fdd43a5364e5336913715d731c758a9 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Tue, 10 Jan 2023 13:53:05 +0100 Subject: [PATCH 08/50] [scripts] Increase HW-SW cycle check delta CVA6 bump made some checks fail with the restrictive 300 cycles threshold --- scripts/check_cycles.py | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/scripts/check_cycles.py b/scripts/check_cycles.py index 7b7040c07..24a861d1a 100644 --- a/scripts/check_cycles.py +++ b/scripts/check_cycles.py @@ -24,19 +24,19 @@ import numpy as np threshold = { - 'imatmul' : 300, - 'fmatmul' : 300, - 'iconv2d' : 300, - 'fconv2d' : 300, - 'fconv3d' : 300, - 'jacobi2d' : 300, - 'dropout' : 300, - 'fft' : 300, - 'dwt' : 300, - 'exp' : 300, - 'softmax' : 300, - 'pathfinder' : 300, - 'roi_align' : 300, + 'imatmul' : 500, + 'fmatmul' : 500, + 'iconv2d' : 500, + 'fconv2d' : 500, + 'fconv3d' : 500, + 'jacobi2d' : 500, + 'dropout' : 500, + 'fft' : 500, + 'dwt' : 500, + 'exp' : 500, + 'softmax' : 500, + 'pathfinder' : 500, + 'roi_align' : 500, } skip_check = { From 8e66ed22141fd558c96b677175d71486315877f1 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 16 May 2023 09:47:33 +0200 Subject: [PATCH 09/50] cva6: Bump Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index bebbc1475..3fddb6e58 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit bebbc1475f9ffba661e8354d8773e27ab9338db1 +Subproject commit 3fddb6e5814604c7ec49e4320de0037292346c63 From 5cc30cf41e8c9c5a780e08017b7b5183fbe1138b Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 16 May 2023 10:50:49 +0200 Subject: [PATCH 10/50] hw/Makefile: Update CVA6 target Signed-off-by: Nils Wistoff --- hardware/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hardware/Makefile b/hardware/Makefile index a3c08784c..674919386 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -132,7 +132,7 @@ $(buildpath)/$(library): .PHONY: compile compile: dpi lib $(buildpath) bender $(buildpath)/compile_$(config).tcl $(buildpath)/compile_$(config).tcl: $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) - ./bender script vsim --vlog-arg="$(vlog_args)" -t rtl -t asic -t ara_test -t cva6_test -t cv64a6v $(bender_defs) > $(buildpath)/compile_$(config).tcl + ./bender script vsim --vlog-arg="$(vlog_args)" -t rtl -t asic -t ara_test -t cva6_test -t cv64a6_imafdcv_sv39 $(bender_defs) > $(buildpath)/compile_$(config).tcl echo "exit" >> $(buildpath)/compile_$(config).tcl cd $(buildpath) && $(questa_cmd) vsim -work $(library) -c -do compile_$(config).tcl # Remove the file if compilation did not succeed @@ -164,7 +164,7 @@ verilate: $(buildpath) bender $(veril_library)/V$(veril_top) $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) rm -rf $(veril_library); mkdir -p $(veril_library) - ./bender script verilator -t rtl -t ara_test -t cva6_test -t cv64a6v -t verilator $(bender_defs) > $(veril_library)/bender_script_$(config) + ./bender script verilator -t rtl -t ara_test -t cva6_test -t cv64a6_imafdcv_sv39 -t verilator $(bender_defs) > $(veril_library)/bender_script_$(config) # Verilate the design $(veril_path)/verilator -f $(veril_library)/bender_script_$(config) \ -GNrLanes=$(nr_lanes) \ @@ -228,7 +228,7 @@ lint: spyglass/tmp/files spyglass/sdc/func.sdc spyglass/scripts/run_lint.tcl spyglass/tmp/files: $(bender) mkdir -p spyglass/tmp - ./bender script verilator -t rtl -t spyglass -t cva6_test -t cv64a6v $(bender_defs) --define SPYGLASS > spyglass/tmp/files + ./bender script verilator -t rtl -t spyglass -t cva6_test -t cv64a6_imafdcv_sv39 $(bender_defs) --define SPYGLASS > spyglass/tmp/files # DPIs .PHONY: dpi From e8a3d91981a463211dd81537416cd33eab73eda2 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 16 May 2023 11:06:19 +0200 Subject: [PATCH 11/50] Bender.yml: Update cva6 rev Signed-off-by: Nils Wistoff --- Bender.lock | 64 ++++++++++++++++++++++++++++++++++------------------- Bender.yml | 2 +- 2 files changed, 42 insertions(+), 24 deletions(-) diff --git a/Bender.lock b/Bender.lock index fc78b497e..70a365310 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,4 +1,3 @@ ---- packages: apb: revision: 77ddf073f194d44b9119949d2421be59789e69ae @@ -7,38 +6,57 @@ packages: Git: https://github.com/pulp-platform/apb.git dependencies: - common_cells + ariane: + revision: 3fddb6e5814604c7ec49e4320de0037292346c63 + version: null + source: + Git: https://github.com/pulp-platform/cva6.git + dependencies: + - axi + - common_cells + - fpnew + - tech_cells_generic axi: - revision: 442ff3375710513623f95944d66cc2bd09b2f155 - version: 0.29.1 + revision: null + version: null source: - Git: "https://github.com/pulp-platform/axi.git" + Path: hardware/deps/axi dependencies: - - common_cells - - common_verification + - common_cells + - common_verification common_cells: - revision: 015917ff33e5f944e866814f72f2074fb0f4220f - version: 1.22.1 + revision: null + version: null source: - Git: "https://github.com/pulp-platform/common_cells.git" + Path: hardware/deps/common_cells dependencies: - - common_verification - - tech_cells_generic + - common_verification + - tech_cells_generic common_verification: - revision: 6fc76fb013315af9fabbb90b431863d498df2d6d - version: 0.2.0 + revision: null + version: null source: - Git: "https://github.com/pulp-platform/common_verification.git" + Path: hardware/deps/common_verification dependencies: [] - cva6: - revision: 3245e44ec49c1cdcd19eb298cd81f0672eaf81ca - version: ~ + fpnew: + revision: 3116391bf66660f806b45e212b9949c528b4e270 + version: 0.7.0 source: - Git: "https://github.com/pulp-platform/cva6.git" - dependencies: [] + Git: https://github.com/openhwgroup/cvfpu.git + dependencies: + - common_cells + - fpu_div_sqrt_mvp + fpu_div_sqrt_mvp: + revision: 86e1f558b3c95e91577c41b2fc452c86b04e85ac + version: 1.0.4 + source: + Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git + dependencies: + - common_cells tech_cells_generic: - revision: 203038f857158ae4634c47ce0281f402cc2a1344 - version: 0.2.4 + revision: null + version: null source: - Git: "https://github.com/pulp-platform/tech_cells_generic.git" + Path: hardware/deps/tech_cells_generic dependencies: - - common_verification \ No newline at end of file + - common_verification diff --git a/Bender.yml b/Bender.yml index 051313258..a236809c5 100644 --- a/Bender.yml +++ b/Bender.yml @@ -10,7 +10,7 @@ package: dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } - cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: acc_port } + ariane: { git: "https://github.com/pulp-platform/cva6.git", rev: acc_port_rerebase } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.1 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } From 952e14b5eeced7ee197ee653af582990a61fb473 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 17 May 2023 13:56:53 +0200 Subject: [PATCH 12/50] vmfpu: Remove unavailable fpnew ports Signed-off-by: Nils Wistoff --- hardware/src/lane/vmfpu.sv | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hardware/src/lane/vmfpu.sv b/hardware/src/lane/vmfpu.sv index c00844552..bf5511eef 100644 --- a/hardware/src/lane/vmfpu.sv +++ b/hardware/src/lane/vmfpu.sv @@ -983,9 +983,7 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*; .Features (FPUFeatures ), .Implementation(FPUImplementation), .TagType (strb_t ), - .NumLanes (FPULanes ), - .TrueSIMDClass (TrueSIMDClass ), - .MaskType (fpu_mask_t ) + .TrueSIMDClass (TrueSIMDClass ) ) i_fpnew_bulk ( .clk_i (clk_i ), .rst_ni (rst_ni ), From 4c3f1d61a43b23dcf31ab9f9999c06ed79fc1d53 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 17 May 2023 16:05:32 +0200 Subject: [PATCH 13/50] ara_soc: Upgrade axi to apb axi2apb_64_32 has been deprecated. Replace it by the up-to-date axi and apb IPs. Signed-off-by: Nils Wistoff --- Bender.lock | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Bender.lock b/Bender.lock index 70a365310..6e31bf78e 100644 --- a/Bender.lock +++ b/Bender.lock @@ -16,6 +16,13 @@ packages: - common_cells - fpnew - tech_cells_generic + apb: + revision: 77ddf073f194d44b9119949d2421be59789e69ae + version: 0.2.4 + source: + Git: https://github.com/pulp-platform/apb.git + dependencies: + - common_cells axi: revision: null version: null From 1614913dbf815d06685aa0674e04499878bce353 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 17 May 2023 23:14:49 +0200 Subject: [PATCH 14/50] cva6: Bump Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 3fddb6e58..0578fc259 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 3fddb6e5814604c7ec49e4320de0037292346c63 +Subproject commit 0578fc2591565d723b91923dd512027b35a1112a From d0132e893fa6731e87ed96a148940c79165da5e9 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 17 May 2023 23:15:47 +0200 Subject: [PATCH 15/50] Bender.yml: Rename package ariane to cva6 Signed-off-by: Nils Wistoff --- Bender.lock | 1 + Bender.yml | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Bender.lock b/Bender.lock index 6e31bf78e..d25f39744 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,6 +7,7 @@ packages: dependencies: - common_cells ariane: + cva6: revision: 3fddb6e5814604c7ec49e4320de0037292346c63 version: null source: diff --git a/Bender.yml b/Bender.yml index a236809c5..dd9f182aa 100644 --- a/Bender.yml +++ b/Bender.yml @@ -10,7 +10,7 @@ package: dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } - ariane: { git: "https://github.com/pulp-platform/cva6.git", rev: acc_port_rerebase } + cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: acc_port_rerebase } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.1 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } From de5f0f05651843b92a03ba203c8a13f6d4b27119 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 17 Mar 2023 11:24:32 +0100 Subject: [PATCH 16/50] [hardware] Adapt vmfpu module Signed-off-by: Nils Wistoff --- hardware/src/lane/vmfpu.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hardware/src/lane/vmfpu.sv b/hardware/src/lane/vmfpu.sv index bf5511eef..544225b04 100644 --- a/hardware/src/lane/vmfpu.sv +++ b/hardware/src/lane/vmfpu.sv @@ -782,7 +782,8 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*; }; // Don't compress classify result - localparam int unsigned TrueSIMDClass = 1; + localparam int unsigned TrueSIMDClass = 1; + localparam int unsigned EnableSIMDMask = 1; operation_e fp_op; logic fp_opmod; @@ -983,7 +984,8 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*; .Features (FPUFeatures ), .Implementation(FPUImplementation), .TagType (strb_t ), - .TrueSIMDClass (TrueSIMDClass ) + .TrueSIMDClass (TrueSIMDClass ), + .EnableSIMDMask(EnableSIMDMask ) ) i_fpnew_bulk ( .clk_i (clk_i ), .rst_ni (rst_ni ), From 8d2fcdf360512b748d3f282a00fdb27637d036f5 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Fri, 16 Jun 2023 18:32:09 +0200 Subject: [PATCH 17/50] cva6: Bump Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 0578fc259..442fb4a5d 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 0578fc2591565d723b91923dd512027b35a1112a +Subproject commit 442fb4a5dc0cfe1d3e315579f3c73569a9a725c3 From 8e66e504d5e90a94ba8da1ee8250998262ac55e6 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Sun, 18 Jun 2023 20:49:59 +0200 Subject: [PATCH 18/50] cva6: Bump (remove stall signls) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 442fb4a5d..f4a4811f6 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 442fb4a5dc0cfe1d3e315579f3c73569a9a725c3 +Subproject commit f4a4811f62882a504cc299e79b1521ba1a2a6e0a From 2f4e87cf437e46c24109b1c5edc74ad6b5ddd308 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Mon, 19 Jun 2023 00:10:28 +0200 Subject: [PATCH 19/50] cva6: Bump (move accel_disp and merge commit) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index f4a4811f6..1a04b437d 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit f4a4811f62882a504cc299e79b1521ba1a2a6e0a +Subproject commit 1a04b437dde32a81a97f1a1a7f7b7830eca9a5d6 From cc8c945f56c1dcad374639b64da5109beaf5e553 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Mon, 19 Jun 2023 11:54:28 +0200 Subject: [PATCH 20/50] cva6: Bump (merge ctrl) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 1a04b437d..c430de57a 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 1a04b437dde32a81a97f1a1a7f7b7830eca9a5d6 +Subproject commit c430de57abc111345b917986eb82e9e996b42eda From c6edd3d1299cb4fb8d8f61a231c8cb55fc7447e3 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Mon, 19 Jun 2023 23:12:43 +0200 Subject: [PATCH 21/50] scripts/wave_core.tcl: Update CVA6 module hierarchy Signed-off-by: Nils Wistoff --- hardware/scripts/wave_core.tcl | 85 +++++++++++++++++----------------- 1 file changed, 43 insertions(+), 42 deletions(-) diff --git a/hardware/scripts/wave_core.tcl b/hardware/scripts/wave_core.tcl index 7f0434ad7..c22e20281 100644 --- a/hardware/scripts/wave_core.tcl +++ b/hardware/scripts/wave_core.tcl @@ -4,61 +4,62 @@ # # Author: Matheus Cavalcante -add wave -noupdate -group CVA6 -group core /ara_tb/dut/i_ara_soc/i_system/i_ariane/* +add wave -noupdate -group CVA6 -group core /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/* -add wave -noupdate -group CVA6 -group frontend /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/* -add wave -noupdate -group CVA6 -group frontend -group icache /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cache_subsystem/i_cva6_icache/* -add wave -noupdate -group CVA6 -group frontend -group ras /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_ras/* -add wave -noupdate -group CVA6 -group frontend -group btb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_btb/* -add wave -noupdate -group CVA6 -group frontend -group bht /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_bht/* -# add wave -noupdate -group CVA6 -group frontend -group instr_scan /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/*/i_instr_scan/* -# add wave -noupdate -group CVA6 -group frontend -group fetch_fifo /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_fetch_fifo/* +add wave -noupdate -group CVA6 -group frontend /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/* +add wave -noupdate -group CVA6 -group frontend -group icache /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_cva6_icache/* +# add wave -noupdate -group CVA6 -group frontend -group ras /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_ras/* +# add wave -noupdate -group CVA6 -group frontend -group btb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_btb/* +# add wave -noupdate -group CVA6 -group frontend -group bht /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_bht/* +# add wave -noupdate -group CVA6 -group frontend -group instr_scan /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/*/i_instr_scan/* +# add wave -noupdate -group CVA6 -group frontend -group fetch_fifo /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_fetch_fifo/* -add wave -noupdate -group CVA6 -group id_stage -group decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/id_stage_i/decoder_i/* -add wave -noupdate -group CVA6 -group id_stage -group compressed_decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/id_stage_i/compressed_decoder_i/* -add wave -noupdate -group CVA6 -group id_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/id_stage_i/* +add wave -noupdate -group CVA6 -group id_stage -group decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/id_stage_i/decoder_i/* +add wave -noupdate -group CVA6 -group id_stage -group compressed_decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/id_stage_i/genblk1/compressed_decoder_i/* +add wave -noupdate -group CVA6 -group id_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/id_stage_i/* -add wave -noupdate -group CVA6 -group issue_stage -group scoreboard /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/i_scoreboard/* -add wave -noupdate -group CVA6 -group issue_stage -group issue_read_operands /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/i_issue_read_operands/* -add wave -noupdate -group CVA6 -group issue_stage -group rename /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/i_re_name/* -add wave -noupdate -group CVA6 -group issue_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/* +add wave -noupdate -group CVA6 -group issue_stage -group scoreboard /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/i_scoreboard/* +add wave -noupdate -group CVA6 -group issue_stage -group issue_read_operands /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/* +add wave -noupdate -group CVA6 -group issue_stage -group rename /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/i_re_name/* +add wave -noupdate -group CVA6 -group issue_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/* -add wave -noupdate -group CVA6 -group ex_stage -group alu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/alu_i/* -add wave -noupdate -group CVA6 -group ex_stage -group mult /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/i_mult/* -add wave -noupdate -group CVA6 -group ex_stage -group mult -group mul /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/i_mult/i_multiplier/* -add wave -noupdate -group CVA6 -group ex_stage -group mult -group div /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/i_mult/i_div/* -add wave -noupdate -group CVA6 -group ex_stage -group fpu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/fpu_gen/fpu_i/* -add wave -noupdate -group CVA6 -group ex_stage -group fpu -group fpnew /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_gen/i_fpnew_bulk/* +add wave -noupdate -group CVA6 -group ex_stage -group alu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/alu_i/* +add wave -noupdate -group CVA6 -group ex_stage -group mult /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/i_mult/* +add wave -noupdate -group CVA6 -group ex_stage -group mult -group mul /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/* +add wave -noupdate -group CVA6 -group ex_stage -group mult -group div /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/i_mult/i_div/* +add wave -noupdate -group CVA6 -group ex_stage -group fpu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/fpu_gen/fpu_i/* +add wave -noupdate -group CVA6 -group ex_stage -group fpu -group fpnew /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/fpu_gen/fpu_i/fpu_gen/i_fpnew_bulk/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group lsu_bypass /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/lsu_bypass_i/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_mmu/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group itlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_mmu/i_itlb/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group dtlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_mmu/i_dtlb/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group ptw /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_mmu/i_ptw/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group lsu_bypass /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/lsu_bypass_i/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group itlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_itlb/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group dtlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_dtlb/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group ptw /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_ptw/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_store_unit/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit -group store_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_store_unit/store_buffer_i/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/i_store_unit/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit -group store_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/i_store_unit/store_buffer_i/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group load_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_load_unit/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group load_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/* -add wave -noupdate -group CVA6 -group ex_stage -group branch_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/branch_unit_i/* +add wave -noupdate -group CVA6 -group ex_stage -group branch_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/branch_unit_i/* -add wave -noupdate -group CVA6 -group ex_stage -group csr_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/csr_buffer_i/* +add wave -noupdate -group CVA6 -group ex_stage -group csr_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/csr_buffer_i/* -add wave -noupdate -group CVA6 -group ex_stage -group dispatcher /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/gen_accelerator/i_acc_dispatcher/* -add wave -noupdate -group CVA6 -group ex_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/* +add wave -noupdate -group CVA6 -group ex_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/* -add wave -noupdate -group CVA6 -group commit_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/commit_stage_i/* +add wave -noupdate -group CVA6 -group commit_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/commit_stage_i/* -add wave -noupdate -group CVA6 -group csr_file /ara_tb/dut/i_ara_soc/i_system/i_ariane/csr_regfile_i/* +add wave -noupdate -group CVA6 -group csr_file /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/csr_regfile_i/* -add wave -noupdate -group CVA6 -group controller /ara_tb/dut/i_ara_soc/i_system/i_ariane/controller_i/* +add wave -noupdate -group CVA6 -group controller /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/controller_i/* -add wave -noupdate -group CVA6 -group wt_dcache /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cache_subsystem/i_wt_dcache/* -add wave -noupdate -group CVA6 -group wt_dcache -group miss_handler /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cache_subsystem/i_wt_dcache/i_wt_dcache_missunit/* +add wave -noupdate -group CVA6 -group wt_dcache /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/* +add wave -noupdate -group CVA6 -group wt_dcache -group miss_handler /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/i_wt_dcache_missunit/* -add wave -noupdate -group CVA6 -group wt_dcache -group load {/ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cache_subsystem/i_wt_dcache/gen_rd_ports[0]/i_wt_dcache_ctrl/*} -add wave -noupdate -group CVA6 -group wt_dcache -group ptw {/ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cache_subsystem/i_wt_dcache/gen_rd_ports[1]/i_wt_dcache_ctrl/*} +add wave -noupdate -group CVA6 -group wt_dcache -group load {/ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[0]/i_wt_dcache_ctrl/*} +add wave -noupdate -group CVA6 -group wt_dcache -group ptw {/ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[1]/i_wt_dcache_ctrl/*} -add wave -noupdate -group CVA6 -group perf_counters /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_perf_counters/* +add wave -noupdate -group CVA6 -group dispatcher /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/gen_accelerator/i_acc_dispatcher/* + +add wave -noupdate -group CVA6 -group perf_counters /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/gen_perf_counter/perf_counters_i/* From 7f654c9642c9d515f971b883fbf0af38e9483b76 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Mon, 19 Jun 2023 23:11:54 +0200 Subject: [PATCH 22/50] cva6: Bump (merge issue) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index c430de57a..271ede7bb 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit c430de57abc111345b917986eb82e9e996b42eda +Subproject commit 271ede7bbb47f3b798a54284b553fd42cdb27cc5 From bf544ef8ec919249e7e60c6074f897c33b9053c7 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 20 Jun 2023 11:57:38 +0200 Subject: [PATCH 23/50] cva6: Bump (move decoder) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 271ede7bb..76090ae6b 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 271ede7bbb47f3b798a54284b553fd42cdb27cc5 +Subproject commit 76090ae6b5622bdb36c8c0ba32a5b9902f4028b3 From 2addb5fddea0365b08cbd494f4cbbbbb18869f69 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 20 Jun 2023 11:58:41 +0200 Subject: [PATCH 24/50] cva6_accel_first_pass_decoder: Merge other accel decode logic Signed-off-by: Nils Wistoff --- hardware/src/cva6_accel_first_pass_decoder.sv | 118 ++++++++++++------ 1 file changed, 81 insertions(+), 37 deletions(-) diff --git a/hardware/src/cva6_accel_first_pass_decoder.sv b/hardware/src/cva6_accel_first_pass_decoder.sv index 0519d58b7..74c7e14e2 100644 --- a/hardware/src/cva6_accel_first_pass_decoder.sv +++ b/hardware/src/cva6_accel_first_pass_decoder.sv @@ -7,36 +7,49 @@ // instruction, whether it reads scalar registers, and whether // it writes to a destination scalar register -module cva6_accel_first_pass_decoder import rvv_pkg::*; ( - input logic [31:0] instruction_i, // instruction from IF - output logic is_accel_o, // is a vector instruction - output logic is_rs1_o, - output logic is_rs2_o, - output logic is_rd_o, - output logic is_fs1_o, - output logic is_fs2_o, - output logic is_fd_o, - output logic is_vfp_o, // is a vector floating-point instruction - output logic is_load_o, - output logic is_store_o +module cva6_accel_first_pass_decoder import rvv_pkg::*; import ariane_pkg::*; ( + input logic [31:0] instruction_i, // instruction from IF + input riscv::xs_t fs_i, // floating point extension status + input riscv::xs_t vs_i, // vector extension status + output logic is_accel_o, // is a vector instruction + output scoreboard_entry_t instruction_o, // predecoded instruction + output logic illegal_instr_o, // is an illegal instruction + output logic is_control_flow_instr_o ); + logic is_rs1; + logic is_rs2; + logic is_rd; + logic is_fs1; + logic is_fs2; + logic is_fd; + logic is_vfp; // is a vector floating-point instruction + logic is_load; + logic is_store; + // Cast instruction into the `rvv_instruction_t` struct rvv_instruction_t instr; assign instr = rvv_instruction_t'(instruction_i); + // Cast instruction into scalar `instruction_t` struct + riscv::instruction_t instr_scalar; + assign instr_scalar = riscv::instruction_t'(instruction_i); + + // Vector instructions never change control flow + assign is_control_flow_instr_o = 1'b0; + always_comb begin // Default values is_accel_o = 1'b0; - is_rs1_o = 1'b0; - is_rs2_o = 1'b0; - is_rd_o = 1'b0; - is_fs1_o = 1'b0; - is_fs2_o = 1'b0; - is_fd_o = 1'b0; - is_vfp_o = 1'b0; - is_load_o = instr.i_type.opcode == riscv::OpcodeLoadFp; - is_store_o = instr.i_type.opcode == riscv::OpcodeStoreFp; + is_rs1 = 1'b0; + is_rs2 = 1'b0; + is_rd = 1'b0; + is_fs1 = 1'b0; + is_fs2 = 1'b0; + is_fd = 1'b0; + is_vfp = 1'b0; + is_load = instr.i_type.opcode == riscv::OpcodeLoadFp; + is_store = instr.i_type.opcode == riscv::OpcodeStoreFp; // Decode based on the opcode case (instr.i_type.opcode) @@ -46,20 +59,20 @@ module cva6_accel_first_pass_decoder import rvv_pkg::*; ( is_accel_o = 1'b1; case (instr.varith_type.func3) OPFVV: begin - is_fd_o = instr.varith_type.func6 == 6'b010_000; // VFWUNARY0 - is_vfp_o = 1'b1; + is_fd = instr.varith_type.func6 == 6'b010_000; // VFWUNARY0 + is_vfp = 1'b1; end - OPMVV: is_rd_o = instr.varith_type.func6 == 6'b010_000; // VWXUNARY0 - OPIVX: is_rs1_o = 1'b1 ; + OPMVV: is_rd = instr.varith_type.func6 == 6'b010_000; // VWXUNARY0 + OPIVX: is_rs1 = 1'b1 ; OPFVF: begin - is_fs1_o = 1'b1; - is_vfp_o = 1'b1; + is_fs1 = 1'b1; + is_vfp = 1'b1; end - OPMVX: is_rs1_o = 1'b1 ; + OPMVX: is_rs1 = 1'b1 ; OPCFG: begin - is_rs1_o = instr.vsetivli_type.func2 != 2'b11; // not vsetivli - is_rs2_o = instr.vsetvl_type.func7 == 7'b100_0000; // vsetvl - is_rd_o = 1'b1 ; + is_rs1 = instr.vsetivli_type.func2 != 2'b11; // not vsetivli + is_rs2 = instr.vsetvl_type.func7 == 7'b100_0000; // vsetvl + is_rd = 1'b1 ; end endcase end @@ -77,8 +90,8 @@ module cva6_accel_first_pass_decoder import rvv_pkg::*; ( 4'b1110, //VLxE512/VSxE512 4'b1111: begin //VLxE1024/VSxE1024 is_accel_o = 1'b1 ; - is_rs1_o = 1'b1 ; - is_rs2_o = instr.vmem_type.mop == 2'b10; // Strided operation + is_rs1 = 1'b1 ; + is_rs2 = instr.vmem_type.mop == 2'b10; // Strided operation end endcase end @@ -91,7 +104,7 @@ module cva6_accel_first_pass_decoder import rvv_pkg::*; ( 3'b110, //VAMO*EI32.V 3'b111: begin //VAMO*EI64.V is_accel_o = 1'b1; - is_rs1_o = 1'b1; + is_rs1 = 1'b1; end endcase end @@ -106,13 +119,44 @@ module cva6_accel_first_pass_decoder import rvv_pkg::*; ( 3'b110, //CSRRSI 3'b111: begin //CSRRCI is_accel_o = is_vector_csr(riscv::csr_reg_t'(instr.i_type.imm)); - is_rs1_o = is_vector_csr(riscv::csr_reg_t'(instr.i_type.imm)); - is_rs2_o = is_vector_csr(riscv::csr_reg_t'(instr.i_type.imm)); - is_rd_o = is_vector_csr(riscv::csr_reg_t'(instr.i_type.imm)); + is_rs1 = is_vector_csr(riscv::csr_reg_t'(instr.i_type.imm)); + is_rs2 = is_vector_csr(riscv::csr_reg_t'(instr.i_type.imm)); + is_rd = is_vector_csr(riscv::csr_reg_t'(instr.i_type.imm)); end endcase end endcase end + always_comb begin + instruction_o = '0; + illegal_instr_o = 1'b1; + + if (is_accel_o && vs_i != riscv::Off) begin // trigger illegal instruction if the vector extension is turned off + // TODO: Instruction going to other accelerators might need to distinguish whether the value of vs_i is needed or not. + // Send accelerator instructions to the coprocessor + instruction_o.fu = ACCEL; + instruction_o.vfp = is_vfp; + instruction_o.rs1 = (is_rs1 || is_fs1) ? instr_scalar.rtype.rs1 : {REG_ADDR_SIZE{1'b0}}; + instruction_o.rs2 = (is_rs2 || is_fs2) ? instr_scalar.rtype.rs2 : {REG_ADDR_SIZE{1'b0}}; + instruction_o.rd = (is_rd || is_fd) ? instr_scalar.rtype.rd : {REG_ADDR_SIZE{1'b0}}; + + // Decode the vector operation + unique case ({is_store, is_load, is_fs1, is_fs2, is_fd}) + 5'b10000: instruction_o.op = ACCEL_OP_STORE; + 5'b01000: instruction_o.op = ACCEL_OP_LOAD; + 5'b00100: instruction_o.op = ACCEL_OP_FS1; + 5'b00001: instruction_o.op = ACCEL_OP_FD; + 5'b00000: instruction_o.op = ACCEL_OP; + endcase + + // Check that mstatus.FS is not OFF if we have a FP instruction for the accelerator + illegal_instr_o = (is_vfp && (fs_i == riscv::Off)) ? 1'b1 : 1'b0; + + // result holds the undecoded instruction + instruction_o.result = { {riscv::XLEN-32{1'b0}}, instruction_i[31:0] }; + instruction_o.use_imm = 1'b0; + end + end + endmodule : cva6_accel_first_pass_decoder From 36a06ba65e0fbea6236fa918240ba7f05e99ce3e Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 20 Jun 2023 19:11:46 +0200 Subject: [PATCH 25/50] cva6: Bump (unify interfaces) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 76090ae6b..abcaf83ca 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 76090ae6b5622bdb36c8c0ba32a5b9902f4028b3 +Subproject commit abcaf83ca76e1d7a352e2385dfdcc54b293a549d From ad525372ac7052c55a54143a43ac376e62ce7b79 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 20 Jun 2023 19:13:04 +0200 Subject: [PATCH 26/50] cva6: Unify accelerator and CVX interface Signed-off-by: Nils Wistoff --- hardware/include/ara_pkg.sv | 4 +- hardware/scripts/wave_core.tcl | 84 +++++++++--------- hardware/src/accel_dispatcher_ideal.sv | 28 +++--- hardware/src/ara.sv | 8 -- hardware/src/ara_dispatcher.sv | 114 ++++++++++++------------- hardware/src/ara_system.sv | 38 ++++----- hardware/tb/ara_testharness.sv | 6 +- 7 files changed, 131 insertions(+), 151 deletions(-) diff --git a/hardware/include/ara_pkg.sv b/hardware/include/ara_pkg.sv index 014b00473..1f8e50cfa 100644 --- a/hardware/include/ara_pkg.sv +++ b/hardware/include/ara_pkg.sv @@ -239,8 +239,8 @@ package ara_pkg; ///////////////////////////// // Use Ariane's accelerator interface. - typedef ariane_pkg::accelerator_req_t accelerator_req_t; - typedef ariane_pkg::accelerator_resp_t accelerator_resp_t; + typedef acc_pkg::accelerator_req_t accelerator_req_t; + typedef acc_pkg::accelerator_resp_t accelerator_resp_t; ///////////////////////// // Backend interface // diff --git a/hardware/scripts/wave_core.tcl b/hardware/scripts/wave_core.tcl index c22e20281..757f814e7 100644 --- a/hardware/scripts/wave_core.tcl +++ b/hardware/scripts/wave_core.tcl @@ -4,62 +4,62 @@ # # Author: Matheus Cavalcante -add wave -noupdate -group CVA6 -group core /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/* +add wave -noupdate -group CVA6 -group core /ara_tb/dut/i_ara_soc/i_system/i_ariane/* -add wave -noupdate -group CVA6 -group frontend /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/* -add wave -noupdate -group CVA6 -group frontend -group icache /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_cva6_icache/* -# add wave -noupdate -group CVA6 -group frontend -group ras /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_ras/* -# add wave -noupdate -group CVA6 -group frontend -group btb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_btb/* -# add wave -noupdate -group CVA6 -group frontend -group bht /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_bht/* -# add wave -noupdate -group CVA6 -group frontend -group instr_scan /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/*/i_instr_scan/* -# add wave -noupdate -group CVA6 -group frontend -group fetch_fifo /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_fetch_fifo/* +add wave -noupdate -group CVA6 -group frontend /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/* +add wave -noupdate -group CVA6 -group frontend -group icache /ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/* +# add wave -noupdate -group CVA6 -group frontend -group ras /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_ras/* +# add wave -noupdate -group CVA6 -group frontend -group btb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_btb/* +# add wave -noupdate -group CVA6 -group frontend -group bht /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_bht/* +# add wave -noupdate -group CVA6 -group frontend -group instr_scan /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/*/i_instr_scan/* +# add wave -noupdate -group CVA6 -group frontend -group fetch_fifo /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_fetch_fifo/* -add wave -noupdate -group CVA6 -group id_stage -group decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/id_stage_i/decoder_i/* -add wave -noupdate -group CVA6 -group id_stage -group compressed_decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/id_stage_i/genblk1/compressed_decoder_i/* -add wave -noupdate -group CVA6 -group id_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/id_stage_i/* +add wave -noupdate -group CVA6 -group id_stage -group decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/id_stage_i/decoder_i/* +add wave -noupdate -group CVA6 -group id_stage -group compressed_decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/id_stage_i/genblk1/compressed_decoder_i/* +add wave -noupdate -group CVA6 -group id_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/id_stage_i/* -add wave -noupdate -group CVA6 -group issue_stage -group scoreboard /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/i_scoreboard/* -add wave -noupdate -group CVA6 -group issue_stage -group issue_read_operands /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/* -add wave -noupdate -group CVA6 -group issue_stage -group rename /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/i_re_name/* -add wave -noupdate -group CVA6 -group issue_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/* +add wave -noupdate -group CVA6 -group issue_stage -group scoreboard /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/i_scoreboard/* +add wave -noupdate -group CVA6 -group issue_stage -group issue_read_operands /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/i_issue_read_operands/* +add wave -noupdate -group CVA6 -group issue_stage -group rename /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/i_re_name/* +add wave -noupdate -group CVA6 -group issue_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/* -add wave -noupdate -group CVA6 -group ex_stage -group alu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/alu_i/* -add wave -noupdate -group CVA6 -group ex_stage -group mult /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/i_mult/* -add wave -noupdate -group CVA6 -group ex_stage -group mult -group mul /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/* -add wave -noupdate -group CVA6 -group ex_stage -group mult -group div /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/i_mult/i_div/* -add wave -noupdate -group CVA6 -group ex_stage -group fpu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/fpu_gen/fpu_i/* -add wave -noupdate -group CVA6 -group ex_stage -group fpu -group fpnew /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/fpu_gen/fpu_i/fpu_gen/i_fpnew_bulk/* +add wave -noupdate -group CVA6 -group ex_stage -group alu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/alu_i/* +add wave -noupdate -group CVA6 -group ex_stage -group mult /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/i_mult/* +add wave -noupdate -group CVA6 -group ex_stage -group mult -group mul /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/i_mult/i_multiplier/* +add wave -noupdate -group CVA6 -group ex_stage -group mult -group div /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/i_mult/i_div/* +add wave -noupdate -group CVA6 -group ex_stage -group fpu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/fpu_gen/fpu_i/* +add wave -noupdate -group CVA6 -group ex_stage -group fpu -group fpnew /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_gen/i_fpnew_bulk/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group lsu_bypass /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/lsu_bypass_i/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group itlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_itlb/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group dtlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_dtlb/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group ptw /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_ptw/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group lsu_bypass /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/lsu_bypass_i/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group itlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_itlb/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group dtlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_dtlb/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group ptw /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_ptw/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/i_store_unit/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit -group store_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/i_store_unit/store_buffer_i/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_store_unit/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit -group store_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_store_unit/store_buffer_i/* -add wave -noupdate -group CVA6 -group ex_stage -group lsu -group load_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/* +add wave -noupdate -group CVA6 -group ex_stage -group lsu -group load_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_load_unit/* -add wave -noupdate -group CVA6 -group ex_stage -group branch_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/branch_unit_i/* +add wave -noupdate -group CVA6 -group ex_stage -group branch_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/branch_unit_i/* -add wave -noupdate -group CVA6 -group ex_stage -group csr_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/csr_buffer_i/* +add wave -noupdate -group CVA6 -group ex_stage -group csr_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/csr_buffer_i/* -add wave -noupdate -group CVA6 -group ex_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/* +add wave -noupdate -group CVA6 -group ex_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/* -add wave -noupdate -group CVA6 -group commit_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/commit_stage_i/* +add wave -noupdate -group CVA6 -group commit_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/commit_stage_i/* -add wave -noupdate -group CVA6 -group csr_file /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/csr_regfile_i/* +add wave -noupdate -group CVA6 -group csr_file /ara_tb/dut/i_ara_soc/i_system/i_ariane/csr_regfile_i/* -add wave -noupdate -group CVA6 -group controller /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/controller_i/* +add wave -noupdate -group CVA6 -group controller /ara_tb/dut/i_ara_soc/i_system/i_ariane/controller_i/* -add wave -noupdate -group CVA6 -group wt_dcache /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/* -add wave -noupdate -group CVA6 -group wt_dcache -group miss_handler /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/i_wt_dcache_missunit/* +add wave -noupdate -group CVA6 -group wt_dcache /ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/i_wt_dcache/* +add wave -noupdate -group CVA6 -group wt_dcache -group miss_handler /ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/i_wt_dcache/i_wt_dcache_missunit/* -add wave -noupdate -group CVA6 -group wt_dcache -group load {/ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[0]/i_wt_dcache_ctrl/*} -add wave -noupdate -group CVA6 -group wt_dcache -group ptw {/ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[1]/i_wt_dcache_ctrl/*} +add wave -noupdate -group CVA6 -group wt_dcache -group load {/ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[0]/i_wt_dcache_ctrl/*} +add wave -noupdate -group CVA6 -group wt_dcache -group ptw {/ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[1]/i_wt_dcache_ctrl/*} -add wave -noupdate -group CVA6 -group dispatcher /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/gen_accelerator/i_acc_dispatcher/* +add wave -noupdate -group CVA6 -group dispatcher /ara_tb/dut/i_ara_soc/i_system/i_ariane/gen_accelerator/i_acc_dispatcher/* -add wave -noupdate -group CVA6 -group perf_counters /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/gen_perf_counter/perf_counters_i/* +add wave -noupdate -group CVA6 -group perf_counters /ara_tb/dut/i_ara_soc/i_system/i_ariane/gen_perf_counter/perf_counters_i/* diff --git a/hardware/src/accel_dispatcher_ideal.sv b/hardware/src/accel_dispatcher_ideal.sv index 8c564b34c..b89d93474 100644 --- a/hardware/src/accel_dispatcher_ideal.sv +++ b/hardware/src/accel_dispatcher_ideal.sv @@ -25,11 +25,7 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; ( input logic rst_ni, // Accelerator interaface output accelerator_req_t acc_req_o, - output logic acc_req_valid_o, - input logic acc_req_ready_i, - input accelerator_resp_t acc_resp_i, - input logic acc_resp_valid_i, - output logic acc_resp_ready_o + input accelerator_resp_t acc_resp_i ); localparam string vtrace = `STRINGIFY(`VTRACE); @@ -69,7 +65,7 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; ( status_cnt_n = status_cnt_q; fifo_data_raw = fifo_q[read_pointer_q]; - if (acc_req_ready_i && ~fifo_empty) begin + if (acc_resp_i.req_ready && ~fifo_empty) begin // read from the queue is a default assignment // but increment the read pointer... if (read_pointer_n == N_VINSN - 1) @@ -94,16 +90,16 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; ( assign fifo_empty = (status_cnt_q == 0); - // Always valid until empty - assign acc_req_valid_o = ~fifo_empty; - // Flush the answer - assign acc_resp_ready_o = 1'b1; // Output assignment assign fifo_data = fifo_payload_t'(fifo_data_raw); assign acc_req_o = '{ insn : fifo_data.insn, rs1 : fifo_data.rs1, rs2 : fifo_data.rs2, + // Always valid until empty + req_valid : ~fifo_empty, + // Flush the answer + resp_ready : 1'b1, default : '0 }; @@ -133,7 +129,7 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; ( // Stop the computation when the instructions are over and ara has returned idle // Just check that we are after reset always_ff @(posedge clk_i) begin - if (rst_ni && was_reset && !acc_req_valid_o && i_system.i_ara.ara_idle) begin + if (rst_ni && was_reset && !acc_req_o.req_valid && i_system.i_ara.ara_idle) begin $display("[hw-cycles]: %d", int'(perf_cnt_q)); $info("Core Test ", $sformatf("*** SUCCESS *** (tohost = %0d)", 0)); $finish(0); @@ -160,10 +156,10 @@ endmodule fifo_payload_t payload; acc_req_o = '0; - acc_req_valid_o = 1'b0; + acc_req_o.req_valid = 1'b0; // Flush the answer - acc_resp_ready_o = 1'b1; + acc_req_o.resp_ready = 1'b1; acc_req_o = '0; acc_req_o.frm = fpnew_pkg::RNE; @@ -176,17 +172,17 @@ endmodule while ($fscanf(fd, "%h", payload) == 1) begin // Always valid - acc_req_valid_o = 1'b1; + acc_req_o.req_valid = 1'b1; acc_req_o.insn = payload.insn; acc_req_o.rs1 = payload.rs1; // Wait for the handshake - wait(acc_req_ready_i); + wait(acc_resp_i.req_ready); @(posedge clk_i); @(negedge clk_i); end // Stop dispatching - acc_req_valid_o = 1'b0; + acc_req_o.req_valid = 1'b0; $fclose(fd); end diff --git a/hardware/src/ara.sv b/hardware/src/ara.sv index c6976be6f..0583d1eea 100644 --- a/hardware/src/ara.sv +++ b/hardware/src/ara.sv @@ -39,11 +39,7 @@ module ara import ara_pkg::*; #( output logic scan_data_o, // Interface with Ariane input accelerator_req_t acc_req_i, - input logic acc_req_valid_i, - output logic acc_req_ready_o, output accelerator_resp_t acc_resp_o, - output logic acc_resp_valid_o, - input logic acc_resp_ready_i, // AXI interface output axi_req_t axi_req_o, input axi_resp_t axi_resp_i @@ -95,11 +91,7 @@ module ara import ara_pkg::*; #( .rst_ni (rst_ni ), // Interface with Ariane .acc_req_i (acc_req_i ), - .acc_req_valid_i (acc_req_valid_i ), - .acc_req_ready_o (acc_req_ready_o ), .acc_resp_o (acc_resp_o ), - .acc_resp_valid_o (acc_resp_valid_o), - .acc_resp_ready_i (acc_resp_ready_i), // Interface with the sequencer .ara_req_o (ara_req ), .ara_req_valid_o (ara_req_valid ), diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv index 2eb6e2ce3..998e84230 100644 --- a/hardware/src/ara_dispatcher.sv +++ b/hardware/src/ara_dispatcher.sv @@ -22,11 +22,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( input logic rst_ni, // Interfaces with Ariane input accelerator_req_t acc_req_i, - input logic acc_req_valid_i, - output logic acc_req_ready_o, output accelerator_resp_t acc_resp_o, - output logic acc_resp_valid_o, - input logic acc_resp_ready_i, // Interface with Ara's backend output ara_req_t ara_req_o, output logic ara_req_valid_o, @@ -276,8 +272,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( is_decoding = 1'b0; in_lane_op = 1'b0; - acc_req_ready_o = 1'b0; - acc_resp_valid_o = 1'b0; + acc_resp_o.req_ready = 1'b0; + acc_resp_o.resp_valid = 1'b0; acc_resp_o = '{ trans_id : acc_req_i.trans_id, load_complete : load_zero_vl | load_complete_q, @@ -326,8 +322,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( automatic rvv_instruction_t insn = rvv_instruction_t'(acc_req_i.insn.instr); // Stall the interface, wait for the backend to accept the injected uop - acc_req_ready_o = 1'b0; - acc_resp_valid_o = 1'b0; + acc_resp_o.req_ready = 1'b0; + acc_resp_o.resp_valid = 1'b0; // Handle LMUL > 1 rs_lmul_cnt_d = rs_lmul_cnt_q; @@ -428,11 +424,11 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( endcase if (state_d == NORMAL_OPERATION && state_q != RESHUFFLE) begin - if (acc_req_valid_i && ara_req_ready_i && acc_resp_ready_i) begin + if (acc_req_i.req_valid && ara_req_ready_i && acc_req_i.resp_ready) begin // Decoding is_decoding = 1'b1; // Acknowledge the request - acc_req_ready_o = ara_req_ready_i; + acc_resp_o.req_ready = ara_req_ready_i; // Decode the instructions based on their opcode unique case (acc_req_i.insn.itype.opcode) @@ -445,14 +441,14 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( automatic rvv_instruction_t insn = rvv_instruction_t'(acc_req_i.insn.instr); // These always respond at the same cycle - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; // Decode based on their func3 field unique case (insn.varith_type.func3) // Configuration instructions OPCFG: begin: opcfg // These can be acknowledged regardless of the state of Ara - acc_req_ready_o = 1'b1; + acc_resp_o.req_ready = 1'b1; is_config = 1'b1; // Update vtype @@ -1216,8 +1212,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( 6'b010000: begin // VWXUNARY0 // vmv.x.s // Stall the interface until we get the result - acc_req_ready_o = 1'b0; - acc_resp_valid_o = 1'b0; + acc_resp_o.req_ready = 1'b0; + acc_resp_o.resp_valid = 1'b0; case (insn.varith_type.rs1) 5'b00000: begin @@ -1256,10 +1252,10 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // Wait until the back-end answers to acknowledge those instructions if (ara_resp_valid_i) begin - acc_req_ready_o = 1'b1; + acc_resp_o.req_ready = 1'b1; acc_resp_o.result = ara_resp_i.resp; acc_resp_o.error = ara_resp_i.error; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; ara_req_valid_d = 1'b0; end end @@ -1894,8 +1890,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( 6'b010000: begin // VWFUNARY0 // vmv.f.s // Stall the interface until we get the result - acc_req_ready_o = 1'b0; - acc_resp_valid_o = 1'b0; + acc_resp_o.req_ready = 1'b0; + acc_resp_o.resp_valid = 1'b0; ara_req_d.op = ara_pkg::VFMVFS; ara_req_d.use_vd = 1'b0; @@ -1930,10 +1926,10 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // Wait until the back-end answers to acknowledge those instructions if (ara_resp_valid_i) begin - acc_req_ready_o = 1'b1; + acc_resp_o.req_ready = 1'b1; acc_resp_o.result = vfmvfs_result; acc_resp_o.error = ara_resp_i.error; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; ara_req_valid_d = 1'b0; end end @@ -2513,7 +2509,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( is_vload = 1'b1; // Wait before acknowledging this instruction - acc_req_ready_o = 1'b0; + acc_resp_o.req_ready = 1'b0; // These generate a request to Ara's backend ara_req_d.vd = insn.vmem_type.rd; @@ -2558,9 +2554,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( end end default: begin // Invalid. Element is too wide, or encoding is non-existant. - acc_req_ready_o = 1'b1; + acc_resp_o.req_ready = 1'b1; acc_resp_o.error = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; ara_req_valid_d = 1'b0; end endcase @@ -2582,13 +2578,13 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( 5'b10000: begin // Unit-strided, fault-only first // TODO: Not implemented illegal_insn = 1'b1; - acc_req_ready_o = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.req_ready = 1'b1; + acc_resp_o.resp_valid = 1'b1; end default: begin // Reserved illegal_insn = 1'b1; - acc_req_ready_o = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.req_ready = 1'b1; + acc_resp_o.resp_valid = 1'b1; end endcase end @@ -2617,7 +2613,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // But the new eew is greater than vsew if (signed'(ara_req_d.vtype.vsew - vtype_q.vsew) > 0) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end end // The new emul is greater than the previous lmul @@ -2625,7 +2621,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // But the new eew is lower than vsew if (signed'(ara_req_d.vtype.vsew - vtype_q.vsew) < 0) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end end default:; @@ -2636,19 +2632,19 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( unique case (ara_req_d.emul) LMUL_2: if ((insn.varith_type.rd & 5'b00001) != 5'b00000) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end LMUL_4: if ((insn.varith_type.rd & 5'b00011) != 5'b00000) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end LMUL_8: if ((insn.varith_type.rd & 5'b00111) != 5'b00000) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end LMUL_RSVD: begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end default:; endcase @@ -2659,8 +2655,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( ignore_zero_vl_check = 1'b1; // The LMUL value is kept in the instruction itself illegal_insn = 1'b0; - acc_req_ready_o = 1'b0; - acc_resp_valid_o = 1'b0; + acc_resp_o.req_ready = 1'b0; + acc_resp_o.resp_valid = 1'b0; ara_req_valid_d = 1'b1; // Maximum vector length. VLMAX = nf * VLEN / EW8. @@ -2691,9 +2687,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // Wait until the back-end answers to acknowledge those instructions if (ara_resp_valid_i) begin - acc_req_ready_o = 1'b1; + acc_resp_o.req_ready = 1'b1; acc_resp_o.error = ara_resp_i.error; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; ara_req_valid_d = 1'b0; // In case of error, modify vstart if (ara_resp_i.error) @@ -2719,7 +2715,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( is_vstore = 1'b1; // Wait before acknowledging this instruction - acc_req_ready_o = 1'b0; + acc_resp_o.req_ready = 1'b0; // vl depends on the EEW encoded in the instruction. // Ara does not reshuffle source vregs upon vector stores, @@ -2771,9 +2767,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( end end default: begin // Invalid. Element is too wide, or encoding is non-existant. - acc_req_ready_o = 1'b1; + acc_resp_o.req_ready = 1'b1; acc_resp_o.error = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; ara_req_valid_d = 1'b0; end endcase @@ -2794,8 +2790,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( end default: begin // Reserved illegal_insn = 1'b1; - acc_req_ready_o = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.req_ready = 1'b1; + acc_resp_o.resp_valid = 1'b1; end endcase end @@ -2824,7 +2820,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // But the new eew is greater than vsew if (signed'(ara_req_d.vtype.vsew - vtype_q.vsew) > 0) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end end // The new emul is greater than the previous lmul @@ -2832,7 +2828,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // But the new eew is lower than vsew if (signed'(ara_req_d.vtype.vsew - vtype_q.vsew) < 0) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end end default:; @@ -2843,19 +2839,19 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( unique case (ara_req_d.emul) LMUL_2: if ((insn.varith_type.rd & 5'b00001) != 5'b00000) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end LMUL_4: if ((insn.varith_type.rd & 5'b00011) != 5'b00000) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end LMUL_8: if ((insn.varith_type.rd & 5'b00111) != 5'b00000) begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end LMUL_RSVD: begin illegal_insn = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end default:; endcase @@ -2892,16 +2888,16 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( endcase illegal_insn = 1'b0; - acc_req_ready_o = 1'b0; - acc_resp_valid_o = 1'b0; + acc_resp_o.req_ready = 1'b0; + acc_resp_o.resp_valid = 1'b0; ara_req_valid_d = 1'b1; end // Wait until the back-end answers to acknowledge those instructions if (ara_resp_valid_i) begin - acc_req_ready_o = 1'b1; + acc_resp_o.req_ready = 1'b1; acc_resp_o.error = ara_resp_i.error; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; ara_req_valid_d = 1'b0; // If there is an error, change vstart if (ara_resp_i.error) @@ -2915,7 +2911,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( riscv::OpcodeSystem: begin // These always respond at the same cycle - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; is_config = 1'b1; unique case (acc_req_i.insn.itype.funct3) @@ -3083,7 +3079,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( default: begin // Trigger an illegal instruction acc_resp_o.error = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end endcase end @@ -3091,7 +3087,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( default: begin // Trigger an illegal instruction acc_resp_o.error = 1'b1; - acc_resp_valid_o = 1'b1; + acc_resp_o.resp_valid = 1'b1; end endcase end @@ -3148,8 +3144,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( automatic rvv_instruction_t insn = rvv_instruction_t'(acc_req_i.insn.instr); // Stall the interface, and inject a reshuffling instruction - acc_req_ready_o = 1'b0; - acc_resp_valid_o = 1'b0; + acc_resp_o.req_ready = 1'b0; + acc_resp_o.resp_valid = 1'b0; ara_req_valid_d = 1'b0; // Initialize the reshuffle counter limit to handle LMUL > 1 @@ -3215,8 +3211,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // operation was resolved (to decrement its pending load/store counter) // This can collide with the same signal from the vector load/store unit, so we must // delay the zero_vl acknowledge by 1 cycle - acc_req_ready_o = ~((is_vload & load_complete_q) | (is_vstore & store_complete_q)); - acc_resp_valid_o = ~((is_vload & load_complete_q) | (is_vstore & store_complete_q)); + acc_resp_o.req_ready = ~((is_vload & load_complete_q) | (is_vstore & store_complete_q)); + acc_resp_o.resp_valid = ~((is_vload & load_complete_q) | (is_vstore & store_complete_q)); ara_req_valid_d = 1'b0; load_zero_vl = is_vload; store_zero_vl = is_vstore; diff --git a/hardware/src/ara_system.sv b/hardware/src/ara_system.sv index 16d480def..c2e7a7c5b 100644 --- a/hardware/src/ara_system.sv +++ b/hardware/src/ara_system.sv @@ -73,13 +73,11 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( // Ara and Ariane // ////////////////////// - import ariane_pkg::accelerator_req_t; - import ariane_pkg::accelerator_resp_t; + import acc_pkg::accelerator_req_t; + import acc_pkg::accelerator_resp_t; // Accelerator ports accelerator_req_t acc_req; - logic acc_req_valid; - logic acc_req_ready; accelerator_resp_t acc_resp; logic acc_resp_valid; logic acc_resp_ready; @@ -98,20 +96,21 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( .clk_i (clk_i ), .rst_ni (rst_ni ), .acc_req_o (acc_req ), - .acc_req_valid_o (acc_req_valid ), - .acc_req_ready_i (acc_req_ready ), .acc_resp_i (acc_resp ), .acc_resp_valid_i (acc_resp_valid ), .acc_resp_ready_o (acc_resp_ready ) ); `else - ariane #( + cva6 #( .ArianeCfg(ArianeCfg), + .cvxif_req_t (acc_pkg::accelerator_req_t), + .cvxif_resp_t (acc_pkg::accelerator_resp_t), .AxiAddrWidth ( AxiAddrWidth ), .AxiDataWidth ( AxiNarrowDataWidth ), .AxiIdWidth ( AxiIdWidth ), .axi_ar_chan_t (ariane_axi_ar_t), .axi_aw_chan_t (ariane_axi_aw_t), + .axi_w_chan_t (ariane_axi_w_t), .axi_req_t (ariane_axi_req_t), .axi_rsp_t (ariane_axi_resp_t) ) i_ariane ( @@ -123,19 +122,20 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( .ipi_i ('0 ), .time_irq_i ('0 ), .debug_req_i ('0 ), - .axi_req_o (ariane_narrow_axi_req ), - .axi_resp_i (ariane_narrow_axi_resp), - // Accelerator ports - .acc_req_o (acc_req ), - .acc_req_valid_o (acc_req_valid ), - .acc_req_ready_i (acc_req_ready ), - .acc_resp_i (acc_resp ), - .acc_resp_valid_i (acc_resp_valid ), - .acc_resp_ready_o (acc_resp_ready ), + // Invalidation requests .acc_cons_en_o (acc_cons_en ), .inval_addr_i (inval_addr ), .inval_valid_i (inval_valid ), - .inval_ready_o (inval_ready ) + .inval_ready_o (inval_ready ), + .rvfi_o ( ), + // Accelerator ports + .cvxif_req_o (acc_req ), + .cvxif_resp_i (acc_resp ), + .l15_req_o ( ), + .l15_rtrn_i ( '0 ), + // Memory interface + .axi_req_o (ariane_narrow_axi_req ), + .axi_resp_i (ariane_narrow_axi_resp) ); `endif @@ -218,11 +218,7 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( .scan_data_i (1'b0 ), .scan_data_o (/* Unused */ ), .acc_req_i (acc_req ), - .acc_req_valid_i (acc_req_valid ), - .acc_req_ready_o (acc_req_ready ), .acc_resp_o (acc_resp ), - .acc_resp_valid_o(acc_resp_valid), - .acc_resp_ready_i(acc_resp_ready), .axi_req_o (ara_axi_req ), .axi_resp_i (ara_axi_resp ) ); diff --git a/hardware/tb/ara_testharness.sv b/hardware/tb/ara_testharness.sv index 09901b262..84edf4c8e 100644 --- a/hardware/tb/ara_testharness.sv +++ b/hardware/tb/ara_testharness.sv @@ -153,7 +153,7 @@ module ara_testharness #( // If disabled if (!runtime_cnt_en_q) // Start only if the software allowed the enable and we detect the first V instruction - runtime_cnt_en_d = i_ara_soc.i_system.i_ara.acc_req_valid_i & cnt_en_mask; + runtime_cnt_en_d = i_ara_soc.i_system.i_ara.acc_req_i.req_valid & cnt_en_mask; // If enabled if (runtime_cnt_en_q) // Stop counting only if the software disabled the counter and Ara returned idle @@ -177,14 +177,14 @@ module ara_testharness #( runtime_to_be_updated_d = runtime_to_be_updated_q; // Assert the update flag upon a new valid vector instruction - if (!runtime_to_be_updated_q && i_ara_soc.i_system.i_ara.acc_req_valid_i) begin + if (!runtime_to_be_updated_q && i_ara_soc.i_system.i_ara.acc_req_i.req_valid) begin runtime_to_be_updated_d = 1'b1; end // Update the internal runtime and reset the update flag if (runtime_to_be_updated_q && i_ara_soc.i_system.i_ara.ara_idle && - !i_ara_soc.i_system.i_ara.acc_req_valid_i) begin + !i_ara_soc.i_system.i_ara.acc_req_i.req_valid) begin runtime_buf_d = runtime_cnt_q; runtime_to_be_updated_d = 1'b0; end From 5f17f44af50f10446cb098cf351f7366b2bbc3df Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 20 Jun 2023 20:09:22 +0200 Subject: [PATCH 27/50] cva6: Bump (move issue logic) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index abcaf83ca..646f33cae 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit abcaf83ca76e1d7a352e2385dfdcc54b293a549d +Subproject commit 646f33caee03a4e5a5f781b935a42fe9e7d959b2 From d07b1ec6de409679b7e39b0481f1aa747a15e3e2 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 21 Jun 2023 22:27:16 +0200 Subject: [PATCH 28/50] cva6: Bump (remove acc intf) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 646f33cae..d6da78237 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 646f33caee03a4e5a5f781b935a42fe9e7d959b2 +Subproject commit d6da782372359e6abefa6a4b8905fe9e4ecb5686 From 03b76049dda029796bfa753073e14cf16a240954 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Fri, 23 Jun 2023 16:10:25 +0200 Subject: [PATCH 29/50] cva6: Bump (acc_port invalidation) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index d6da78237..5a5778309 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit d6da782372359e6abefa6a4b8905fe9e4ecb5686 +Subproject commit 5a5778309fd98dfc496ab582412db3865501c45e From 745cef4b29f60e532b0e85fb85fe6099800b04ae Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Fri, 23 Jun 2023 16:11:03 +0200 Subject: [PATCH 30/50] ara_system: Pack inval interface into acc interface Signed-off-by: Nils Wistoff --- hardware/src/ara_system.sv | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hardware/src/ara_system.sv b/hardware/src/ara_system.sv index c2e7a7c5b..1e8d639b4 100644 --- a/hardware/src/ara_system.sv +++ b/hardware/src/ara_system.sv @@ -90,6 +90,16 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( logic [63:0] hart_id; assign hart_id = {'0, hart_id_i}; + // Pack invalidation interface into acc interface + accelerator_resp_t acc_resp_pack; + always_comb begin : pack_inval + acc_resp_pack = acc_resp; + acc_resp_pack.inval_valid = inval_valid; + acc_resp_pack.inval_addr = inval_addr; + inval_ready = acc_req.inval_ready; + acc_cons_en = acc_req.acc_cons_en; + end + `ifdef IDEAL_DISPATCHER // Perfect dispatcher to Ara accel_dispatcher_ideal i_accel_dispatcher_ideal ( @@ -122,15 +132,10 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( .ipi_i ('0 ), .time_irq_i ('0 ), .debug_req_i ('0 ), - // Invalidation requests - .acc_cons_en_o (acc_cons_en ), - .inval_addr_i (inval_addr ), - .inval_valid_i (inval_valid ), - .inval_ready_o (inval_ready ), .rvfi_o ( ), // Accelerator ports .cvxif_req_o (acc_req ), - .cvxif_resp_i (acc_resp ), + .cvxif_resp_i (acc_resp_pack ), .l15_req_o ( ), .l15_rtrn_i ( '0 ), // Memory interface From 3fc5e4f665bf57bd1028a3bcbdb24117820cc49d Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Fri, 23 Jun 2023 16:19:43 +0200 Subject: [PATCH 31/50] cva6: Bump (merge fu_data mux) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 5a5778309..a753c21c9 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 5a5778309fd98dfc496ab582412db3865501c45e +Subproject commit a753c21c97deb48a9c94b42a0cb93b58acf5a4cb From b82509142ac846f782a997321dcf5264890bc2a3 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 27 Jun 2023 11:02:09 +0200 Subject: [PATCH 32/50] cva6: Bump (cva6_accel_first_pass_decoder_stub) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index a753c21c9..82e928952 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit a753c21c97deb48a9c94b42a0cb93b58acf5a4cb +Subproject commit 82e928952f2e416a7d9722a005ccad2311e01635 From 89aa0fdceb25681c0eabab4e0583fb23f58ecde6 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Thu, 29 Jun 2023 10:06:40 +0200 Subject: [PATCH 33/50] cva6: Bump (rebase) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 82e928952..702f205f3 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 82e928952f2e416a7d9722a005ccad2311e01635 +Subproject commit 702f205f3e5fc71ee23a36f3e35bb1564b4ed5d7 From fd49d4264c56117e2b5c8d64dbeb8dce8094c6b2 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Fri, 30 Jun 2023 09:54:32 +0200 Subject: [PATCH 34/50] cva6: Bump (acc_req in acc_pkg) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 702f205f3..7f2b9cd22 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 702f205f3e5fc71ee23a36f3e35bb1564b4ed5d7 +Subproject commit 7f2b9cd22690be534f3e35ce2a28de9114b4e18d From c1de65684af7c7fa280ba97b0beba62b8f19c6a9 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Fri, 30 Jun 2023 13:42:47 +0200 Subject: [PATCH 35/50] cva6: Bump (rem unused signals) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 7f2b9cd22..4af846329 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 7f2b9cd22690be534f3e35ce2a28de9114b4e18d +Subproject commit 4af846329268790540200bf063afa64d7109e623 From bac0e0a6036074da70096819ef61625787ee146c Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Tue, 4 Jul 2023 12:34:55 +0200 Subject: [PATCH 36/50] cva6: Bump (cv32a6_embedded_config_pkg) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 4af846329..34d4d6f13 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 4af846329268790540200bf063afa64d7109e623 +Subproject commit 34d4d6f130837333b838bed7d5a9a55d4d2e713a From 0fe7cdbd84299f115af6c7859b52630e48115818 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Fri, 7 Jul 2023 10:49:57 +0200 Subject: [PATCH 37/50] cva6: Bump (rebase) Signed-off-by: Nils Wistoff --- hardware/deps/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 34d4d6f13..b0d6f4969 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 34d4d6f130837333b838bed7d5a9a55d4d2e713a +Subproject commit b0d6f496910b3b8a0387134d5b91f7c8194bdf37 From 08cc2810b187d16592f3be9ed93520faeaa7d703 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 3 Nov 2023 16:50:50 +0100 Subject: [PATCH 38/50] [hardware, .gitmodules] Switch from submodules to bender --- .github/workflows/ci.yml | 2 +- .gitmodules | 18 ------------------ hardware/Makefile | 22 +++++++++++++++++----- hardware/deps/apb | 1 - hardware/deps/axi | 1 - hardware/deps/common_cells | 1 - hardware/deps/common_verification | 1 - hardware/deps/cva6 | 1 - hardware/deps/tech_cells_generic | 1 - 9 files changed, 18 insertions(+), 30 deletions(-) delete mode 160000 hardware/deps/apb delete mode 160000 hardware/deps/axi delete mode 160000 hardware/deps/common_cells delete mode 160000 hardware/deps/common_verification delete mode 160000 hardware/deps/cva6 delete mode 160000 hardware/deps/tech_cells_generic diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index c0538262c..c9fda5ee0 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -277,7 +277,7 @@ jobs: ln -s $VERILATOR_ROOT/share/verilator/include $VERILATOR_ROOT/include ln -s $VERILATOR_ROOT/share/verilator/bin/verilator_includer $VERILATOR_ROOT/bin/verilator_includer - name: Download RTL submodules - run: git submodule update --init --recursive hardware + run: make -C hardware update - name: Compile Verilated model of Ara run: | sudo apt-get install libelf-dev diff --git a/.gitmodules b/.gitmodules index 824e85ae0..4221e4dff 100644 --- a/.gitmodules +++ b/.gitmodules @@ -9,21 +9,6 @@ [submodule "toolchain/verilator"] path = toolchain/verilator url = https://github.com/verilator/verilator -[submodule "hardware/deps/axi"] - path = hardware/deps/axi - url = https://github.com/pulp-platform/axi.git -[submodule "hardware/deps/common_cells"] - path = hardware/deps/common_cells - url = https://github.com/pulp-platform/common_cells.git -[submodule "hardware/deps/tech_cells_generic"] - path = hardware/deps/tech_cells_generic - url = https://github.com/pulp-platform/tech_cells_generic.git -[submodule "hardware/deps/common_verification"] - path = hardware/deps/common_verification - url = https://github.com/pulp-platform/common_verification.git -[submodule "hardware/deps/cva6"] - path = hardware/deps/cva6 - url = https://github.com/pulp-platform/cva6.git [submodule "toolchain/newlib"] path = toolchain/newlib url = https://sourceware.org/git/newlib-cygwin.git @@ -32,6 +17,3 @@ path = toolchain/riscv-llvm url = https://github.com/llvm/llvm-project.git ignore = dirty -[submodule "hardware/deps/apb"] - path = hardware/deps/apb - url = https://github.com/pulp-platform/apb.git diff --git a/hardware/Makefile b/hardware/Makefile index 674919386..627a920ef 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -10,6 +10,9 @@ ARA_DIR := $(shell git rev-parse --show-toplevel 2>/dev/null || echo $$ARA_DIR) INSTALL_DIR := $(abspath $(ROOT_DIR)/../install) VERILATOR_INCLUDE := $(INSTALL_DIR)/verilator/share/verilator/include/vltstd +BENDER := $(ROOT_DIR)/../hardware/bender +BENDER_VERSION := 0.27.3 + # Choose Ara's configuration ifndef config ifdef ARA_CONFIGURATION @@ -111,12 +114,21 @@ all: compile $(buildpath): mkdir -p $(buildpath) +.PHONY: $(BENDER) update # Bender -bender: - @[ -x ./bender ] && echo "Bender already exists." || \ - curl --proto '=https' --tlsv1.2 https://fabianschuiki.github.io/bender/init -sSf | sh -s -- 0.23.1 +$(BENDER): + @[ -x $(BENDER) ] && echo "Bender already exists." || \ + curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- $(BENDER_VERSION) @echo "$$(./bender --version) available." +update: $(BENDER) $(ROOT_DIR)/../Bender.yml + rm -rf $(ROOT_DIR)/../hardware/deps/* + $(BENDER) update -f + $(BENDER) checkout + +checkout: $(BENDER) + $(BENDER) checkout + # Patches .PHONY: apply-patches apply-patches: patches @@ -228,7 +240,7 @@ lint: spyglass/tmp/files spyglass/sdc/func.sdc spyglass/scripts/run_lint.tcl spyglass/tmp/files: $(bender) mkdir -p spyglass/tmp - ./bender script verilator -t rtl -t spyglass -t cva6_test -t cv64a6_imafdcv_sv39 $(bender_defs) --define SPYGLASS > spyglass/tmp/files + $(BENDER) script verilator -t rtl -t spyglass -t cva6_test -t cv64a6_imafdcv_sv39 $(bender_defs) --define SPYGLASS > spyglass/tmp/files # DPIs .PHONY: dpi @@ -246,4 +258,4 @@ $(buildpath)/$(dpi_library)/ara_dpi.so: $(dpi) .PHONY: clean clean: rm -rf $(buildpath) - rm -f bender + rm -f $(BENDER) diff --git a/hardware/deps/apb b/hardware/deps/apb deleted file mode 160000 index 77ddf073f..000000000 --- a/hardware/deps/apb +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 77ddf073f194d44b9119949d2421be59789e69ae diff --git a/hardware/deps/axi b/hardware/deps/axi deleted file mode 160000 index 442ff3375..000000000 --- a/hardware/deps/axi +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 442ff3375710513623f95944d66cc2bd09b2f155 diff --git a/hardware/deps/common_cells b/hardware/deps/common_cells deleted file mode 160000 index 015917ff3..000000000 --- a/hardware/deps/common_cells +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 015917ff33e5f944e866814f72f2074fb0f4220f diff --git a/hardware/deps/common_verification b/hardware/deps/common_verification deleted file mode 160000 index 6fc76fb01..000000000 --- a/hardware/deps/common_verification +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 6fc76fb013315af9fabbb90b431863d498df2d6d diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 deleted file mode 160000 index b0d6f4969..000000000 --- a/hardware/deps/cva6 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit b0d6f496910b3b8a0387134d5b91f7c8194bdf37 diff --git a/hardware/deps/tech_cells_generic b/hardware/deps/tech_cells_generic deleted file mode 160000 index 203038f85..000000000 --- a/hardware/deps/tech_cells_generic +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 203038f857158ae4634c47ce0281f402cc2a1344 From 555f196271d16127e194e140de63cf4dba4c51ab Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 3 Nov 2023 16:51:15 +0100 Subject: [PATCH 39/50] [hardware, Bender] Bump dependencies --- Bender.local | 6 ++++++ Bender.lock | 34 +++++++++++++--------------------- Bender.yml | 10 +++++----- hardware/Makefile | 11 +++++------ hardware/tb/dpi/elfloader.cc | 2 +- 5 files changed, 30 insertions(+), 33 deletions(-) create mode 100644 Bender.local diff --git a/Bender.local b/Bender.local new file mode 100644 index 000000000..f1055d810 --- /dev/null +++ b/Bender.local @@ -0,0 +1,6 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +overrides: + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } diff --git a/Bender.lock b/Bender.lock index d25f39744..dc39c2929 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,8 +7,7 @@ packages: dependencies: - common_cells ariane: - cva6: - revision: 3fddb6e5814604c7ec49e4320de0037292346c63 + revision: b0d6f496910b3b8a0387134d5b91f7c8194bdf37 version: null source: Git: https://github.com/pulp-platform/cva6.git @@ -17,34 +16,27 @@ packages: - common_cells - fpnew - tech_cells_generic - apb: - revision: 77ddf073f194d44b9119949d2421be59789e69ae - version: 0.2.4 - source: - Git: https://github.com/pulp-platform/apb.git - dependencies: - - common_cells axi: - revision: null - version: null + revision: 9251564ed67e3e71adf46dbeba62ef4435d2524c + version: 0.31.1 source: - Path: hardware/deps/axi + Git: https://github.com/pulp-platform/axi.git dependencies: - common_cells - common_verification common_cells: - revision: null - version: null + revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f + version: 1.32.0 source: - Path: hardware/deps/common_cells + Git: https://github.com/pulp-platform/common_cells.git dependencies: - common_verification - tech_cells_generic common_verification: - revision: null - version: null + revision: 9c07fa860593b2caabd9b5681740c25fac04b878 + version: 0.2.3 source: - Path: hardware/deps/common_verification + Git: https://github.com/pulp-platform/common_verification.git dependencies: [] fpnew: revision: 3116391bf66660f806b45e212b9949c528b4e270 @@ -62,9 +54,9 @@ packages: dependencies: - common_cells tech_cells_generic: - revision: null - version: null + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 source: - Path: hardware/deps/tech_cells_generic + Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: - common_verification diff --git a/Bender.yml b/Bender.yml index dd9f182aa..ba80dfd24 100644 --- a/Bender.yml +++ b/Bender.yml @@ -8,11 +8,11 @@ package: - "Paul Scheffler " dependencies: - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } - cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: acc_port_rerebase } - tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.1 } - apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } + ariane: { git: "https://github.com/pulp-platform/cva6.git", rev: acc_port_rebase } + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } + apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } workspace: checkout_dir: "hardware/deps" diff --git a/hardware/Makefile b/hardware/Makefile index 627a920ef..5117701c0 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -144,11 +144,11 @@ $(buildpath)/$(library): .PHONY: compile compile: dpi lib $(buildpath) bender $(buildpath)/compile_$(config).tcl $(buildpath)/compile_$(config).tcl: $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) - ./bender script vsim --vlog-arg="$(vlog_args)" -t rtl -t asic -t ara_test -t cva6_test -t cv64a6_imafdcv_sv39 $(bender_defs) > $(buildpath)/compile_$(config).tcl + $(BENDER) script vsim --vlog-arg="$(vlog_args)" -t rtl -t asic -t ara_test -t cva6_test -t cv64a6_imafdcv_sv39 -t tech_cells_generic_include_tc_sram -t tech_cells_generic_include_tc_clk $(bender_defs) > $(buildpath)/compile_$(config).tcl echo "exit" >> $(buildpath)/compile_$(config).tcl cd $(buildpath) && $(questa_cmd) vsim -work $(library) -c -do compile_$(config).tcl - # Remove the file if compilation did not succeed - if [ `cat $(buildpath)/transcript | grep "\*\* Error" | wc -l` -ne 0 ]; then rm $(buildpath)/compile_$(config).tcl; fi + # Rename the file if compilation did not succeed + if [ `cat $(buildpath)/transcript | grep "\*\* Error" | wc -l` -ne 0 ]; then mv $(buildpath)/compile_$(config).tcl $(buildpath)/compile_$(config).tcl.ERROR; fi # Simulation .PHONY: sim @@ -176,7 +176,7 @@ verilate: $(buildpath) bender $(veril_library)/V$(veril_top) $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) rm -rf $(veril_library); mkdir -p $(veril_library) - ./bender script verilator -t rtl -t ara_test -t cva6_test -t cv64a6_imafdcv_sv39 -t verilator $(bender_defs) > $(veril_library)/bender_script_$(config) + $(BENDER) script verilator -t rtl -t ara_test -t cva6_test -t cv64a6_imafdcv_sv39 -t verilator $(bender_defs) > $(veril_library)/bender_script_$(config) # Verilate the design $(veril_path)/verilator -f $(veril_library)/bender_script_$(config) \ -GNrLanes=$(nr_lanes) \ @@ -194,8 +194,7 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi -Wno-WIDTH \ -Wno-WIDTHCONCAT \ -Wno-ENUMVALUE \ - -Wno-COMBDLY - \ + -Wno-COMBDLY \ -Wall \ --hierarchical \ tb/verilator/waiver.vlt \ diff --git a/hardware/tb/dpi/elfloader.cc b/hardware/tb/dpi/elfloader.cc index 7e0528f54..0df988270 120000 --- a/hardware/tb/dpi/elfloader.cc +++ b/hardware/tb/dpi/elfloader.cc @@ -1 +1 @@ -../../deps/cva6/corev_apu/tb/dpi/elfloader.cc \ No newline at end of file +../../deps/ariane/corev_apu/tb/dpi/elfloader.cc \ No newline at end of file From 9da37166a0668e6b37e18469e75a0f15d17c6c82 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 10 Nov 2023 13:23:28 +0100 Subject: [PATCH 40/50] [bender] Bump cva6 (fix missing dependency in bender) --- Bender.lock | 40 ++++++++++++++++++++-------------------- Bender.yml | 2 +- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/Bender.lock b/Bender.lock index dc39c2929..ac5c18b46 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,56 +1,56 @@ packages: apb: - revision: 77ddf073f194d44b9119949d2421be59789e69ae - version: 0.2.4 + revision: null + version: null source: - Git: https://github.com/pulp-platform/apb.git + Path: hardware/deps/apb dependencies: - common_cells ariane: - revision: b0d6f496910b3b8a0387134d5b91f7c8194bdf37 + revision: null version: null source: - Git: https://github.com/pulp-platform/cva6.git + Path: hardware/deps/ariane dependencies: - axi - common_cells - fpnew - tech_cells_generic axi: - revision: 9251564ed67e3e71adf46dbeba62ef4435d2524c - version: 0.31.1 + revision: null + version: null source: - Git: https://github.com/pulp-platform/axi.git + Path: hardware/deps/axi dependencies: - common_cells - common_verification common_cells: - revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f - version: 1.32.0 + revision: null + version: null source: - Git: https://github.com/pulp-platform/common_cells.git + Path: hardware/deps/common_cells dependencies: - common_verification - tech_cells_generic common_verification: - revision: 9c07fa860593b2caabd9b5681740c25fac04b878 - version: 0.2.3 + revision: null + version: null source: - Git: https://github.com/pulp-platform/common_verification.git + Path: hardware/deps/common_verification dependencies: [] fpnew: - revision: 3116391bf66660f806b45e212b9949c528b4e270 - version: 0.7.0 + revision: null + version: null source: - Git: https://github.com/openhwgroup/cvfpu.git + Path: hardware/deps/fpnew dependencies: - common_cells - fpu_div_sqrt_mvp fpu_div_sqrt_mvp: - revision: 86e1f558b3c95e91577c41b2fc452c86b04e85ac - version: 1.0.4 + revision: null + version: null source: - Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git + Path: hardware/deps/fpu_div_sqrt_mvp dependencies: - common_cells tech_cells_generic: diff --git a/Bender.yml b/Bender.yml index ba80dfd24..2a2a1202e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -10,7 +10,7 @@ package: dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } - ariane: { git: "https://github.com/pulp-platform/cva6.git", rev: acc_port_rebase } + ariane: { git: "https://github.com/pulp-platform/cva6.git", rev: mp/acc_port_rebase } # mp/acc_port_rebase tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } From 16af65950ce917cb649d5b369aa1455c920511b3 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Mon, 13 Nov 2023 11:30:28 +0100 Subject: [PATCH 41/50] [hardware] Update bender targets --- hardware/Makefile | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hardware/Makefile b/hardware/Makefile index 5117701c0..3b8f2539d 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -104,8 +104,14 @@ dpi := $(patsubst tb/dpi/%.cc,$(buildpath)/$(dpi_library)/%.o,$(wildcard tb/dp vlog_args += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 vlog_args += -work $(library) +# Bender # Defines bender_defs += --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen) --define ARIANE_ACCELERATOR_PORT=1 +# Targets +bender_common_targs := -t rtl -t cv64a6_imafdcv_sv39 -t tech_cells_generic_include_tc_sram -t tech_cells_generic_include_tc_clk +bender_targs_simc := $(bender_common_targs) -t ara_test -t cva6_test +bender_targs_veril := $(bender_common_targs) -t ara_test -t cva6_test -t verilator +bender_targs_spyglass := $(bender_common_targs) -t spyglass # Default target all: compile @@ -144,7 +150,7 @@ $(buildpath)/$(library): .PHONY: compile compile: dpi lib $(buildpath) bender $(buildpath)/compile_$(config).tcl $(buildpath)/compile_$(config).tcl: $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) - $(BENDER) script vsim --vlog-arg="$(vlog_args)" -t rtl -t asic -t ara_test -t cva6_test -t cv64a6_imafdcv_sv39 -t tech_cells_generic_include_tc_sram -t tech_cells_generic_include_tc_clk $(bender_defs) > $(buildpath)/compile_$(config).tcl + $(BENDER) script vsim --vlog-arg="$(vlog_args)" $(bender_targs_simc) $(bender_defs) > $(buildpath)/compile_$(config).tcl echo "exit" >> $(buildpath)/compile_$(config).tcl cd $(buildpath) && $(questa_cmd) vsim -work $(library) -c -do compile_$(config).tcl # Rename the file if compilation did not succeed @@ -176,7 +182,7 @@ verilate: $(buildpath) bender $(veril_library)/V$(veril_top) $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) rm -rf $(veril_library); mkdir -p $(veril_library) - $(BENDER) script verilator -t rtl -t ara_test -t cva6_test -t cv64a6_imafdcv_sv39 -t verilator $(bender_defs) > $(veril_library)/bender_script_$(config) + $(BENDER) script verilator $(bender_targs_veril) $(bender_defs) > $(veril_library)/bender_script_$(config) # Verilate the design $(veril_path)/verilator -f $(veril_library)/bender_script_$(config) \ -GNrLanes=$(nr_lanes) \ @@ -239,7 +245,7 @@ lint: spyglass/tmp/files spyglass/sdc/func.sdc spyglass/scripts/run_lint.tcl spyglass/tmp/files: $(bender) mkdir -p spyglass/tmp - $(BENDER) script verilator -t rtl -t spyglass -t cva6_test -t cv64a6_imafdcv_sv39 $(bender_defs) --define SPYGLASS > spyglass/tmp/files + $(BENDER) script verilator $(bender_targs_spyglass) $(bender_defs) --define SPYGLASS > spyglass/tmp/files # DPIs .PHONY: dpi From 48b155aa30d1f0f640272e825215482f44b93ebe Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Mon, 13 Nov 2023 13:39:25 +0100 Subject: [PATCH 42/50] [hardware] Update tc_sram patch --- .../0001-tech-cells-generic-sram.patch | 71 +++++++++++-------- 1 file changed, 42 insertions(+), 29 deletions(-) diff --git a/hardware/patches/0001-tech-cells-generic-sram.patch b/hardware/patches/0001-tech-cells-generic-sram.patch index dc1e1a99b..054143245 100644 --- a/hardware/patches/0001-tech-cells-generic-sram.patch +++ b/hardware/patches/0001-tech-cells-generic-sram.patch @@ -1,38 +1,51 @@ diff --git a/src/rtl/tc_sram.sv b/src/rtl/tc_sram.sv -index 53530e0..075dcea 100644 +index b702a11..eeef776 100644 --- a/src/rtl/tc_sram.sv +++ b/src/rtl/tc_sram.sv -@@ -124,9 +124,11 @@ module tc_sram #( - // write memory array - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin -+ `ifndef VERILATOR - for (int unsigned i = 0; i < NumWords; i++) begin - sram[i] <= init_val[i]; - end -+ `endif - for (int i = 0; i < NumPorts; i++) begin - r_addr_q[i] <= {AddrWidth{1'b0}}; - // initialize the read output register for each port -@@ -149,12 +151,14 @@ module tc_sram #( - for (int unsigned i = 0; i < NumPorts; i++) begin - if (req_i[i]) begin - if (we_i[i]) begin +@@ -145,12 +145,14 @@ module tc_sram #( + for (int unsigned i = 0; i < NumPorts; i++) begin + if (req_i[i]) begin + if (we_i[i]) begin + `ifndef VERILATOR - // update value when write is set at clock - for (int unsigned j = 0; j < DataWidth; j++) begin - if (be_i[i][j/ByteWidth]) begin - sram[addr_i[i]][j] <= wdata_i[i][j]; + // update value when write is set at clock + for (int unsigned j = 0; j < BeWidth; j++) begin + if (be_i[i][j]) begin + sram[addr_i[i]][j*ByteWidth+:ByteWidth] <= wdata_i[i][j*ByteWidth+:ByteWidth]; + end end - end + `endif - end else begin - // otherwise update read address for subsequent non request cycles - r_addr_q[i] <= addr_i[i]; -@@ -164,6 +168,23 @@ module tc_sram #( - end // if !rst_ni + end else begin + // otherwise update read address for subsequent non request cycles + r_addr_q[i] <= addr_i[i]; +@@ -163,7 +165,9 @@ module tc_sram #( + // write memory array + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin ++ `ifndef VERILATOR + sram <= init_val; ++ `endif + for (int i = 0; i < NumPorts; i++) begin + r_addr_q[i] <= {AddrWidth{1'b0}}; + // initialize the read output register for each port +@@ -186,12 +190,14 @@ module tc_sram #( + for (int unsigned i = 0; i < NumPorts; i++) begin + if (req_i[i]) begin + if (we_i[i]) begin ++ `ifndef VERILATOR + // update value when write is set at clock + for (int unsigned j = 0; j < BeWidth; j++) begin + if (be_i[i][j]) begin + sram[addr_i[i]][j*ByteWidth+:ByteWidth] <= wdata_i[i][j*ByteWidth+:ByteWidth]; + end + end ++ `endif + end else begin + // otherwise update read address for subsequent non request cycles + r_addr_q[i] <= addr_i[i]; +@@ -202,6 +208,23 @@ module tc_sram #( + end end - + + `ifdef VERILATOR + for (genvar i = 0; i < NumPorts; i++) begin + // update value when write is set at clock @@ -53,7 +66,7 @@ index 53530e0..075dcea 100644 // Validate parameters. // pragma translate_off `ifndef VERILATOR -@@ -204,4 +225,59 @@ module tc_sram #( +@@ -242,4 +265,59 @@ module tc_sram #( `endif `endif // pragma translate_on From fe7ac55b2cb45a83777b14c6a110da5fecc40a3e Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Mon, 13 Nov 2023 14:08:37 +0100 Subject: [PATCH 43/50] [Bender, hardware] Bump axi to v0.39.1 --- Bender.local | 1 + Bender.lock | 41 ++++++++++++++++++++------------------- Bender.yml | 2 +- hardware/src/ara_soc.sv | 5 +++-- hardware/src/vlsu/vlsu.sv | 14 ++++++------- 5 files changed, 33 insertions(+), 30 deletions(-) diff --git a/Bender.local b/Bender.local index f1055d810..b18c329f5 100644 --- a/Bender.local +++ b/Bender.local @@ -3,4 +3,5 @@ # SPDX-License-Identifier: SHL-0.51 overrides: + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } diff --git a/Bender.lock b/Bender.lock index ac5c18b46..d5d413996 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,56 +1,57 @@ packages: apb: - revision: null - version: null + revision: 77ddf073f194d44b9119949d2421be59789e69ae + version: 0.2.4 source: - Path: hardware/deps/apb + Git: https://github.com/pulp-platform/apb.git dependencies: - common_cells ariane: - revision: null + revision: 44f387fb71464336cab47597c433411345ae4a6e version: null source: - Path: hardware/deps/ariane + Git: https://github.com/pulp-platform/cva6.git dependencies: - axi - common_cells - fpnew - tech_cells_generic axi: - revision: null - version: null + revision: fccffb5953ec8564218ba05e20adbedec845e014 + version: 0.39.1 source: - Path: hardware/deps/axi + Git: https://github.com/pulp-platform/axi.git dependencies: - common_cells - common_verification + - tech_cells_generic common_cells: - revision: null - version: null + revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f + version: 1.32.0 source: - Path: hardware/deps/common_cells + Git: https://github.com/pulp-platform/common_cells.git dependencies: - common_verification - tech_cells_generic common_verification: - revision: null - version: null + revision: 9c07fa860593b2caabd9b5681740c25fac04b878 + version: 0.2.3 source: - Path: hardware/deps/common_verification + Git: https://github.com/pulp-platform/common_verification.git dependencies: [] fpnew: - revision: null - version: null + revision: 3116391bf66660f806b45e212b9949c528b4e270 + version: 0.7.0 source: - Path: hardware/deps/fpnew + Git: https://github.com/openhwgroup/cvfpu.git dependencies: - common_cells - fpu_div_sqrt_mvp fpu_div_sqrt_mvp: - revision: null - version: null + revision: 86e1f558b3c95e91577c41b2fc452c86b04e85ac + version: 1.0.4 source: - Path: hardware/deps/fpu_div_sqrt_mvp + Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git dependencies: - common_cells tech_cells_generic: diff --git a/Bender.yml b/Bender.yml index 2a2a1202e..b71e55cfa 100644 --- a/Bender.yml +++ b/Bender.yml @@ -8,7 +8,7 @@ package: - "Paul Scheffler " dependencies: - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } ariane: { git: "https://github.com/pulp-platform/cva6.git", rev: mp/acc_port_rebase } # mp/acc_port_rebase tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } diff --git a/hardware/src/ara_soc.sv b/hardware/src/ara_soc.sv index d1330d4ee..2806587e7 100644 --- a/hardware/src/ara_soc.sv +++ b/hardware/src/ara_soc.sv @@ -133,6 +133,7 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( MaxSlvTrans : 4, FallThrough : 1'b0, LatencyMode : axi_pkg::CUT_MST_PORTS, + PipelineStages : 0, AxiIdWidthSlvPorts: AxiSocIdWidth, AxiIdUsedSlvPorts : AxiSocIdWidth, UniqueIds : 1'b0, @@ -188,8 +189,8 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( axi_atop_filter #( .AxiIdWidth (AxiSocIdWidth ), .AxiMaxWriteTxns(4 ), - .req_t (soc_wide_req_t ), - .resp_t (soc_wide_resp_t) + .axi_req_t (soc_wide_req_t ), + .axi_resp_t (soc_wide_resp_t) ) i_l2mem_atop_filter ( .clk_i (clk_i ), .rst_ni (rst_ni ), diff --git a/hardware/src/vlsu/vlsu.sv b/hardware/src/vlsu/vlsu.sv index aa2e05283..b6904850c 100644 --- a/hardware/src/vlsu/vlsu.sv +++ b/hardware/src/vlsu/vlsu.sv @@ -84,13 +84,13 @@ module vlsu import ara_pkg::*; import rvv_pkg::*; #( axi_resp_t axi_resp; axi_cut #( - .ar_chan_t(axi_ar_t ), - .r_chan_t (axi_r_t ), - .aw_chan_t(axi_aw_t ), - .w_chan_t (axi_w_t ), - .b_chan_t (axi_b_t ), - .req_t (axi_req_t ), - .resp_t (axi_resp_t) + .ar_chan_t (axi_ar_t ), + .r_chan_t (axi_r_t ), + .aw_chan_t (axi_aw_t ), + .w_chan_t (axi_w_t ), + .b_chan_t (axi_b_t ), + .axi_req_t (axi_req_t ), + .axi_resp_t(axi_resp_t) ) i_axi_cut ( .clk_i (clk_i ), .rst_ni (rst_ni ), From 7be158fd8304398113dc201e0300a7fa2075be6b Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Mon, 13 Nov 2023 14:09:09 +0100 Subject: [PATCH 44/50] [hardware] Disable -Wall in verilator Otherwise, warnings are actually blocking --- hardware/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/hardware/Makefile b/hardware/Makefile index 3b8f2539d..21ddda25f 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -201,7 +201,6 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi -Wno-WIDTHCONCAT \ -Wno-ENUMVALUE \ -Wno-COMBDLY \ - -Wall \ --hierarchical \ tb/verilator/waiver.vlt \ --Mdir $(veril_library) \ From 7335828c3bf07def9839a3c88c64650994bba753 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Mon, 13 Nov 2023 18:48:46 +0100 Subject: [PATCH 45/50] [ci] Don't check the patch directory for whitespace changes --- .github/workflows/ci.yml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index c9fda5ee0..64b9d36cf 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -454,9 +454,10 @@ jobs: # are mandatory there if they exist. - name: Check for trailing whitespaces and tabs run: | - git diff --check $base HEAD -- \ - apps config hardware .github \ - *.md Bender.* Makefile + bash -O extglob -c \ + "git diff --check $base HEAD -- \ + apps config .github *.md Bender.* \ + Makefile hardware/!(patches)" ##################### # Benchmark stage # From 6c1920163436f8b2d33b5706880dc488f8406f39 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Tue, 28 Nov 2023 20:36:39 +0100 Subject: [PATCH 46/50] [hardware] :bug: Filter operand queue ready from sldu and addrgen The addrgen-sldu operand queue is common to slide unit and addrgen. Since it's shared, we should be sure not to sample a spurious ready from the wrong unit, i.e., when we are feeding the addrgen, we don't want spurious readies from the slide unit. The units should be responsible for avoiding sampling wrong data, but spurious ready signals can happen in specific corner cases. Fixing this without impacting timing is hard, so we just mask the ready signals here as well to avoid bugs. --- hardware/src/lane/operand_queues_stage.sv | 42 ++++++++++++++++------- hardware/src/vlsu/addrgen.sv | 7 ++-- 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/hardware/src/lane/operand_queues_stage.sv b/hardware/src/lane/operand_queues_stage.sv index 5ed714522..467584510 100644 --- a/hardware/src/lane/operand_queues_stage.sv +++ b/hardware/src/lane/operand_queues_stage.sv @@ -208,25 +208,41 @@ module operand_queues_stage import ara_pkg::*; import rvv_pkg::*; import cf_math * Slide Unit * ****************/ + // This operand queue is common to slide unit and addrgen. + // Since it's shared, we should be sure not to sample a + // spurious ready from the wrong unit, i.e., when we are + // feeding the addrgen, we don't want spurious readies from + // the slide unit. The units should be responsible for avoiding + // sampling wrong data, but spurious ready signals can happen in + // specific corner cases. Fixing this without impacting timing is + // hard, so we just mask the ready signals here as well to avoid + // bugs. + logic sldu_operand_ready_filtered; + logic addrgen_operand_ready_filtered; + assign sldu_operand_ready_filtered = sldu_operand_ready_i & + (sldu_addrgen_operand_target_fu_o == ALU_SLDU); + assign addrgen_operand_ready_filtered = addrgen_operand_ready_i & + (sldu_addrgen_operand_target_fu_o == MFPU_ADDRGEN); + operand_queue #( .CmdBufDepth (VlduInsnQueueDepth), .DataBufDepth (2 ), .FPUSupport (FPUSupport ), .NrLanes (NrLanes ) ) i_operand_queue_slide_addrgen_a ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .lane_id_i (lane_id_i ), - .operand_queue_cmd_i (operand_queue_cmd_i[SlideAddrGenA] ), - .operand_queue_cmd_valid_i(operand_queue_cmd_valid_i[SlideAddrGenA] ), - .operand_i (operand_i[SlideAddrGenA] ), - .operand_valid_i (operand_valid_i[SlideAddrGenA] ), - .operand_issued_i (operand_issued_i[SlideAddrGenA] ), - .operand_queue_ready_o (operand_queue_ready_o[SlideAddrGenA] ), - .operand_o (sldu_addrgen_operand_o ), - .operand_target_fu_o (sldu_addrgen_operand_target_fu_o ), - .operand_valid_o (sldu_addrgen_operand_valid_o ), - .operand_ready_i (addrgen_operand_ready_i | sldu_operand_ready_i) + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .lane_id_i (lane_id_i ), + .operand_queue_cmd_i (operand_queue_cmd_i[SlideAddrGenA] ), + .operand_queue_cmd_valid_i(operand_queue_cmd_valid_i[SlideAddrGenA] ), + .operand_i (operand_i[SlideAddrGenA] ), + .operand_valid_i (operand_valid_i[SlideAddrGenA] ), + .operand_issued_i (operand_issued_i[SlideAddrGenA] ), + .operand_queue_ready_o (operand_queue_ready_o[SlideAddrGenA] ), + .operand_o (sldu_addrgen_operand_o ), + .operand_target_fu_o (sldu_addrgen_operand_target_fu_o ), + .operand_valid_o (sldu_addrgen_operand_valid_o ), + .operand_ready_i (addrgen_operand_ready_filtered | sldu_operand_ready_filtered) ); ///////////////// diff --git a/hardware/src/vlsu/addrgen.sv b/hardware/src/vlsu/addrgen.sv index 2fbe05e55..a25d086a1 100644 --- a/hardware/src/vlsu/addrgen.sv +++ b/hardware/src/vlsu/addrgen.sv @@ -324,9 +324,10 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #( // Bump lane pointer elm_ptr_d = '0; word_lane_ptr_d += 1; - if (word_lane_ptr_q == NrLanes - 1) - // Ready for the next full word - addrgen_operand_ready_o = 1'b1; + if (word_lane_ptr_q == NrLanes - 1) begin + // Ready for the next full word + addrgen_operand_ready_o = 1'b1; + end end else begin // Bump element pointer elm_ptr_d += 1; From a2ee7ee4f75e9a98302bf58ecc9a91aae94c6e32 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Wed, 29 Nov 2023 13:13:40 +0100 Subject: [PATCH 47/50] [Bender] Bump CVA6 and fix its commit Implement clock gating on the unused cache banks --- Bender.local | 2 +- Bender.lock | 2 +- Bender.yml | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Bender.local b/Bender.local index b18c329f5..5d8caebc0 100644 --- a/Bender.local +++ b/Bender.local @@ -3,5 +3,5 @@ # SPDX-License-Identifier: SHL-0.51 overrides: - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } diff --git a/Bender.lock b/Bender.lock index d5d413996..b1a28f968 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,7 +7,7 @@ packages: dependencies: - common_cells ariane: - revision: 44f387fb71464336cab47597c433411345ae4a6e + revision: 2ebe023f7289300348c68e99267afcc03256f3ed version: null source: Git: https://github.com/pulp-platform/cva6.git diff --git a/Bender.yml b/Bender.yml index b71e55cfa..ffe56f936 100644 --- a/Bender.yml +++ b/Bender.yml @@ -8,11 +8,11 @@ package: - "Paul Scheffler " dependencies: - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } - ariane: { git: "https://github.com/pulp-platform/cva6.git", rev: mp/acc_port_rebase } # mp/acc_port_rebase - tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } - apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } + ariane: { git: "https://github.com/pulp-platform/cva6.git", rev: 2ebe023f7289300348c68e99267afcc03256f3ed } # mp/acc_port_rebase + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } + apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } workspace: checkout_dir: "hardware/deps" From b0bd889eb584990cc2b3f3879a948bcec3d4bb9a Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 1 Dec 2023 10:36:38 +0100 Subject: [PATCH 48/50] [hardware] Patch bender dependency --- hardware/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hardware/Makefile b/hardware/Makefile index 21ddda25f..0b72af6a6 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -120,8 +120,9 @@ all: compile $(buildpath): mkdir -p $(buildpath) -.PHONY: $(BENDER) update +.PHONY: bender update # Bender +bender: $(BENDER) $(BENDER): @[ -x $(BENDER) ] && echo "Bender already exists." || \ curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- $(BENDER_VERSION) From 90e4e75dbe777b419a66fa554f38cdfb47c73e2c Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 1 Dec 2023 10:36:52 +0100 Subject: [PATCH 49/50] [README] Update readme --- README.md | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 96719e765..4412208b7 100644 --- a/README.md +++ b/README.md @@ -97,13 +97,38 @@ make riscv_tests ## RTL Simulation -To simulate the Ara system with ModelSim, go to the `hardware` folder, which contains all the SystemVerilog files. Use the following command to run your simulation: +### Hardware dependencies + +The Ara repository depends on external IPs and uses Bender to handle the IP dependencies. +To install Bender and initialize all the hardware IPs, run the following commands: + +```bash +# Go to the hardware folder +cd hardware +# Install Bender and checkout all the IPs +make update +``` + +### Patches (only once!) + +Note: this step is required only once, and needs to be repeated ONLY if the IP hardware dependencies are deleted and checked out again. + +Some of the IPs need to be patched to work with Verilator. ```bash # Go to the hardware folder cd hardware # Apply the patches (only need to run this once) make apply-patches +``` + +### Simulation + +To simulate the Ara system with ModelSim, go to the `hardware` folder, which contains all the SystemVerilog files. Use the following command to run your simulation: + +```bash +# Go to the hardware folder +cd hardware # Only compile the hardware without running the simulation. make compile # Run the simulation with the *hello_world* binary loaded From 2175df208aa9735ddfb4b31802c93e6ff85c3209 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 1 Dec 2023 10:43:50 +0100 Subject: [PATCH 50/50] [CHANGELOG] Update Changelog --- CHANGELOG.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 454448f22..c3513976f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -80,6 +80,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Reset gating registers before the integer multipliers in `vmfpu` - Fix narrowing for `vnclip` and `vnclipu` - NaN-box the scalar value before forwarding back to CVA6 + - Filter operand queue ready_i from addrgen and sldu selectively when they should not handshake + - CI: don't check the patch directory for whitespace changes ### Added @@ -189,6 +191,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Simplify the datapath of the slide unit. The `sldu` supports only powers of two, and cannot slide and reshuffle at the same time. Non-power-of-two slides are now handled with micro operations. - Bump Verilator to v5.012 - Only allow one workflow at a time per branch/PR + - Bump CVA6 version following OpenHW Group's modification + - Bump fpnew to CVFPU + - Switch from git submodules to Bender to handle hardware dependencies + - Bump AXI, tech_cells_generic, and common_cells dependencies ## 2.2.0 - 2021-11-02