diff --git a/include/axi/typedef.svh b/include/axi/typedef.svh index 5eec91171..e409273ab 100644 --- a/include/axi/typedef.svh +++ b/include/axi/typedef.svh @@ -13,6 +13,7 @@ // - Andreas Kurth // - Florian Zaruba // - Wolfgang Roenninger +// - Thomas Benz // Macros to define AXI and AXI-Lite Channel and Request/Response Structs @@ -23,62 +24,62 @@ // AXI4+ATOP Channel and Request/Response Structs // // Usage Example: -// `AXI_TYPEDEF_AW_CHAN_T(axi_aw_t, axi_addr_t, axi_id_t, axi_user_t) -// `AXI_TYPEDEF_W_CHAN_T(axi_w_t, axi_data_t, axi_strb_t, axi_user_t) -// `AXI_TYPEDEF_B_CHAN_T(axi_b_t, axi_id_t, axi_user_t) -// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_user_t) -// `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_user_t) +// `AXI_TYPEDEF_AW_CHAN_T(axi_aw_t, axi_addr_t, axi_id_t, axi_aw_user_t) +// `AXI_TYPEDEF_W_CHAN_T(axi_w_t, axi_data_t, axi_strb_t, axi_w_user_t) +// `AXI_TYPEDEF_B_CHAN_T(axi_b_t, axi_id_t, axi_b_user_t) +// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_ar_user_t) +// `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_r_user_t) // `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_t, axi_w_t, axi_ar_t) // `AXI_TYPEDEF_RESP_T(axi_resp_t, axi_b_t, axi_r_t) -`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) \ - typedef struct packed { \ - id_t id; \ - addr_t addr; \ - axi_pkg::len_t len; \ - axi_pkg::size_t size; \ - axi_pkg::burst_t burst; \ - logic lock; \ - axi_pkg::cache_t cache; \ - axi_pkg::prot_t prot; \ - axi_pkg::qos_t qos; \ - axi_pkg::region_t region; \ - axi_pkg::atop_t atop; \ - user_t user; \ +`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) \ + typedef struct packed { \ + id_t id; \ + addr_t addr; \ + axi_pkg::len_t len; \ + axi_pkg::size_t size; \ + axi_pkg::burst_t burst; \ + logic lock; \ + axi_pkg::cache_t cache; \ + axi_pkg::prot_t prot; \ + axi_pkg::qos_t qos; \ + axi_pkg::region_t region; \ + axi_pkg::atop_t atop; \ + aw_user_t user; \ } aw_chan_t; -`define AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) \ - typedef struct packed { \ - data_t data; \ - strb_t strb; \ - logic last; \ - user_t user; \ +`define AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) \ + typedef struct packed { \ + data_t data; \ + strb_t strb; \ + logic last; \ + w_user_t user; \ } w_chan_t; -`define AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) \ - typedef struct packed { \ - id_t id; \ - axi_pkg::resp_t resp; \ - user_t user; \ +`define AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) \ + typedef struct packed { \ + id_t id; \ + axi_pkg::resp_t resp; \ + b_user_t user; \ } b_chan_t; -`define AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) \ - typedef struct packed { \ - id_t id; \ - addr_t addr; \ - axi_pkg::len_t len; \ - axi_pkg::size_t size; \ - axi_pkg::burst_t burst; \ - logic lock; \ - axi_pkg::cache_t cache; \ - axi_pkg::prot_t prot; \ - axi_pkg::qos_t qos; \ - axi_pkg::region_t region; \ - user_t user; \ +`define AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) \ + typedef struct packed { \ + id_t id; \ + addr_t addr; \ + axi_pkg::len_t len; \ + axi_pkg::size_t size; \ + axi_pkg::burst_t burst; \ + logic lock; \ + axi_pkg::cache_t cache; \ + axi_pkg::prot_t prot; \ + axi_pkg::qos_t qos; \ + axi_pkg::region_t region; \ + ar_user_t user; \ } ar_chan_t; -`define AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) \ - typedef struct packed { \ - id_t id; \ - data_t data; \ - axi_pkg::resp_t resp; \ - logic last; \ - user_t user; \ +`define AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) \ + typedef struct packed { \ + id_t id; \ + data_t data; \ + axi_pkg::resp_t resp; \ + logic last; \ + r_user_t user; \ } r_chan_t; `define AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) \ typedef struct packed { \ @@ -105,27 +106,44 @@ //////////////////////////////////////////////////////////////////////////////////////////////////// -// All AXI4+ATOP Channels and Request/Response Structs in One Macro - Custom Type Name Version +// All AXI4+ATOP Channels and Request/Response Structs in One Macro - Custom Type Name and +// Per-channel Custom User Signal Version // // This can be used whenever the user is not interested in "precise" control of the naming of the // individual channels. // // Usage Example: -// `AXI_TYPEDEF_ALL_CT(axi, axi_req_t, axi_rsp_t, addr_t, id_t, data_t, strb_t, user_t) +// `AXI_TYPEDEF_ALL_CT_PU(axi, axi_req_t, axi_rsp_t, addr_t, id_t, data_t, strb_t, aw_user_t, w_user_t, b_user_t, ar_user_t, r_user_t) // // This defines `axi_req_t` and `axi_rsp_t` request/response structs as well as `axi_aw_chan_t`, // `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs. -`define AXI_TYPEDEF_ALL_CT(__name, __req, __rsp, __addr_t, __id_t, __data_t, __strb_t, __user_t) \ - `AXI_TYPEDEF_AW_CHAN_T(__name``_aw_chan_t, __addr_t, __id_t, __user_t) \ - `AXI_TYPEDEF_W_CHAN_T(__name``_w_chan_t, __data_t, __strb_t, __user_t) \ - `AXI_TYPEDEF_B_CHAN_T(__name``_b_chan_t, __id_t, __user_t) \ - `AXI_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t, __id_t, __user_t) \ - `AXI_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t, __id_t, __user_t) \ - `AXI_TYPEDEF_REQ_T(__req, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \ +`define AXI_TYPEDEF_ALL_CT_PU(__name, __req, __rsp, __addr_t, __id_t, __data_t, __strb_t, __aw_user_t, __w_user_t, __b_user_t, __ar_user_t, __r_user_t) \ + `AXI_TYPEDEF_AW_CHAN_T(__name``_aw_chan_t, __addr_t, __id_t, __aw_user_t) \ + `AXI_TYPEDEF_W_CHAN_T(__name``_w_chan_t, __data_t, __strb_t, __w_user_t) \ + `AXI_TYPEDEF_B_CHAN_T(__name``_b_chan_t, __id_t, __b_user_t) \ + `AXI_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t, __id_t, __ar_user_t) \ + `AXI_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t, __id_t, __r_user_t) \ + `AXI_TYPEDEF_REQ_T(__req, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \ `AXI_TYPEDEF_RESP_T(__rsp, __name``_b_chan_t, __name``_r_chan_t) //////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// +// All AXI4+ATOP Channels and Request/Response Structs in One Macro - Custom Type Name Version +// +// This can be used whenever the user is not interested in "precise" control of the naming of the +// individual channels. +// +// Usage Example: +// `AXI_TYPEDEF_ALL_CT_PU(axi, axi_req_t, axi_rsp_t, addr_t, id_t, data_t, strb_t, user_t) +// +// This defines `axi_req_t` and `axi_rsp_t` request/response structs as well as `axi_aw_chan_t`, +// `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs. +`define AXI_TYPEDEF_ALL_CT(__name, __req, __rsp, __addr_t, __id_t, __data_t, __strb_t, __user_t) \ + `AXI_TYPEDEF_ALL_CT_PU(__name, __req, __rsp, __addr_t, __id_t, __data_t, __strb_t, __user_t, __user_t, __user_t, __user_t, __user_t) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + //////////////////////////////////////////////////////////////////////////////////////////////////// // All AXI4+ATOP Channels and Request/Response Structs in One Macro // @@ -137,8 +155,8 @@ // // This defines `axi_req_t` and `axi_resp_t` request/response structs as well as `axi_aw_chan_t`, // `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs. -`define AXI_TYPEDEF_ALL(__name, __addr_t, __id_t, __data_t, __strb_t, __user_t) \ - `AXI_TYPEDEF_ALL_CT(__name, __name``_req_t, __name``_resp_t, __addr_t, __id_t, __data_t, __strb_t, __user_t) +`define AXI_TYPEDEF_ALL(__name, __addr_t, __id_t, __data_t, __strb_t, __user_t) \ + `AXI_TYPEDEF_ALL_CT(__name, __name``_req_t, __name``_resp_t, __addr_t, __id_t, __data_t, __strb_t, __user_t, __user_t, __user_t, __user_t, __user_t) //////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/axi_atop_filter.sv b/src/axi_atop_filter.sv index de60516a3..2fe538102 100644 --- a/src/axi_atop_filter.sv +++ b/src/axi_atop_filter.sv @@ -374,15 +374,25 @@ endmodule /// Interface variant of [`axi_atop_filter`](module.axi_atop_filter). module axi_atop_filter_intf #( /// AXI ID width - parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, /// AXI address width - parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, /// AXI data width - parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, /// AXI user signal width - parameter int unsigned AXI_USER_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, /// Maximum number of in-flight AXI write transactions - parameter int unsigned AXI_MAX_WRITE_TXNS = 0 + parameter int unsigned AXI_MAX_WRITE_TXNS = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH ) ( /// Rising-edge clock of both ports input logic clk_i, @@ -394,17 +404,22 @@ module axi_atop_filter_intf #( AXI_BUS.Master mst ); - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) diff --git a/src/axi_cdc.sv b/src/axi_cdc.sv index 152cbef24..cc39233c6 100644 --- a/src/axi_cdc.sv +++ b/src/axi_cdc.sv @@ -124,12 +124,22 @@ endmodule // interface wrapper module axi_cdc_intf #( - parameter int unsigned AXI_ID_WIDTH = 0, - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_USER_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH, /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. - parameter int unsigned LOG_DEPTH = 1 + parameter int unsigned LOG_DEPTH = 32'd1 ) ( // slave side - clocked by `src_clk_i` input logic src_clk_i, @@ -141,18 +151,22 @@ module axi_cdc_intf #( AXI_BUS.Master dst ); - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) req_t src_req, dst_req; resp_t src_resp, dst_resp; diff --git a/src/axi_cdc_dst.sv b/src/axi_cdc_dst.sv index f252a9800..05169b19d 100644 --- a/src/axi_cdc_dst.sv +++ b/src/axi_cdc_dst.sv @@ -151,12 +151,22 @@ endmodule module axi_cdc_dst_intf #( - parameter int unsigned AXI_ID_WIDTH = 0, - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_USER_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH, /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. - parameter int unsigned LOG_DEPTH = 1 + parameter int unsigned LOG_DEPTH = 32'd1 ) ( // asynchronous slave port AXI_BUS_ASYNC_GRAY.Slave src, @@ -170,14 +180,18 @@ module axi_cdc_dst_intf #( typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; typedef logic [AXI_DATA_WIDTH-1:0] data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) req_t dst_req; resp_t dst_resp; diff --git a/src/axi_cdc_src.sv b/src/axi_cdc_src.sv index 614a17e45..c9f450d68 100644 --- a/src/axi_cdc_src.sv +++ b/src/axi_cdc_src.sv @@ -150,12 +150,22 @@ endmodule module axi_cdc_src_intf #( - parameter int unsigned AXI_ID_WIDTH = 0, - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_USER_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH. - parameter int unsigned LOG_DEPTH = 1 + parameter int unsigned LOG_DEPTH = 32'd1 ) ( // synchronous slave port - clocked by `src_clk_i` input logic src_clk_i, @@ -165,18 +175,22 @@ module axi_cdc_src_intf #( AXI_BUS_ASYNC_GRAY.Master dst ); - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) req_t src_req; resp_t src_resp; diff --git a/src/axi_cut.sv b/src/axi_cut.sv index 34278ca62..bbb90c43d 100644 --- a/src/axi_cut.sv +++ b/src/axi_cut.sv @@ -118,15 +118,25 @@ endmodule // interface wrapper module axi_cut_intf #( // Bypass eneable - parameter bit BYPASS = 1'b0, + parameter bit BYPASS = 1'b0, // The address width. - parameter int unsigned ADDR_WIDTH = 0, + parameter int unsigned ADDR_WIDTH = 32'd0, // The data width. - parameter int unsigned DATA_WIDTH = 0, + parameter int unsigned DATA_WIDTH = 32'd0, // The ID width. - parameter int unsigned ID_WIDTH = 0, + parameter int unsigned ID_WIDTH = 32'd0, // The user data width. - parameter int unsigned USER_WIDTH = 0 + parameter int unsigned USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = USER_WIDTH ) ( input logic clk_i , input logic rst_ni , @@ -134,17 +144,21 @@ module axi_cut_intf #( AXI_BUS.Master out ); - typedef logic [ID_WIDTH-1:0] id_t; - typedef logic [ADDR_WIDTH-1:0] addr_t; - typedef logic [DATA_WIDTH-1:0] data_t; - typedef logic [DATA_WIDTH/8-1:0] strb_t; - typedef logic [USER_WIDTH-1:0] user_t; + typedef logic [ID_WIDTH-1:0] id_t; + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) diff --git a/src/axi_delayer.sv b/src/axi_delayer.sv index 8d217d14e..7b06bc4c4 100644 --- a/src/axi_delayer.sv +++ b/src/axi_delayer.sv @@ -126,14 +126,24 @@ endmodule // interface wrapper module axi_delayer_intf #( // Synopsys DC requires a default value for parameters. - parameter int unsigned AXI_ID_WIDTH = 0, - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_USER_WIDTH = 0, - parameter bit STALL_RANDOM_INPUT = 0, - parameter bit STALL_RANDOM_OUTPUT = 0, - parameter int unsigned FIXED_DELAY_INPUT = 1, - parameter int unsigned FIXED_DELAY_OUTPUT = 1 + parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH + parameter bit STALL_RANDOM_INPUT = 32'd0, + parameter bit STALL_RANDOM_OUTPUT = 32'd0, + parameter int unsigned FIXED_DELAY_INPUT = 32'd1, + parameter int unsigned FIXED_DELAY_OUTPUT = 32'd1 ) ( input logic clk_i, input logic rst_ni, @@ -141,17 +151,21 @@ module axi_delayer_intf #( AXI_BUS.Master mst ); - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) diff --git a/src/axi_demux.sv b/src/axi_demux.sv index fc061ff09..418e06026 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -808,20 +808,30 @@ endmodule `include "axi/assign.svh" `include "axi/typedef.svh" module axi_demux_intf #( - parameter int unsigned AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params - parameter bit ATOP_SUPPORT = 1'b1, - parameter int unsigned AXI_ADDR_WIDTH = 32'd0, - parameter int unsigned AXI_DATA_WIDTH = 32'd0, - parameter int unsigned AXI_USER_WIDTH = 32'd0, - parameter int unsigned NO_MST_PORTS = 32'd3, - parameter int unsigned MAX_TRANS = 32'd8, - parameter int unsigned AXI_LOOK_BITS = 32'd3, - parameter bit UNIQUE_IDS = 1'b0, - parameter bit SPILL_AW = 1'b1, - parameter bit SPILL_W = 1'b0, - parameter bit SPILL_B = 1'b0, - parameter bit SPILL_AR = 1'b1, - parameter bit SPILL_R = 1'b0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params + parameter bit ATOP_SUPPORT = 1'b1, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned NO_MST_PORTS = 32'd3, + parameter int unsigned MAX_TRANS = 32'd8, + parameter int unsigned AXI_LOOK_BITS = 32'd3, + parameter bit UNIQUE_IDS = 1'b0, + parameter bit SPILL_AW = 1'b1, + parameter bit SPILL_W = 1'b0, + parameter bit SPILL_B = 1'b0, + parameter bit SPILL_AR = 1'b1, + parameter bit SPILL_R = 1'b0, // Dependent parameters, DO NOT OVERRIDE! parameter int unsigned SELECT_WIDTH = (NO_MST_PORTS > 32'd1) ? $clog2(NO_MST_PORTS) : 32'd1, parameter type select_t = logic [SELECT_WIDTH-1:0] // MST port select type @@ -835,16 +845,20 @@ module axi_demux_intf #( AXI_BUS.Master mst [NO_MST_PORTS-1:0] // master ports ); - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) diff --git a/src/axi_dumper.sv b/src/axi_dumper.sv index c3031ea5c..e258810d5 100644 --- a/src/axi_dumper.sv +++ b/src/axi_dumper.sv @@ -170,23 +170,37 @@ module axi_dumper_intf #( parameter int unsigned AXI_ID_WIDTH = 32'd0, parameter int unsigned AXI_ADDR_WIDTH = 32'd0, parameter int unsigned AXI_DATA_WIDTH = 32'd0, - parameter int unsigned AXI_USER_WIDTH = 32'd0 + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH ) ( input logic clk_i, input logic rst_ni, AXI_BUS_DV.Monitor axi_bus ); - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) diff --git a/src/axi_dw_converter.sv b/src/axi_dw_converter.sv index 7e6f6dad3..2e041dc9c 100644 --- a/src/axi_dw_converter.sv +++ b/src/axi_dw_converter.sv @@ -116,12 +116,22 @@ endmodule : axi_dw_converter `include "axi/typedef.svh" module axi_dw_converter_intf #( - parameter int unsigned AXI_ID_WIDTH = 1, - parameter int unsigned AXI_ADDR_WIDTH = 1, - parameter int unsigned AXI_SLV_PORT_DATA_WIDTH = 8, - parameter int unsigned AXI_MST_PORT_DATA_WIDTH = 8, - parameter int unsigned AXI_USER_WIDTH = 0, - parameter int unsigned AXI_MAX_READS = 8 + parameter int unsigned AXI_ID_WIDTH = 32'd1, + parameter int unsigned AXI_ADDR_WIDTH = 32'd1, + parameter int unsigned AXI_SLV_PORT_DATA_WIDTH = 32'd8, + parameter int unsigned AXI_MST_PORT_DATA_WIDTH = 32'd8, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_MAX_READS = 32'd8 ) ( input logic clk_i, input logic rst_ni, diff --git a/src/axi_dw_downsizer.sv b/src/axi_dw_downsizer.sv index 88d774ad0..159297181 100644 --- a/src/axi_dw_downsizer.sv +++ b/src/axi_dw_downsizer.sv @@ -20,11 +20,11 @@ // bursts, but only if they consist of a single beat; it will answer with SLVERR // on multi-beat FIXED bursts. module axi_dw_downsizer #( - parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads - parameter int unsigned AxiSlvPortDataWidth = 8 , // Data width of the slv port - parameter int unsigned AxiMstPortDataWidth = 8 , // Data width of the mst port - parameter int unsigned AxiAddrWidth = 1 , // Address width - parameter int unsigned AxiIdWidth = 1 , // ID width + parameter int unsigned AxiMaxReads = 32'd1, // Number of outstanding reads + parameter int unsigned AxiSlvPortDataWidth = 32'd8, // Data width of the slv port + parameter int unsigned AxiMstPortDataWidth = 32'd8, // Data width of the mst port + parameter int unsigned AxiAddrWidth = 32'd1, // Address width + parameter int unsigned AxiIdWidth = 32'd1, // ID width parameter type aw_chan_t = logic, // AW Channel Type parameter type mst_w_chan_t = logic, // W Channel Type for mst port parameter type slv_w_chan_t = logic, // W Channel Type for slv port diff --git a/src/axi_dw_upsizer.sv b/src/axi_dw_upsizer.sv index 9908b7860..632e97b4c 100644 --- a/src/axi_dw_upsizer.sv +++ b/src/axi_dw_upsizer.sv @@ -19,11 +19,11 @@ // upon receiving a burst of such type. module axi_dw_upsizer #( - parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads - parameter int unsigned AxiSlvPortDataWidth = 8 , // Data width of the slv port - parameter int unsigned AxiMstPortDataWidth = 8 , // Data width of the mst port - parameter int unsigned AxiAddrWidth = 1 , // Address width - parameter int unsigned AxiIdWidth = 1 , // ID width + parameter int unsigned AxiMaxReads = 32'd1, // Number of outstanding reads + parameter int unsigned AxiSlvPortDataWidth = 32'd8, // Data width of the slv port + parameter int unsigned AxiMstPortDataWidth = 32'd8, // Data width of the mst port + parameter int unsigned AxiAddrWidth = 32'd1, // Address width + parameter int unsigned AxiIdWidth = 32'd1, // ID width parameter type aw_chan_t = logic, // AW Channel Type parameter type mst_w_chan_t = logic, // W Channel Type for mst port parameter type slv_w_chan_t = logic, // W Channel Type for slv port diff --git a/src/axi_err_slv.sv b/src/axi_err_slv.sv index e7719c429..feae26cd3 100644 --- a/src/axi_err_slv.sv +++ b/src/axi_err_slv.sv @@ -17,14 +17,14 @@ // it. This module optionally supports ATOPs if the `ATOPs` parameter is set. module axi_err_slv #( - parameter int unsigned AxiIdWidth = 0, // AXI ID Width + parameter int unsigned AxiIdWidth = 32'd0, // AXI ID Width parameter type axi_req_t = logic, // AXI 4 request struct, with atop field parameter type axi_resp_t = logic, // AXI 4 response struct parameter axi_pkg::resp_t Resp = axi_pkg::RESP_DECERR, // Error generated by this slave. parameter int unsigned RespWidth = 32'd64, // Data response width, gets zero extended or truncated to r.data. parameter logic [RespWidth-1:0] RespData = 64'hCA11AB1EBADCAB1E, // Hexvalue for data return value parameter bit ATOPs = 1'b1, // Activate support for ATOPs. Set to 1 if this slave could ever get an atomic AXI transaction. - parameter int unsigned MaxTrans = 1 // Maximum # of accepted transactions before stalling + parameter int unsigned MaxTrans = 32'd1 // Maximum # of accepted transactions before stalling ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/src/axi_fifo.sv b/src/axi_fifo.sv index 8e4cbdfb1..1ccd70b45 100644 --- a/src/axi_fifo.sv +++ b/src/axi_fifo.sv @@ -165,12 +165,22 @@ endmodule // interface wrapper module axi_fifo_intf #( - parameter int unsigned ADDR_WIDTH = 0, // The address width. - parameter int unsigned DATA_WIDTH = 0, // The data width. - parameter int unsigned ID_WIDTH = 0, // The ID width. - parameter int unsigned USER_WIDTH = 0, // The user data width. - parameter int unsigned DEPTH = 0, // The number of FiFo slots. - parameter int unsigned FALL_THROUGH = 0 // FiFo in fall-through mode + parameter int unsigned ADDR_WIDTH = 32'd0, // The address width. + parameter int unsigned DATA_WIDTH = 32'd0, // The data width. + parameter int unsigned ID_WIDTH = 32'd0, // The ID width. + parameter int unsigned USER_WIDTH = 32'd0, // The user data width. + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = USER_WIDTH + parameter int unsigned DEPTH = 32'd0, // The number of FiFo slots. + parameter int unsigned FALL_THROUGH = 32'd0 // FiFo in fall-through mode ) ( input logic clk_i, input logic rst_ni, @@ -179,17 +189,21 @@ module axi_fifo_intf #( AXI_BUS.Master mst ); - typedef logic [ID_WIDTH-1:0] id_t; - typedef logic [ADDR_WIDTH-1:0] addr_t; - typedef logic [DATA_WIDTH-1:0] data_t; - typedef logic [DATA_WIDTH/8-1:0] strb_t; - typedef logic [USER_WIDTH-1:0] user_t; + typedef logic [ID_WIDTH-1:0] id_t; + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) diff --git a/src/axi_id_prepend.sv b/src/axi_id_prepend.sv index e9359b902..9c621c637 100644 --- a/src/axi_id_prepend.sv +++ b/src/axi_id_prepend.sv @@ -16,9 +16,9 @@ // Constraints enforced through assertions: ID width of slave and master port module axi_id_prepend #( - parameter int unsigned NoBus = 1, // Can take multiple axi busses - parameter int unsigned AxiIdWidthSlvPort = 4, // AXI ID Width of the Slave Ports - parameter int unsigned AxiIdWidthMstPort = 6, // AXI ID Width of the Master Ports + parameter int unsigned NoBus = 32'd1, // Can take multiple axi busses + parameter int unsigned AxiIdWidthSlvPort = 32'd4, // AXI ID Width of the Slave Ports + parameter int unsigned AxiIdWidthMstPort = 32'd6, // AXI ID Width of the Master Ports parameter type slv_aw_chan_t = logic, // AW Channel Type for slv port parameter type slv_w_chan_t = logic, // W Channel Type for slv port parameter type slv_b_chan_t = logic, // B Channel Type for slv port diff --git a/src/axi_id_remap.sv b/src/axi_id_remap.sv index 85dc66e0d..d3cd0ee8f 100644 --- a/src/axi_id_remap.sv +++ b/src/axi_id_remap.sv @@ -581,13 +581,23 @@ endmodule /// /// See the documentation of the main module for the definition of ports and parameters. module axi_id_remap_intf #( - parameter int unsigned AXI_SLV_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_SLV_PORT_ID_WIDTH = 32'd0, parameter int unsigned AXI_SLV_PORT_MAX_UNIQ_IDS = 32'd0, - parameter int unsigned AXI_MAX_TXNS_PER_ID = 32'd0, - parameter int unsigned AXI_MST_PORT_ID_WIDTH = 32'd0, - parameter int unsigned AXI_ADDR_WIDTH = 32'd0, - parameter int unsigned AXI_DATA_WIDTH = 32'd0, - parameter int unsigned AXI_USER_WIDTH = 32'd0 + parameter int unsigned AXI_MAX_TXNS_PER_ID = 32'd0, + parameter int unsigned AXI_MST_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH ) ( input logic clk_i, input logic rst_ni, @@ -599,21 +609,25 @@ module axi_id_remap_intf #( typedef logic [AXI_ADDR_WIDTH-1:0] axi_addr_t; typedef logic [AXI_DATA_WIDTH-1:0] axi_data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] axi_strb_t; - typedef logic [AXI_USER_WIDTH-1:0] axi_user_t; - - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) + typedef logic [AXI_AW_USER_WIDTH-1:0] axi_aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] axi_w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] axi_b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] axi_ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] axi_r_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_w_user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_r_user_t) `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_w_user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_r_user_t) `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv index fc36a217f..b6a238eeb 100644 --- a/src/axi_id_serialize.sv +++ b/src/axi_id_serialize.sv @@ -37,17 +37,27 @@ module axi_id_serialize #( /// are counted separately (except for ATOPs, which count as both read and write). /// /// The maximum value of this parameter is `2**AxiMstPortIdWidth`. - parameter int unsigned AxiMstPortMaxUniqIds = 32'd0, + parameter int unsigned AxiMstPortMaxUniqIds = 32'd0, /// Maximum number of in-flight transactions with the same ID at the master port. parameter int unsigned AxiMstPortMaxTxnsPerId = 32'd0, /// Address width of both AXI4+ATOP ports - parameter int unsigned AxiAddrWidth = 32'd0, + parameter int unsigned AxiAddrWidth = 32'd0, /// Data width of both AXI4+ATOP ports - parameter int unsigned AxiDataWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, /// User width of both AXI4+ATOP ports - parameter int unsigned AxiUserWidth = 32'd0, + parameter int unsigned AxiUserWidth = 32'd0, + /// AXI AW user signal width + parameter int unsigned AxiAwUserWidth = AxiUserWidth, + /// AXI W user signal width + parameter int unsigned AxiWUserWidth = AxiUserWidth, + /// AXI B user signal width + parameter int unsigned AxiBUserWidth = AxiUserWidth, + /// AXI AR user signal width + parameter int unsigned AxiArUserWidth = AxiUserWidth, + /// AXI R user signal width + parameter int unsigned AxiRUserWidth = AxiUserWidth, /// Enable support for AXI4+ATOP atomics - parameter bit AtopSupport = 1'b1, + parameter bit AtopSupport = 1'b1, /// Request struct type of the AXI4+ATOP slave port parameter type slv_req_t = logic, /// Response struct type of the AXI4+ATOP slave port @@ -104,54 +114,58 @@ module axi_id_serialize #( /// Strobe in any AXI channel typedef logic [AxiDataWidth/8-1:0] strb_t; /// User signal in any AXI channel - typedef logic [AxiUserWidth-1:0] user_t; + typedef logic [AxiAwUserWidth-1:0] aw_user_t; + typedef logic [AxiWUserWidth-1:0] w_user_t; + typedef logic [AxiBUserWidth-1:0] b_user_t; + typedef logic [AxiArUserWidth-1:0] ar_user_t; + typedef logic [AxiRUserWidth-1:0] r_user_t; /// W channel at any interface - `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, w_user_t) /// AW channel at slave port - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, aw_user_t) /// B channel at slave port - `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, b_user_t) /// AR channel at slave port - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, ar_user_t) /// R channel at slave port - `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, r_user_t) /// AW channel after serializer - `AXI_TYPEDEF_AW_CHAN_T(ser_aw_t, addr_t, ser_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(ser_aw_t, addr_t, ser_id_t, aw_user_t) /// B channel after serializer - `AXI_TYPEDEF_B_CHAN_T(ser_b_t, ser_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(ser_b_t, ser_id_t, b_user_t) /// AR channel after serializer - `AXI_TYPEDEF_AR_CHAN_T(ser_ar_t, addr_t, ser_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ser_ar_t, addr_t, ser_id_t, ar_user_t) /// R channel after serializer - `AXI_TYPEDEF_R_CHAN_T(ser_r_t, data_t, ser_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(ser_r_t, data_t, ser_id_t, r_user_t) /// AXI Requests from serializer `AXI_TYPEDEF_REQ_T(ser_req_t, ser_aw_t, w_t, ser_ar_t) /// AXI responses to serializer `AXI_TYPEDEF_RESP_T(ser_resp_t, ser_b_t, ser_r_t) /// AW channel after the multiplexer - `AXI_TYPEDEF_AW_CHAN_T(mux_aw_t, addr_t, mux_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mux_aw_t, addr_t, mux_id_t, aw_user_t) /// B channel after the multiplexer - `AXI_TYPEDEF_B_CHAN_T(mux_b_t, mux_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mux_b_t, mux_id_t, b_user_t) /// AR channel after the multiplexer - `AXI_TYPEDEF_AR_CHAN_T(mux_ar_t, addr_t, mux_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mux_ar_t, addr_t, mux_id_t, ar_user_t) /// R channel after the multiplexer - `AXI_TYPEDEF_R_CHAN_T(mux_r_t, data_t, mux_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mux_r_t, data_t, mux_id_t, r_user_t) /// AXI requests from the multiplexer `AXI_TYPEDEF_REQ_T(mux_req_t, mux_aw_t, w_t, mux_ar_t) /// AXI responses to the multiplexer `AXI_TYPEDEF_RESP_T(mux_resp_t, mux_b_t, mux_r_t) /// AW channel at master port - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, aw_user_t) /// B channel at master port - `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, b_user_t) /// AR channel at master port - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, ar_user_t) /// R channel at master port - `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, r_user_t) /// Type for slave ID map typedef mst_id_t [2**AxiSlvPortIdWidth-1:0] slv_id_map_t; @@ -374,7 +388,17 @@ module axi_id_serialize_intf #( parameter int unsigned AXI_MST_PORT_MAX_TXNS_PER_ID = 32'd0, parameter int unsigned AXI_ADDR_WIDTH = 32'd0, parameter int unsigned AXI_DATA_WIDTH = 32'd0, - parameter int unsigned AXI_USER_WIDTH = 32'd0 + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH ) ( input logic clk_i, input logic rst_ni, @@ -387,20 +411,24 @@ module axi_id_serialize_intf #( typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; typedef logic [AXI_DATA_WIDTH-1:0] data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, r_user_t) `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_t, w_t, slv_ar_t) `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_t, slv_r_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, aw_user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, r_user_t) `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_t, w_t, mst_ar_t) `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_t, mst_r_t) diff --git a/src/axi_intf.sv b/src/axi_intf.sv index c0257f21c..2a1b2802c 100644 --- a/src/axi_intf.sv +++ b/src/axi_intf.sv @@ -18,19 +18,28 @@ /// An AXI4 interface. interface AXI_BUS #( - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_ID_WIDTH = 0, - parameter int unsigned AXI_USER_WIDTH = 0 + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH ); localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_STRB_WIDTH-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; id_t aw_id; addr_t aw_addr; @@ -43,20 +52,20 @@ interface AXI_BUS #( axi_pkg::qos_t aw_qos; axi_pkg::region_t aw_region; axi_pkg::atop_t aw_atop; - user_t aw_user; + aw_user_t aw_user; logic aw_valid; logic aw_ready; data_t w_data; strb_t w_strb; logic w_last; - user_t w_user; + w_user_t w_user; logic w_valid; logic w_ready; id_t b_id; axi_pkg::resp_t b_resp; - user_t b_user; + b_user_t b_user; logic b_valid; logic b_ready; @@ -70,7 +79,7 @@ interface AXI_BUS #( axi_pkg::prot_t ar_prot; axi_pkg::qos_t ar_qos; axi_pkg::region_t ar_region; - user_t ar_user; + ar_user_t ar_user; logic ar_valid; logic ar_ready; @@ -78,7 +87,7 @@ interface AXI_BUS #( data_t r_data; axi_pkg::resp_t r_resp; logic r_last; - user_t r_user; + r_user_t r_user; logic r_valid; logic r_ready; @@ -114,18 +123,27 @@ interface AXI_BUS_DV #( parameter int unsigned AXI_ADDR_WIDTH = 0, parameter int unsigned AXI_DATA_WIDTH = 0, parameter int unsigned AXI_ID_WIDTH = 0, - parameter int unsigned AXI_USER_WIDTH = 0 + parameter int unsigned AXI_USER_WIDTH = 0, + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH )( input logic clk_i ); localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_STRB_WIDTH-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; id_t aw_id; addr_t aw_addr; @@ -138,20 +156,20 @@ interface AXI_BUS_DV #( axi_pkg::qos_t aw_qos; axi_pkg::region_t aw_region; axi_pkg::atop_t aw_atop; - user_t aw_user; + aw_user_t aw_user; logic aw_valid; logic aw_ready; data_t w_data; strb_t w_strb; logic w_last; - user_t w_user; + w_user_t w_user; logic w_valid; logic w_ready; id_t b_id; axi_pkg::resp_t b_resp; - user_t b_user; + b_user_t b_user; logic b_valid; logic b_ready; @@ -165,7 +183,7 @@ interface AXI_BUS_DV #( axi_pkg::prot_t ar_prot; axi_pkg::qos_t ar_qos; axi_pkg::region_t ar_region; - user_t ar_user; + ar_user_t ar_user; logic ar_valid; logic ar_ready; @@ -173,7 +191,7 @@ interface AXI_BUS_DV #( data_t r_data; axi_pkg::resp_t r_resp; logic r_last; - user_t r_user; + r_user_t r_user; logic r_valid; logic r_ready; @@ -258,21 +276,30 @@ endinterface /// An asynchronous AXI4 interface. interface AXI_BUS_ASYNC #( - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_ID_WIDTH = 0, - parameter int unsigned AXI_USER_WIDTH = 0, - parameter int unsigned BUFFER_WIDTH = 0 + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + parameter int unsigned BUFFER_WIDTH = 32'd0, + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH ); localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_STRB_WIDTH-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - typedef logic [BUFFER_WIDTH-1:0] buffer_t; + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + typedef logic [BUFFER_WIDTH-1:0] buffer_t; id_t aw_id; addr_t aw_addr; @@ -285,20 +312,20 @@ interface AXI_BUS_ASYNC axi_pkg::qos_t aw_qos; axi_pkg::region_t aw_region; axi_pkg::atop_t aw_atop; - user_t aw_user; + aw_user_t aw_user; buffer_t aw_writetoken; buffer_t aw_readpointer; data_t w_data; strb_t w_strb; logic w_last; - user_t w_user; + w_user_t w_user; buffer_t w_writetoken; buffer_t w_readpointer; id_t b_id; axi_pkg::resp_t b_resp; - user_t b_user; + b_user_t b_user; buffer_t b_writetoken; buffer_t b_readpointer; @@ -312,7 +339,7 @@ interface AXI_BUS_ASYNC axi_pkg::prot_t ar_prot; axi_pkg::qos_t ar_qos; axi_pkg::region_t ar_region; - user_t ar_user; + ar_user_t ar_user; buffer_t ar_writetoken; buffer_t ar_readpointer; @@ -320,7 +347,7 @@ interface AXI_BUS_ASYNC data_t r_data; axi_pkg::resp_t r_resp; logic r_last; - user_t r_user; + r_user_t r_user; buffer_t r_writetoken; buffer_t r_readpointer; @@ -347,26 +374,35 @@ endinterface /// An asynchronous AXI4 interface for Gray CDCs. interface AXI_BUS_ASYNC_GRAY #( - parameter int unsigned AXI_ADDR_WIDTH = 0, - parameter int unsigned AXI_DATA_WIDTH = 0, - parameter int unsigned AXI_ID_WIDTH = 0, - parameter int unsigned AXI_USER_WIDTH = 0, - parameter int unsigned LOG_DEPTH = 0 + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + parameter int unsigned LOG_DEPTH = 32'd0, + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH ); localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_STRB_WIDTH-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) aw_chan_t [2**LOG_DEPTH-1:0] aw_data; w_chan_t [2**LOG_DEPTH-1:0] w_data; diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv index 6385b2633..9cfa2e424 100644 --- a/src/axi_isolate.sv +++ b/src/axi_isolate.sv @@ -39,24 +39,34 @@ /// module is de-isolated again. module axi_isolate #( /// Maximum number of pending requests per channel - parameter int unsigned NumPending = 32'd16, + parameter int unsigned NumPending = 32'd16, /// Gracefully terminate all incoming transactions in case of isolation by returning proper error /// responses. - parameter bit TerminateTransaction = 1'b0, + parameter bit TerminateTransaction = 1'b0, /// Support atomic operations (ATOPs) - parameter bit AtopSupport = 1'b1, + parameter bit AtopSupport = 1'b1, /// Address width of all AXI4+ATOP ports - parameter int signed AxiAddrWidth = 32'd0, + parameter int unsigned AxiAddrWidth = 32'd0, /// Data width of all AXI4+ATOP ports - parameter int signed AxiDataWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, /// ID width of all AXI4+ATOP ports - parameter int signed AxiIdWidth = 32'd0, + parameter int unsigned AxiIdWidth = 32'd0, /// User signal width of all AXI4+ATOP ports - parameter int signed AxiUserWidth = 32'd0, + parameter int unsigned AxiUserWidth = 32'd0, + /// AXI AW user signal width + parameter int unsigned AxiAwUserWidth = AxiUserWidth, + /// AXI W user signal width + parameter int unsigned AxiWUserWidth = AxiUserWidth, + /// AXI B user signal width + parameter int unsigned AxiBUserWidth = AxiUserWidth, + /// AXI AR user signal width + parameter int unsigned AxiArUserWidth = AxiUserWidth, + /// AXI R user signal width + parameter int unsigned AxiRUserWidth = AxiUserWidth, /// Request struct type of all AXI4+ATOP ports - parameter type axi_req_t = logic, + parameter type axi_req_t = logic, /// Response struct type of all AXI4+ATOP ports - parameter type axi_resp_t = logic + parameter type axi_resp_t = logic ) ( /// Rising-edge clock of all ports input logic clk_i, @@ -80,13 +90,17 @@ module axi_isolate #( typedef logic [AxiAddrWidth-1:0] addr_t; typedef logic [AxiDataWidth-1:0] data_t; typedef logic [AxiDataWidth/8-1:0] strb_t; - typedef logic [AxiUserWidth-1:0] user_t; - - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + typedef logic [AxiAwUserWidth-1:0] aw_user_t; + typedef logic [AxiWUserWidth-1:0] w_user_t; + typedef logic [AxiBUserWidth-1:0] b_user_t; + typedef logic [AxiArUserWidth-1:0] ar_user_t; + typedef logic [AxiRUserWidth-1:0] r_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) axi_req_t [1:0] demux_req; axi_resp_t [1:0] demux_rsp; @@ -412,13 +426,23 @@ endmodule /// /// See the documentation of the main module for the definition of ports and parameters. module axi_isolate_intf #( - parameter int unsigned NUM_PENDING = 32'd16, - parameter bit TERMINATE_TRANSACTION = 1'b0, - parameter bit ATOP_SUPPORT = 1'b1, - parameter int unsigned AXI_ID_WIDTH = 32'd0, - parameter int unsigned AXI_ADDR_WIDTH = 32'd0, - parameter int unsigned AXI_DATA_WIDTH = 32'd0, - parameter int unsigned AXI_USER_WIDTH = 32'd0 + parameter int unsigned NUM_PENDING = 32'd16, + parameter bit TERMINATE_TRANSACTION = 1'b0, + parameter bit ATOP_SUPPORT = 1'b1, + parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH ) ( input logic clk_i, input logic rst_ni, @@ -427,18 +451,22 @@ module axi_isolate_intf #( input logic isolate_i, output logic isolated_o ); - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) @@ -459,7 +487,11 @@ module axi_isolate_intf #( .AxiAddrWidth ( AXI_ADDR_WIDTH ), .AxiDataWidth ( AXI_DATA_WIDTH ), .AxiIdWidth ( AXI_ID_WIDTH ), - .AxiUserWidth ( AXI_USER_WIDTH ), + .AxiAwUserWidth ( AXI_AW_USER_WIDTH ), + .AxiWUserWidth ( AXI_W_USER_WIDTH ), + .AxiBUserWidth ( AXI_B_USER_WIDTH ), + .AxiArUserWidth ( AXI_AR_USER_WIDTH ), + .AxiRUserWidth ( AXI_R_USER_WIDTH ), .axi_req_t ( axi_req_t ), .axi_resp_t ( axi_resp_t ) ) i_axi_isolate ( @@ -476,10 +508,14 @@ module axi_isolate_intf #( // pragma translate_off `ifndef VERILATOR initial begin - assume (AXI_ID_WIDTH > 0) else $fatal(1, "AXI_ID_WIDTH has to be > 0."); - assume (AXI_ADDR_WIDTH > 0) else $fatal(1, "AXI_ADDR_WIDTH has to be > 0."); - assume (AXI_DATA_WIDTH > 0) else $fatal(1, "AXI_DATA_WIDTH has to be > 0."); - assume (AXI_USER_WIDTH > 0) else $fatal(1, "AXI_USER_WIDTH has to be > 0."); + assume (AXI_ID_WIDTH > 0) else $fatal(1, "AXI_ID_WIDTH has to be > 0."); + assume (AXI_ADDR_WIDTH > 0) else $fatal(1, "AXI_ADDR_WIDTH has to be > 0."); + assume (AXI_DATA_WIDTH > 0) else $fatal(1, "AXI_DATA_WIDTH has to be > 0."); + assume (AXI_AW_USER_WIDTH > 0) else $fatal(1, "AXI_AW_USER_WIDTH has to be > 0."); + assume (AXI_W_USER_WIDTH > 0) else $fatal(1, "AXI_W_USER_WIDTH has to be > 0."); + assume (AXI_B_USER_WIDTH > 0) else $fatal(1, "AXI_B_USER_WIDTH has to be > 0."); + assume (AXI_AR_USER_WIDTH > 0) else $fatal(1, "AXI_AR_USER_WIDTH has to be > 0."); + assume (AXI_R_USER_WIDTH > 0) else $fatal(1, "AXI_R_USER_WIDTH has to be > 0."); end `endif // pragma translate_on diff --git a/src/axi_iw_converter.sv b/src/axi_iw_converter.sv index f29425eb1..c480b4695 100644 --- a/src/axi_iw_converter.sv +++ b/src/axi_iw_converter.sv @@ -85,6 +85,16 @@ module axi_iw_converter #( parameter int unsigned AxiDataWidth = 32'd0, /// User signal width of both AXI4+ATOP ports parameter int unsigned AxiUserWidth = 32'd0, + /// AXI AW user signal width + parameter int unsigned AxiAwUserWidth = AxiUserWidth, + /// AXI W user signal width + parameter int unsigned AxiWUserWidth = AxiUserWidth, + /// AXI B user signal width + parameter int unsigned AxiBUserWidth = AxiUserWidth, + /// AXI AR user signal width + parameter int unsigned AxiArUserWidth = AxiUserWidth, + /// AXI R user signal width + parameter int unsigned AxiRUserWidth = AxiUserWidth, /// Request struct type of the AXI4+ATOP slave port parameter type slv_req_t = logic, /// Response struct type of the AXI4+ATOP slave port @@ -113,16 +123,20 @@ module axi_iw_converter #( typedef logic [AxiSlvPortIdWidth-1:0] slv_id_t; typedef logic [AxiMstPortIdWidth-1:0] mst_id_t; typedef logic [AxiDataWidth/8-1:0] strb_t; - typedef logic [AxiUserWidth-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, user_t) + typedef logic [AxiAwUserWidth-1:0] aw_user_t; + typedef logic [AxiWUserWidth-1:0] w_user_t; + typedef logic [AxiBUserWidth-1:0] b_user_t; + typedef logic [AxiArUserWidth-1:0] ar_user_t; + typedef logic [AxiRUserWidth-1:0] r_user_t; + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, aw_user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_t, addr_t, mst_id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, b_user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_t, mst_id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, ar_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_t, addr_t, mst_id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, r_user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, r_user_t) if (AxiMstPortIdWidth < AxiSlvPortIdWidth) begin : gen_downsize if (AxiSlvPortMaxUniqIds <= 2**AxiMstPortIdWidth) begin : gen_remap @@ -152,7 +166,11 @@ module axi_iw_converter #( .AxiMstPortMaxTxnsPerId ( AxiMstPortMaxTxnsPerId ), .AxiAddrWidth ( AxiAddrWidth ), .AxiDataWidth ( AxiDataWidth ), - .AxiUserWidth ( AxiUserWidth ), + .AxiAwUserWidth ( AxiAwUserWidth ), + .AxiWUserWidth ( AxiWUserWidth ), + .AxiBUserWidth ( AxiBUserWidth ), + .AxiArUserWidth ( AxiArUserWidth ), + .AxiRUserWidth ( AxiRUserWidth ), .slv_req_t ( slv_req_t ), .slv_resp_t ( slv_resp_t ), .mst_req_t ( mst_req_t ), @@ -222,12 +240,20 @@ module axi_iw_converter #( // pragma translate_off `ifndef VERILATOR initial begin : p_assert - assert(AxiAddrWidth > 32'd0) + assert(AxiAwUserWidth > 32'd0) else $fatal(1, "Parameter AxiAddrWidth has to be larger than 0!"); assert(AxiDataWidth > 32'd0) else $fatal(1, "Parameter AxiDataWidth has to be larger than 0!"); - assert(AxiUserWidth > 32'd0) - else $fatal(1, "Parameter AxiUserWidth has to be larger than 0!"); + assert(AxiAwUserWidth > 32'd0) + else $fatal(1, "Parameter AxiAwUserWidth has to be larger than 0!"); + assert(AxiWUserWidth > 32'd0) + else $fatal(1, "Parameter AxiWUserWidth has to be larger than 0!"); + assert(AxiBUserWidth > 32'd0) + else $fatal(1, "Parameter AxiBUserWidth has to be larger than 0!"); + assert(AxiArUserWidth > 32'd0) + else $fatal(1, "Parameter AxiArUserWidth has to be larger than 0!"); + assert(AxiRUserWidth > 32'd0) + else $fatal(1, "Parameter AxiRUserWidth has to be larger than 0!"); assert(AxiSlvPortIdWidth > 32'd0) else $fatal(1, "Parameter AxiSlvPortIdWidth has to be larger than 0!"); assert(AxiMstPortIdWidth > 32'd0) @@ -270,7 +296,17 @@ module axi_iw_converter_intf #( parameter int unsigned AXI_MST_PORT_MAX_TXNS_PER_ID = 32'd0, parameter int unsigned AXI_ADDR_WIDTH = 32'd0, parameter int unsigned AXI_DATA_WIDTH = 32'd0, - parameter int unsigned AXI_USER_WIDTH = 32'd0 + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH ) ( input logic clk_i, input logic rst_ni, @@ -282,21 +318,25 @@ module axi_iw_converter_intf #( typedef logic [AXI_ADDR_WIDTH-1:0] axi_addr_t; typedef logic [AXI_DATA_WIDTH-1:0] axi_data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] axi_strb_t; - typedef logic [AXI_USER_WIDTH-1:0] axi_user_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] axi_aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] axi_w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] axi_b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] axi_ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] axi_r_user_t; - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_w_user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_r_user_t) `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_w_user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_r_user_t) `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) @@ -320,7 +360,11 @@ module axi_iw_converter_intf #( .AxiMstPortMaxTxnsPerId ( AXI_MST_PORT_MAX_TXNS_PER_ID ), .AxiAddrWidth ( AXI_ADDR_WIDTH ), .AxiDataWidth ( AXI_DATA_WIDTH ), - .AxiUserWidth ( AXI_USER_WIDTH ), + .AxiAwUserWidth ( AXI_AW_USER_WIDTH ), + .AxiWUserWidth ( AXI_W_USER_WIDTH ), + .AxiBUserWidth ( AXI_B_USER_WIDTH ), + .AxiArUserWidth ( AXI_AR_USER_WIDTH ), + .AxiRUserWidth ( AXI_R_USER_WIDTH ), .slv_req_t ( slv_req_t ), .slv_resp_t ( slv_resp_t ), .mst_req_t ( mst_req_t ), @@ -336,14 +380,22 @@ module axi_iw_converter_intf #( // pragma translate_off `ifndef VERILATOR initial begin - assert (slv.AXI_ID_WIDTH == AXI_SLV_PORT_ID_WIDTH); - assert (slv.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); - assert (slv.AXI_DATA_WIDTH == AXI_DATA_WIDTH); - assert (slv.AXI_USER_WIDTH == AXI_USER_WIDTH); - assert (mst.AXI_ID_WIDTH == AXI_MST_PORT_ID_WIDTH); - assert (mst.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); - assert (mst.AXI_DATA_WIDTH == AXI_DATA_WIDTH); - assert (mst.AXI_USER_WIDTH == AXI_USER_WIDTH); + assert (slv.AXI_ID_WIDTH == AXI_SLV_PORT_ID_WIDTH); + assert (slv.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (slv.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (slv.AXI_AW_USER_WIDTH == AXI_AW_USER_WIDTH); + assert (slv.AXI_W_USER_WIDTH == AXI_W_USER_WIDTH); + assert (slv.AXI_B_USER_WIDTH == AXI_B_USER_WIDTH); + assert (slv.AXI_AR_USER_WIDTH == AXI_AR_USER_WIDTH); + assert (slv.AXI_R_USER_WIDTH == AXI_R_USER_WIDTH); + assert (mst.AXI_ID_WIDTH == AXI_MST_PORT_ID_WIDTH); + assert (mst.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (mst.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (mst.AXI_AW_USER_WIDTH == AXI_AW_USER_WIDTH); + assert (mst.AXI_W_USER_WIDTH == AXI_W_USER_WIDTH); + assert (mst.AXI_B_USER_WIDTH == AXI_B_USER_WIDTH); + assert (mst.AXI_AR_USER_WIDTH == AXI_AR_USER_WIDTH); + assert (mst.AXI_R_USER_WIDTH == AXI_R_USER_WIDTH); end `endif // pragma translate_on diff --git a/src/axi_lfsr.sv b/src/axi_lfsr.sv index 2085a76fe..57a8cf732 100644 --- a/src/axi_lfsr.sv +++ b/src/axi_lfsr.sv @@ -17,17 +17,27 @@ /// set the internal state. module axi_lfsr #( /// AXI4 Data Width - parameter int unsigned DataWidth = 32'd0, + parameter int unsigned DataWidth = 32'd0, /// AXI4 Addr Width - parameter int unsigned AddrWidth = 32'd0, + parameter int unsigned AddrWidth = 32'd0, /// AXI4 Id Width - parameter int unsigned IdWidth = 32'd0, + parameter int unsigned IdWidth = 32'd0, /// AXI4 User Width - parameter int unsigned UserWidth = 32'd0, + parameter int unsigned UserWidth = 32'd0, + /// AXI AW user signal width + parameter int unsigned AwUserWidth = UserWidth, + /// AXI W user signal width + parameter int unsigned WUserWidth = UserWidth, + /// AXI B user signal width + parameter int unsigned BUserWidth = UserWidth, + /// AXI AR user signal width + parameter int unsigned ArUserWidth = UserWidth, + /// AXI R user signal width + parameter int unsigned RUserWidth = UserWidth, /// AXI4 request struct definition - parameter type axi_req_t = logic, + parameter type axi_req_t = logic, /// AXI4 response struct definition - parameter type axi_rsp_t = logic + parameter type axi_rsp_t = logic )( /// Rising-edge clock input logic clk_i, @@ -82,7 +92,11 @@ module axi_lfsr #( .AxiAddrWidth ( AddrWidth ), .AxiDataWidth ( DataWidth ), .AxiIdWidth ( IdWidth ), - .AxiUserWidth ( UserWidth ), + .AxiAwUserWidth ( AwUserWidth ), + .AxiWUserWidth ( WUserWidth ), + .AxiBUserWidth ( BUserWidth ), + .AxiArUserWidth ( ArUserWidth ), + .AxiRUserWidth ( RUserWidth ), .AxiMaxWriteTxns ( 'd2 ), // We only have 1 cycle latency; 2 is enough .AxiMaxReadTxns ( 'd2 ), // We only have 1 cycle latency; 2 is enough .FallThrough ( 1'b0 ), diff --git a/src/axi_modify_address.sv b/src/axi_modify_address.sv index 2a9b96229..76cf27f9c 100644 --- a/src/axi_modify_address.sv +++ b/src/axi_modify_address.sv @@ -97,6 +97,16 @@ module axi_modify_address_intf #( parameter int unsigned AXI_ID_WIDTH = 0, /// User signal width of slave and master port parameter int unsigned AXI_USER_WIDTH = 0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH, /// Derived (=DO NOT OVERRIDE) type of master port addresses type mst_addr_t = logic [AXI_MST_PORT_ADDR_WIDTH-1:0] ) ( @@ -114,15 +124,19 @@ module axi_modify_address_intf #( typedef logic [AXI_SLV_PORT_ADDR_WIDTH-1:0] slv_addr_t; typedef logic [AXI_DATA_WIDTH-1:0] data_t; typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, slv_addr_t, id_t, user_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, mst_addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, slv_addr_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, mst_addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, slv_addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, mst_addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, slv_addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, mst_addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) diff --git a/src/axi_multicut.sv b/src/axi_multicut.sv index 64a354a4c..cc36c96d3 100644 --- a/src/axi_multicut.sv +++ b/src/axi_multicut.sv @@ -94,11 +94,21 @@ endmodule // interface wrapper module axi_multicut_intf #( - parameter int unsigned ADDR_WIDTH = 0, // The address width. - parameter int unsigned DATA_WIDTH = 0, // The data width. - parameter int unsigned ID_WIDTH = 0, // The ID width. - parameter int unsigned USER_WIDTH = 0, // The user data width. - parameter int unsigned NUM_CUTS = 0 // The number of cuts. + parameter int unsigned ADDR_WIDTH = 0, // The address width. + parameter int unsigned DATA_WIDTH = 0, // The data width. + parameter int unsigned ID_WIDTH = 0, // The ID width. + parameter int unsigned USER_WIDTH = 0, // The user data width. + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = USER_WIDTH + parameter int unsigned NUM_CUTS = 0 // The number of cuts. ) ( input logic clk_i, input logic rst_ni, @@ -106,17 +116,21 @@ module axi_multicut_intf #( AXI_BUS.Master out ); - typedef logic [ID_WIDTH-1:0] id_t; - typedef logic [ADDR_WIDTH-1:0] addr_t; - typedef logic [DATA_WIDTH-1:0] data_t; - typedef logic [DATA_WIDTH/8-1:0] strb_t; - typedef logic [USER_WIDTH-1:0] user_t; - - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + typedef logic [ID_WIDTH-1:0] id_t; + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) @@ -151,10 +165,14 @@ module axi_multicut_intf #( // pragma translate_off `ifndef VERILATOR initial begin - assert (ADDR_WIDTH > 0) else $fatal(1, "Wrong addr width parameter"); - assert (DATA_WIDTH > 0) else $fatal(1, "Wrong data width parameter"); - assert (ID_WIDTH > 0) else $fatal(1, "Wrong id width parameter"); - assert (USER_WIDTH > 0) else $fatal(1, "Wrong user width parameter"); + assert (ADDR_WIDTH > 0) else $fatal(1, "Wrong addr width parameter"); + assert (DATA_WIDTH > 0) else $fatal(1, "Wrong data width parameter"); + assert (ID_WIDTH > 0) else $fatal(1, "Wrong id width parameter"); + assert (AXI_AW_USER_WIDTH > 0) else $fatal(1, "Wrong user width parameter"); + assert (AXI_W_USER_WIDTH > 0) else $fatal(1, "Wrong user width parameter"); + assert (AXI_B_USER_WIDTH > 0) else $fatal(1, "Wrong user width parameter"); + assert (AXI_AR_USER_WIDTH > 0) else $fatal(1, "Wrong user width parameter"); + assert (AXI_R_USER_WIDTH > 0) else $fatal(1, "Wrong user width parameter"); assert (in.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); assert (in.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); assert (in.AXI_ID_WIDTH == ID_WIDTH) else $fatal(1, "Wrong interface definition"); diff --git a/src/axi_mux.sv b/src/axi_mux.sv index da17e2b8c..ada9a58f9 100644 --- a/src/axi_mux.sv +++ b/src/axi_mux.sv @@ -498,23 +498,33 @@ endmodule `include "axi/assign.svh" `include "axi/typedef.svh" module axi_mux_intf #( - parameter int unsigned SLV_AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params - parameter int unsigned MST_AXI_ID_WIDTH = 32'd0, - parameter int unsigned AXI_ADDR_WIDTH = 32'd0, - parameter int unsigned AXI_DATA_WIDTH = 32'd0, - parameter int unsigned AXI_USER_WIDTH = 32'd0, - parameter int unsigned NO_SLV_PORTS = 32'd0, // Number of slave ports + parameter int unsigned SLV_AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params + parameter int unsigned MST_AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH + parameter int unsigned NO_SLV_PORTS = 32'd0, // Number of slave ports // Maximum number of outstanding transactions per write - parameter int unsigned MAX_W_TRANS = 32'd8, + parameter int unsigned MAX_W_TRANS = 32'd8, // if enabled, this multiplexer is purely combinatorial - parameter bit FALL_THROUGH = 1'b0, + parameter bit FALL_THROUGH = 1'b0, // add spill register on write master ports, adds a cycle latency on write channels - parameter bit SPILL_AW = 1'b1, - parameter bit SPILL_W = 1'b0, - parameter bit SPILL_B = 1'b0, + parameter bit SPILL_AW = 1'b1, + parameter bit SPILL_W = 1'b0, + parameter bit SPILL_B = 1'b0, // add spill register on read master ports, adds a cycle latency on read channels - parameter bit SPILL_AR = 1'b1, - parameter bit SPILL_R = 1'b0 + parameter bit SPILL_AR = 1'b1, + parameter bit SPILL_R = 1'b0 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -523,26 +533,30 @@ module axi_mux_intf #( AXI_BUS.Master mst // master port ); - typedef logic [SLV_AXI_ID_WIDTH-1:0] slv_id_t; - typedef logic [MST_AXI_ID_WIDTH-1:0] mst_id_t; - typedef logic [AXI_ADDR_WIDTH -1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [SLV_AXI_ID_WIDTH-1:0] slv_id_t; + typedef logic [MST_AXI_ID_WIDTH-1:0] mst_id_t; + typedef logic [AXI_ADDR_WIDTH -1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; // channels typedef - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, aw_user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, aw_user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, b_user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, b_user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, ar_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, ar_user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, r_user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, r_user_t) `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) diff --git a/src/axi_serializer.sv b/src/axi_serializer.sv index 0b064f29e..46537b62e 100644 --- a/src/axi_serializer.sv +++ b/src/axi_serializer.sv @@ -222,17 +222,27 @@ endmodule /// Serialize all AXI transactions to a single ID (zero), interface version. module axi_serializer_intf #( /// AXI4+ATOP ID width. - parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, /// AXI4+ATOP address width. - parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, /// AXI4+ATOP data width. - parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, /// AXI4+ATOP user width. - parameter int unsigned AXI_USER_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH /// Maximum number of in flight read transactions. - parameter int unsigned MAX_READ_TXNS = 32'd0, + parameter int unsigned MAX_READ_TXNS = 32'd0, /// Maximum number of in flight write transactions. - parameter int unsigned MAX_WRITE_TXNS = 32'd0 + parameter int unsigned MAX_WRITE_TXNS = 32'd0 ) ( /// Clock input logic clk_i, @@ -244,16 +254,20 @@ module axi_serializer_intf #( AXI_BUS.Master mst ); - typedef logic [AXI_ID_WIDTH -1:0] id_t; - typedef logic [AXI_ADDR_WIDTH -1:0] addr_t; - typedef logic [AXI_DATA_WIDTH -1:0] data_t; - typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; - typedef logic [AXI_USER_WIDTH -1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + typedef logic [AXI_ID_WIDTH -1:0] id_t; + typedef logic [AXI_ADDR_WIDTH -1:0] addr_t; + typedef logic [AXI_DATA_WIDTH -1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t; + typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t; + typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t; + typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t; + typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) axi_req_t slv_req, mst_req; @@ -281,13 +295,17 @@ module axi_serializer_intf #( // pragma translate_off `ifndef VERILATOR initial begin: p_assertions - assert (AXI_ADDR_WIDTH >= 1) else $fatal(1, "AXI address width must be at least 1!"); - assert (AXI_DATA_WIDTH >= 1) else $fatal(1, "AXI data width must be at least 1!"); - assert (AXI_ID_WIDTH >= 1) else $fatal(1, "AXI ID width must be at least 1!"); - assert (AXI_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!"); - assert (MAX_READ_TXNS >= 1) + assert (AXI_ADDR_WIDTH >= 1) else $fatal(1, "AXI address width must be at least 1!"); + assert (AXI_DATA_WIDTH >= 1) else $fatal(1, "AXI data width must be at least 1!"); + assert (AXI_ID_WIDTH >= 1) else $fatal(1, "AXI ID width must be at least 1!"); + assert (AXI_AW_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!"); + assert (AXI_W_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!"); + assert (AXI_B_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!"); + assert (AXI_AR_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!"); + assert (AXI_R_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!"); + assert (MAX_READ_TXNS >= 1) else $fatal(1, "Maximum number of read transactions must be >= 1!"); - assert (MAX_WRITE_TXNS >= 1) + assert (MAX_WRITE_TXNS >= 1) else $fatal(1, "Maximum number of write transactions must be >= 1!"); end `endif diff --git a/src/axi_sim_mem.sv b/src/axi_sim_mem.sv index b8b6b12c0..1af3772c6 100644 --- a/src/axi_sim_mem.sv +++ b/src/axi_sim_mem.sv @@ -33,6 +33,16 @@ module axi_sim_mem #( parameter int unsigned IdWidth = 32'd0, /// AXI User Width. parameter int unsigned UserWidth = 32'd0, + /// AXI AW user signal width + parameter int unsigned AwUserWidth = UserWidth, + /// AXI W user signal width + parameter int unsigned WUserWidth = UserWidth, + /// AXI B user signal width + parameter int unsigned BUserWidth = UserWidth, + /// AXI AR user signal width + parameter int unsigned ArUserWidth = UserWidth, + /// AXI R user signal width + parameter int unsigned RUserWidth = UserWidth, /// AXI4 request struct definition parameter type axi_req_t = logic, /// AXI4 response struct definition @@ -57,48 +67,52 @@ module axi_sim_mem #( /// Memory monitor write valid. All `mon_w_*` outputs are only valid if this signal is high. /// A write to the memory is visible on the `mon_w_*` outputs in the clock cycle after it has /// happened. - output logic mon_w_valid_o, + output logic mon_w_valid_o, /// Memory monitor write address - output logic [AddrWidth-1:0] mon_w_addr_o, + output logic [AddrWidth-1:0] mon_w_addr_o, /// Memory monitor write data - output logic [DataWidth-1:0] mon_w_data_o, + output logic [DataWidth-1:0] mon_w_data_o, /// Memory monitor write ID - output logic [IdWidth-1:0] mon_w_id_o, + output logic [IdWidth-1:0] mon_w_id_o, /// Memory monitor write user - output logic [UserWidth-1:0] mon_w_user_o, + output logic [WUserWidth-1:0] mon_w_user_o, /// Memory monitor write beat count - output axi_pkg::len_t mon_w_beat_count_o, + output axi_pkg::len_t mon_w_beat_count_o, /// Memory monitor write last - output logic mon_w_last_o, + output logic mon_w_last_o, /// Memory monitor read valid. All `mon_r_*` outputs are only valid if this signal is high. /// A read from the memory is visible on the `mon_w_*` outputs in the clock cycle after it has /// happened. - output logic mon_r_valid_o, + output logic mon_r_valid_o, /// Memory monitor read address - output logic [AddrWidth-1:0] mon_r_addr_o, + output logic [AddrWidth-1:0] mon_r_addr_o, /// Memory monitor read data - output logic [DataWidth-1:0] mon_r_data_o, + output logic [DataWidth-1:0] mon_r_data_o, /// Memory monitor read ID - output logic [IdWidth-1:0] mon_r_id_o, + output logic [IdWidth-1:0] mon_r_id_o, /// Memory monitor read user - output logic [UserWidth-1:0] mon_r_user_o, + output logic [RUserWidth-1:0] mon_r_user_o, /// Memory monitor read beat count - output axi_pkg::len_t mon_r_beat_count_o, + output axi_pkg::len_t mon_r_beat_count_o, /// Memory monitor read last - output logic mon_r_last_o + output logic mon_r_last_o ); localparam int unsigned StrbWidth = DataWidth / 8; - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [IdWidth-1:0] id_t; - typedef logic [StrbWidth-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; - `AXI_TYPEDEF_AW_CHAN_T(aw_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t) + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [IdWidth-1:0] id_t; + typedef logic [StrbWidth-1:0] strb_t; + typedef logic [AwUserWidth-1:0] aw_user_t; + typedef logic [WUserWidth-1:0] w_user_t; + typedef logic [BUserWidth-1:0] b_user_t; + typedef logic [ArUserWidth-1:0] ar_user_t; + typedef logic [RUserWidth-1:0] r_user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, w_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_t, id_t, b_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, ar_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, r_user_t) typedef struct packed { logic valid; @@ -337,14 +351,24 @@ endmodule /// /// See the documentation of the main module for the definition of ports and parameters. module axi_sim_mem_intf #( - parameter int unsigned AXI_ADDR_WIDTH = 32'd0, - parameter int unsigned AXI_DATA_WIDTH = 32'd0, - parameter int unsigned AXI_ID_WIDTH = 32'd0, - parameter int unsigned AXI_USER_WIDTH = 32'd0, - parameter bit WARN_UNINITIALIZED = 1'b0, - parameter bit ClearErrOnAccess = 1'b0, - parameter time APPL_DELAY = 0ps, - parameter time ACQ_DELAY = 0ps + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// AXI AW user signal width + parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH, + /// AXI W user signal width + parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH, + /// AXI B user signal width + parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH, + /// AXI AR user signal width + parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH, + /// AXI R user signal width + parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH + parameter bit WARN_UNINITIALIZED = 1'b0, + parameter bit CLEAR_ERR_ON_ACCESS = 1'b0, + parameter time APPL_DELAY = 0ps, + parameter time ACQ_DELAY = 0ps ) ( input logic clk_i, input logic rst_ni, @@ -382,11 +406,15 @@ module axi_sim_mem_intf #( .AddrWidth (AXI_ADDR_WIDTH), .DataWidth (AXI_DATA_WIDTH), .IdWidth (AXI_ID_WIDTH), - .UserWidth (AXI_USER_WIDTH), + .AwUserWidth (AXI_AW_USER_WIDTH), + .WUserWidth (AXI_W_USER_WIDTH), + .BUserWidth (AXI_B_USER_WIDTH), + .ArUserWidth (AXI_AR_USER_WIDTH), + .RUserWidth (AXI_R_USER_WIDTH), .axi_req_t (axi_req_t), .axi_rsp_t (axi_resp_t), .WarnUninitialized (WARN_UNINITIALIZED), - .ClearErrOnAccess (ClearErrOnAccess), + .ClearErrOnAccess (CLEAR_ERR_ON_ACCESS), .ApplDelay (APPL_DELAY), .AcqDelay (ACQ_DELAY) ) i_sim_mem ( diff --git a/src/axi_test.sv b/src/axi_test.sv index 6fd789415..ef475698c 100644 --- a/src/axi_test.sv +++ b/src/axi_test.sv @@ -280,31 +280,44 @@ package axi_test; /// A driver for AXI4 interface. class axi_driver #( - parameter int AW = 32 , - parameter int DW = 32 , - parameter int IW = 8 , - parameter int UW = 1 , - parameter time TA = 0ns , // stimuli application time - parameter time TT = 0ns // stimuli test time + parameter int AW = 32 , + parameter int DW = 32 , + parameter int IW = 8 , + parameter int UW = 1 , + parameter int UWAW = UW , + parameter int UWW = UW , + parameter int UWB = UW , + parameter int UWAR = UW , + parameter int UWR = UW , + parameter time TA = 0ns , // stimuli application time + parameter time TT = 0ns // stimuli test time ); virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AW), .AXI_DATA_WIDTH(DW), .AXI_ID_WIDTH(IW), - .AXI_USER_WIDTH(UW) + .AXI_AW_USER_WIDTH(UWAW), + .AXI_W_USER_WIDTH (UWW), + .AXI_B_USER_WIDTH (UWB), + .AXI_AR_USER_WIDTH(UWAR), + .AXI_R_USER_WIDTH (UWR) ) axi; - typedef axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat_t; - typedef axi_w_beat #(.DW(DW), .UW(UW)) w_beat_t; - typedef axi_b_beat #(.IW(IW), .UW(UW)) b_beat_t; - typedef axi_r_beat #(.DW(DW), .IW(IW), .UW(UW)) r_beat_t; + typedef axi_ax_beat #(.AW(AW), .IW(IW), .UW(UWAW)) ax_beat_t; + typedef axi_w_beat #(.DW(DW), .UW(UWW)) w_beat_t; + typedef axi_b_beat #(.IW(IW), .UW(UWB)) b_beat_t; + typedef axi_r_beat #(.DW(DW), .IW(IW), .UW(UWR)) r_beat_t; function new( virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AW), .AXI_DATA_WIDTH(DW), .AXI_ID_WIDTH(IW), - .AXI_USER_WIDTH(UW) + .AXI_AW_USER_WIDTH(UWAW), + .AXI_W_USER_WIDTH (UWW), + .AXI_B_USER_WIDTH (UWB), + .AXI_AR_USER_WIDTH(UWAR), + .AXI_R_USER_WIDTH (UWR) ) axi ); this.axi = axi; @@ -680,13 +693,18 @@ package axi_test; class axi_rand_master #( // AXI interface parameters - parameter int AW = 32, - parameter int DW = 32, - parameter int IW = 8, - parameter int UW = 1, + parameter int AW = 32, + parameter int DW = 32, + parameter int IW = 8, + parameter int UW = 1, + parameter int UWAW = UW, + parameter int UWW = UW, + parameter int UWB = UW, + parameter int UWAR = UW, + parameter int UWR = UW, // Stimuli application and test time - parameter time TA = 0ps, - parameter time TT = 0ps, + parameter time TA = 0ps, + parameter time TT = 0ps, // Maximum number of read and write transactions in flight parameter int MAX_READ_TXNS = 1, parameter int MAX_WRITE_TXNS = 1, @@ -714,7 +732,7 @@ package axi_test; parameter int N_AXI_IDS = 2**IW ); typedef axi_test::axi_driver #( - .AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TA), .TT(TT) + .AW(AW), .DW(DW), .IW(IW), .UWAW(UWAW), .UWW(UWW), .UWB(UWB), .UWAR(UWAR), .UWR(UWR), .TA(TA), .TT(TT) ) axi_driver_t; typedef logic [AW-1:0] addr_t; typedef axi_pkg::burst_t burst_t; @@ -723,7 +741,6 @@ package axi_test; typedef logic [IW-1:0] id_t; typedef axi_pkg::len_t len_t; typedef axi_pkg::size_t size_t; - typedef logic [UW-1:0] user_t; typedef axi_pkg::mem_type_t mem_type_t; typedef axi_driver_t::ax_beat_t ax_beat_t; @@ -770,7 +787,11 @@ package axi_test; .AXI_ADDR_WIDTH(AW), .AXI_DATA_WIDTH(DW), .AXI_ID_WIDTH(IW), - .AXI_USER_WIDTH(UW) + .AXI_AW_USER_WIDTH(UWAW), + .AXI_W_USER_WIDTH (UWW), + .AXI_B_USER_WIDTH (UWB), + .AXI_AR_USER_WIDTH(UWAR), + .AXI_R_USER_WIDTH (UWR) ) axi ); if (AXI_MAX_BURST_LEN <= 0 || AXI_MAX_BURST_LEN > 256) begin @@ -1260,13 +1281,18 @@ package axi_test; class axi_rand_slave #( // AXI interface parameters - parameter int AW = 32, - parameter int DW = 32, - parameter int IW = 8, - parameter int UW = 1, + parameter int AW = 32, + parameter int DW = 32, + parameter int IW = 8, + parameter int UW = 1, + parameter int UWAW = UW, + parameter int UWW = UW, + parameter int UWB = UW, + parameter int UWAR = UW, + parameter int UWR = UW, // Stimuli application and test time - parameter time TA = 0ps, - parameter time TT = 0ps, + parameter time TA = 0ps, + parameter time TT = 0ps, parameter bit RAND_RESP = 0, // Upper and lower bounds on wait cycles on Ax, W, and resp (R and B) channels parameter int AX_MIN_WAIT_CYCLES = 0, @@ -1281,7 +1307,7 @@ package axi_test; parameter bit MAPPED = 1'b0 ); typedef axi_test::axi_driver #( - .AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TA), .TT(TT) + .AW(AW), .DW(DW), .IW(IW), .UWAW(UWAW), .UWW(UWW), .UWB(UWB), .UWAR(UWAR), .UWR(UWR), .TA(TA), .TT(TT) ) axi_driver_t; typedef rand_id_queue_pkg::rand_id_queue #( .data_t (axi_driver_t::ax_beat_t), @@ -1308,7 +1334,11 @@ package axi_test; .AXI_ADDR_WIDTH(AW), .AXI_DATA_WIDTH(DW), .AXI_ID_WIDTH(IW), - .AXI_USER_WIDTH(UW) + .AXI_AW_USER_WIDTH(UWAW), + .AXI_W_USER_WIDTH (UWW), + .AXI_B_USER_WIDTH (UWB), + .AXI_AR_USER_WIDTH(UWAR), + .AXI_R_USER_WIDTH (UWR) ) axi ); this.drv = new(axi); @@ -1795,19 +1825,24 @@ package axi_test; /// AXI Monitor. class axi_monitor #( /// AXI4+ATOP ID width - parameter int unsigned IW = 0, + parameter int unsigned IW = 0, /// AXI4+ATOP address width - parameter int unsigned AW = 0, + parameter int unsigned AW = 0, /// AXI4+ATOP data width - parameter int unsigned DW = 0, + parameter int unsigned DW = 0, /// AXI4+ATOP user width - parameter int unsigned UW = 0, + parameter int unsigned UW = 0, + parameter int unsigned UWAW = UW, + parameter int unsigned UWW = UW, + parameter int unsigned UWB = UW, + parameter int unsigned UWAR = UW, + parameter int unsigned UWR = UW, /// Stimuli test time parameter time TT = 0ns ); typedef axi_test::axi_driver #( - .AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TT), .TT(TT) + .AW(AW), .DW(DW), .IW(IW), .UWAW(UWAW), .UWW(UWW), .UWB(UWB), .UWAR(UWAR), .UWR(UWR), .TA(TA), .TT(TT) ) axi_driver_t; typedef axi_driver_t::ax_beat_t ax_beat_t; @@ -1824,7 +1859,11 @@ package axi_test; .AXI_ADDR_WIDTH(AW), .AXI_DATA_WIDTH(DW), .AXI_ID_WIDTH(IW), - .AXI_USER_WIDTH(UW) + .AXI_AW_USER_WIDTH(UWAW), + .AXI_W_USER_WIDTH (UWW), + .AXI_B_USER_WIDTH (UWB), + .AXI_AR_USER_WIDTH(UWAR), + .AXI_R_USER_WIDTH (UWR) ) axi ); this.drv = new(axi); @@ -1890,13 +1929,18 @@ package axi_test; /// end class axi_scoreboard #( /// AXI4+ATOP ID width - parameter int unsigned IW = 0, + parameter int unsigned IW = 0, /// AXI4+ATOP address width - parameter int unsigned AW = 0, + parameter int unsigned AW = 0, /// AXI4+ATOP data width - parameter int unsigned DW = 0, + parameter int unsigned DW = 0, /// AXI4+ATOP user width - parameter int unsigned UW = 0, + parameter int unsigned UW = 0, + parameter int unsigned UWAW = UW, + parameter int unsigned UWW = UW, + parameter int unsigned UWB = UW, + parameter int unsigned UWAR = UW, + parameter int unsigned UWR = UW, /// Stimuli test time parameter time TT = 0ns ); @@ -1914,10 +1958,10 @@ package axi_test; typedef logic [7:0] byte_t; typedef logic [IW-1:0] axi_id_t; typedef logic [AW-1:0] axi_addr_t; - typedef axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat_t; - typedef axi_w_beat #(.DW(DW), .UW(UW)) w_beat_t; - typedef axi_b_beat #(.IW(IW), .UW(UW)) b_beat_t; - typedef axi_r_beat #(.DW(DW), .IW(IW), .UW(UW)) r_beat_t; + typedef axi_ax_beat #(.AW(AW), .IW(IW), .UW(UWAW)) ax_beat_t; + typedef axi_w_beat #(.DW(DW), .UW(UWW)) w_beat_t; + typedef axi_b_beat #(.IW(IW), .UW(UWB)) b_beat_t; + typedef axi_r_beat #(.DW(DW), .IW(IW), .UW(UWR)) r_beat_t; // Monitor interface virtual AXI_BUS_DV #( @@ -1943,10 +1987,14 @@ package axi_test; /// New constructor function new( virtual AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AW ), - .AXI_DATA_WIDTH ( DW ), - .AXI_ID_WIDTH ( IW ), - .AXI_USER_WIDTH ( UW ) + .AXI_ADDR_WIDTH(AW), + .AXI_DATA_WIDTH(DW), + .AXI_ID_WIDTH(IW), + .AXI_AW_USER_WIDTH(UWAW), + .AXI_W_USER_WIDTH (UWW), + .AXI_B_USER_WIDTH (UWB), + .AXI_AR_USER_WIDTH(UWAR), + .AXI_R_USER_WIDTH (UWR) ) axi ); this.axi = axi; @@ -2310,18 +2358,26 @@ package axi_test; class axi_file_master #( - // AXI interface parameters - parameter int AW = 32, - parameter int DW = 32, - parameter int IW = 8, - parameter int UW = 1, + /// AXI4+ATOP ID width + parameter int unsigned IW = 0, + /// AXI4+ATOP address width + parameter int unsigned AW = 0, + /// AXI4+ATOP data width + parameter int unsigned DW = 0, + /// AXI4+ATOP user width + parameter int unsigned UW = 0, + parameter int unsigned UWAW = UW, + parameter int unsigned UWW = UW, + parameter int unsigned UWB = UW, + parameter int unsigned UWAR = UW, + parameter int unsigned UWR = UW, // Stimuli application and test time parameter time TA = 0ps, parameter time TT = 0ps ); typedef axi_test::axi_driver #( - .AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TA), .TT(TT) + .AW(AW), .DW(DW), .IW(IW), .UWAW(UWAW), .UWW(UWW), .UWB(UWB), .UWAR(UWAR), .UWR(UWR), .TA(TA), .TT(TT) ) axi_driver_t; typedef axi_driver_t::ax_beat_t ax_beat_t; @@ -2351,7 +2407,11 @@ package axi_test; .AXI_ADDR_WIDTH(AW), .AXI_DATA_WIDTH(DW), .AXI_ID_WIDTH(IW), - .AXI_USER_WIDTH(UW) + .AXI_AW_USER_WIDTH(UWAW), + .AXI_W_USER_WIDTH (UWW), + .AXI_B_USER_WIDTH (UWB), + .AXI_AR_USER_WIDTH(UWAR), + .AXI_R_USER_WIDTH (UWR) ) axi ); this.drv = new(axi);