diff --git a/Changelog.md b/Changelog.md index 650f992..5020500 100644 --- a/Changelog.md +++ b/Changelog.md @@ -9,6 +9,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ### Fixed - lookup_serial: Make `write_ready_o` independent of `write_valid_i`. +### Changed +- Rename `SET_COUNT` to `WAY_COUNT` to correct terminology, as it reflects the number of ways in a set. + ## 0.1.1 - 28.06.2024 ### Added - Allow fetches to bypass prefetches in L1. diff --git a/src/snitch_icache.sv b/src/snitch_icache.sv index ab673cf..bb5b8d2 100644 --- a/src/snitch_icache.sv +++ b/src/snitch_icache.sv @@ -10,14 +10,14 @@ module snitch_icache #( /// Number of request (fetch) ports parameter int unsigned NR_FETCH_PORTS = -1, - /// L0 Cache Line Count + /// L0 Cache Line Count (L0 is fully associative) parameter int unsigned L0_LINE_COUNT = -1, /// Cache Line Width parameter int unsigned LINE_WIDTH = -1, /// The number of cache lines per set. Power of two; >= 2. parameter int unsigned LINE_COUNT = -1, /// The set associativity of the cache. Power of two; >= 1. - parameter int unsigned SET_COUNT = 1, + parameter int unsigned WAY_COUNT = 1, /// Fetch interface address width. Same as FILL_AW; >= 1. parameter int unsigned FETCH_AW = -1, /// Fetch interface data width. Power of two; >= 8. @@ -88,7 +88,7 @@ module snitch_icache #( LINE_WIDTH: LINE_WIDTH, LINE_COUNT: LINE_COUNT, L0_LINE_COUNT: L0_LINE_COUNT, - SET_COUNT: SET_COUNT, + WAY_COUNT: WAY_COUNT, PENDING_COUNT: NUM_AXI_OUTSTANDING, FETCH_AW: FETCH_AW, FETCH_DW: FETCH_DW, @@ -103,7 +103,7 @@ module snitch_icache #( FILL_ALIGN: $clog2(FILL_DW/8), LINE_ALIGN: $clog2(LINE_WIDTH/8), COUNT_ALIGN: $clog2(LINE_COUNT), - SET_ALIGN: $clog2(SET_COUNT), + SET_ALIGN: $clog2(WAY_COUNT), TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8) - $clog2(LINE_COUNT), L0_TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8), L0_EARLY_TAG_WIDTH: @@ -119,7 +119,7 @@ module snitch_icache #( assert(L0_LINE_COUNT > 0); assert(LINE_WIDTH > 0); assert(LINE_COUNT > 1); - assert(SET_COUNT >= 2) else $warning("Only >= 2 sets are supported"); + assert(WAY_COUNT >= 2) else $warning("Only >= 2 sets are supported"); assert(FETCH_AW > 0); assert(FETCH_DW > 0); assert(FILL_AW > 0); @@ -131,7 +131,7 @@ module snitch_icache #( assert(2**$clog2(LINE_COUNT) == LINE_COUNT) else $fatal(1, "Cache LINE_COUNT %0d is not a power of two", LINE_COUNT); // NOTE(fschuiki): I think the following is not needed - // assert(2**$clog2(SET_COUNT) == SET_COUNT) else $fatal(1, "Cache SET_COUNT %0d is not a power of two", SET_COUNT); + // assert(2**$clog2(WAY_COUNT) == WAY_COUNT) else $fatal(1, "Cache WAY_COUNT %0d is not a power of two", WAY_COUNT); assert(2**$clog2(FETCH_DW) == FETCH_DW) else $fatal(1, "Cache FETCH_DW %0d is not a power of two", FETCH_DW); assert(2**$clog2(FILL_DW) == FILL_DW) diff --git a/src/snitch_icache_lookup_parallel.sv b/src/snitch_icache_lookup_parallel.sv index 26b5d61..12f8594 100644 --- a/src/snitch_icache_lookup_parallel.sv +++ b/src/snitch_icache_lookup_parallel.sv @@ -50,9 +50,9 @@ module snitch_icache_lookup_parallel #( // Multiplex read and write access to the RAMs onto one port, prioritizing // write accesses. logic [CFG.COUNT_ALIGN-1:0] ram_addr ; - logic [CFG.SET_COUNT-1:0] ram_enable ; - logic [CFG.LINE_WIDTH-1:0] ram_wdata, ram_rdata [CFG.SET_COUNT] ; - logic [CFG.TAG_WIDTH+1:0] ram_wtag, ram_rtag [CFG.SET_COUNT] ; + logic [CFG.WAY_COUNT-1:0] ram_enable ; + logic [CFG.LINE_WIDTH-1:0] ram_wdata, ram_rdata [CFG.WAY_COUNT] ; + logic [CFG.TAG_WIDTH+1:0] ram_wtag, ram_rtag [CFG.WAY_COUNT] ; logic ram_write ; logic ram_write_q; logic [CFG.COUNT_ALIGN:0] init_count_q; @@ -86,7 +86,7 @@ module snitch_icache_lookup_parallel #( ram_wtag = '0; end else if (write_valid_i) begin ram_addr = write_addr_i; - ram_enable = CFG.SET_COUNT > 1 ? $unsigned(1 << write_set_i) : 1'b1; + ram_enable = CFG.WAY_COUNT > 1 ? $unsigned(1 << write_set_i) : 1'b1; ram_write = 1'b1; write_ready_o = 1'b1; end else if (out_ready_i) begin @@ -144,7 +144,7 @@ module snitch_icache_lookup_parallel #( end // Instantiate the RAM sets. - for (genvar i = 0; i < CFG.SET_COUNT; i++) begin : g_sets + for (genvar i = 0; i < CFG.WAY_COUNT; i++) begin : g_sets tc_sram_impl #( .NumWords (CFG.LINE_COUNT), .DataWidth (CFG.TAG_WIDTH+2), @@ -188,12 +188,12 @@ module snitch_icache_lookup_parallel #( // Determine which RAM line hit, and multiplex that data to the output. logic [CFG.TAG_WIDTH-1:0] required_tag; - logic [CFG.SET_COUNT-1:0] line_hit; + logic [CFG.WAY_COUNT-1:0] line_hit; always_comb begin - automatic logic [CFG.SET_COUNT-1:0] errors; + automatic logic [CFG.WAY_COUNT-1:0] errors; required_tag = addr_q[CFG.FETCH_AW-1:CFG.LINE_ALIGN + CFG.COUNT_ALIGN]; - for (int i = 0; i < CFG.SET_COUNT; i++) begin + for (int i = 0; i < CFG.WAY_COUNT; i++) begin line_hit[i] = ram_rtag[i][CFG.TAG_WIDTH+1] && ram_rtag[i][CFG.TAG_WIDTH-1:0] == required_tag; errors[i] = ram_rtag[i][CFG.TAG_WIDTH] && line_hit[i]; @@ -204,14 +204,14 @@ module snitch_icache_lookup_parallel #( always_comb begin for (int i = 0; i < CFG.LINE_WIDTH; i++) begin - automatic logic [CFG.SET_COUNT-1:0] masked; - for (int j = 0; j < CFG.SET_COUNT; j++) + automatic logic [CFG.WAY_COUNT-1:0] masked; + for (int j = 0; j < CFG.WAY_COUNT; j++) masked[j] = ram_rdata[j][i] & line_hit[j]; data_d.data[i] = |masked; end end - lzc #(.WIDTH(CFG.SET_COUNT)) i_lzc ( + lzc #(.WIDTH(CFG.WAY_COUNT)) i_lzc ( .in_i ( line_hit ), .cnt_o ( data_d.cset ), .empty_o ( ) diff --git a/src/snitch_icache_lookup_serial.sv b/src/snitch_icache_lookup_serial.sv index db1ac0b..371ceb6 100644 --- a/src/snitch_icache_lookup_serial.sv +++ b/src/snitch_icache_lookup_serial.sv @@ -45,7 +45,7 @@ module snitch_icache_lookup_serial #( input sram_cfg_tag_t sram_cfg_tag_i ); - localparam int unsigned DataAddrWidth = $clog2(CFG.SET_COUNT) + CFG.COUNT_ALIGN; + localparam int unsigned DataAddrWidth = $clog2(CFG.WAY_COUNT) + CFG.COUNT_ALIGN; `ifndef SYNTHESIS initial assert(CFG != '0); @@ -85,8 +85,8 @@ module snitch_icache_lookup_serial #( logic req_handshake; logic [CFG.COUNT_ALIGN-1:0] tag_addr; - logic [CFG.SET_COUNT-1:0] tag_enable; - logic [CFG.TAG_WIDTH+1:0] tag_wdata, tag_rdata [CFG.SET_COUNT]; + logic [CFG.WAY_COUNT-1:0] tag_enable; + logic [CFG.TAG_WIDTH+1:0] tag_wdata, tag_rdata [CFG.WAY_COUNT]; logic tag_write; tag_req_t tag_req_d, tag_req_q; @@ -95,7 +95,7 @@ module snitch_icache_lookup_serial #( logic tag_handshake; logic [CFG.TAG_WIDTH-1:0] required_tag; - logic [CFG.SET_COUNT-1:0] line_hit; + logic [CFG.WAY_COUNT-1:0] line_hit; logic [DataAddrWidth-1:0] lookup_addr; logic [DataAddrWidth-1:0] write_addr; @@ -137,7 +137,7 @@ module snitch_icache_lookup_serial #( // Instantiate the tag sets. if (CFG.L1_TAG_SCM) begin : gen_scm - for (genvar i = 0; i < CFG.SET_COUNT; i++) begin : g_sets + for (genvar i = 0; i < CFG.WAY_COUNT; i++) begin : g_sets register_file_1r_1w #( .ADDR_WIDTH ($clog2(CFG.LINE_COUNT)), .DATA_WIDTH (CFG.TAG_WIDTH+2 ) @@ -161,12 +161,12 @@ module snitch_icache_lookup_serial #( ); end end else begin : gen_sram - logic [CFG.SET_COUNT*(CFG.TAG_WIDTH+2)-1:0] tag_rdata_flat; - for (genvar i = 0; i < CFG.SET_COUNT; i++) begin : g_sets_rdata + logic [CFG.WAY_COUNT*(CFG.TAG_WIDTH+2)-1:0] tag_rdata_flat; + for (genvar i = 0; i < CFG.WAY_COUNT; i++) begin : g_sets_rdata assign tag_rdata[i] = tag_rdata_flat[i*(CFG.TAG_WIDTH+2)+:CFG.TAG_WIDTH+2]; end tc_sram_impl #( - .DataWidth ( (CFG.TAG_WIDTH+2) * CFG.SET_COUNT ), + .DataWidth ( (CFG.TAG_WIDTH+2) * CFG.WAY_COUNT ), .ByteWidth ( CFG.TAG_WIDTH+2 ), .NumWords ( CFG.LINE_COUNT ), .NumPorts ( 1 ), @@ -179,16 +179,16 @@ module snitch_icache_lookup_serial #( .req_i ( |tag_enable ), .we_i ( tag_write ), .addr_i ( tag_addr ), - .wdata_i ( {CFG.SET_COUNT{tag_wdata}} ), + .wdata_i ( {CFG.WAY_COUNT{tag_wdata}} ), .be_i ( tag_enable ), .rdata_o ( tag_rdata_flat ) ); end // Determine which set hit - logic [CFG.SET_COUNT-1:0] errors; + logic [CFG.WAY_COUNT-1:0] errors; assign required_tag = tag_req_q.addr[CFG.FETCH_AW-1:CFG.LINE_ALIGN + CFG.COUNT_ALIGN]; - for (genvar i = 0; i < CFG.SET_COUNT; i++) begin : gen_line_hit + for (genvar i = 0; i < CFG.WAY_COUNT; i++) begin : gen_line_hit assign line_hit[i] = tag_rdata[i][CFG.TAG_WIDTH+1] && tag_rdata[i][CFG.TAG_WIDTH-1:0] == required_tag; // check valid bit and tag assign errors[i] = tag_rdata[i][CFG.TAG_WIDTH] && line_hit[i]; // check error bit @@ -196,7 +196,7 @@ module snitch_icache_lookup_serial #( assign tag_rsp_s.hit = |line_hit; assign tag_rsp_s.error = |errors; - lzc #(.WIDTH(CFG.SET_COUNT)) i_lzc ( + lzc #(.WIDTH(CFG.WAY_COUNT)) i_lzc ( .in_i ( line_hit ), .cnt_o ( tag_rsp_s.cset ), .empty_o ( ) @@ -282,7 +282,7 @@ module snitch_icache_lookup_serial #( tc_sram_impl #( .DataWidth ( CFG.LINE_WIDTH ), - .NumWords ( CFG.LINE_COUNT * CFG.SET_COUNT ), + .NumWords ( CFG.LINE_COUNT * CFG.WAY_COUNT ), .NumPorts ( 1 ), .impl_in_t ( sram_cfg_data_t ) ) i_data ( diff --git a/src/snitch_icache_pkg.sv b/src/snitch_icache_pkg.sv index 17cfa37..94763fb 100644 --- a/src/snitch_icache_pkg.sv +++ b/src/snitch_icache_pkg.sv @@ -19,7 +19,7 @@ package snitch_icache_pkg; int unsigned NR_FETCH_PORTS; int unsigned LINE_WIDTH; int unsigned LINE_COUNT; - int unsigned SET_COUNT; + int unsigned WAY_COUNT; int unsigned PENDING_COUNT; int unsigned L0_LINE_COUNT; int unsigned FETCH_AW; diff --git a/src/snitch_read_only_cache.sv b/src/snitch_read_only_cache.sv index 9142abc..a94e6c9 100644 --- a/src/snitch_read_only_cache.sv +++ b/src/snitch_read_only_cache.sv @@ -14,7 +14,7 @@ module snitch_read_only_cache #( /// The number of cache lines per set. Power of two; >= 2. parameter int unsigned LineCount = -1, /// The set associativity of the cache. Power of two; >= 1. - parameter int unsigned SetCount = 1, + parameter int unsigned WayCount = 1, /// AXI address width parameter int unsigned AxiAddrWidth = 0, /// AXI data width @@ -194,7 +194,7 @@ module snitch_read_only_cache #( localparam snitch_icache_pkg::config_t CFG = '{ LINE_WIDTH: LineWidth, LINE_COUNT: LineCount, - SET_COUNT: SetCount, + WAY_COUNT: WayCount, PENDING_COUNT: PendingCount, FETCH_AW: AxiAddrWidth, FETCH_DW: AxiDataWidth, @@ -209,7 +209,7 @@ module snitch_read_only_cache #( FILL_ALIGN: $clog2(AxiDataWidth/8), LINE_ALIGN: $clog2(LineWidth/8), COUNT_ALIGN: cf_math_pkg::idx_width(LineCount), - SET_ALIGN: cf_math_pkg::idx_width(SetCount), + SET_ALIGN: cf_math_pkg::idx_width(WayCount), TAG_WIDTH: AxiAddrWidth - $clog2(LineWidth/8) - $clog2(LineCount) + 1, ID_WIDTH: 2**AxiIdWidth, PENDING_IW: $clog2(PendingCount), diff --git a/test/snitch_icache_l0_tb.sv b/test/snitch_icache_l0_tb.sv index 080ad6f..658ac88 100644 --- a/test/snitch_icache_l0_tb.sv +++ b/test/snitch_icache_l0_tb.sv @@ -57,7 +57,7 @@ module snitch_icache_l0_tb #( parameter int L0_LINE_COUNT = 8, parameter int LINE_WIDTH = 128, parameter int LINE_COUNT = 0, - parameter int SET_COUNT = 1, + parameter int WAY_COUNT = 1, parameter int FETCH_AW = AddrWidth, parameter int FETCH_DW = 32, parameter int FILL_AW = AddrWidth, @@ -81,7 +81,7 @@ module snitch_icache_l0_tb #( LINE_WIDTH: LINE_WIDTH, LINE_COUNT: LINE_COUNT, L0_LINE_COUNT: L0_LINE_COUNT, - SET_COUNT: SET_COUNT, + WAY_COUNT: WAY_COUNT, PENDING_COUNT: 2, FETCH_AW: FETCH_AW, FETCH_DW: FETCH_DW, @@ -96,7 +96,7 @@ module snitch_icache_l0_tb #( FILL_ALIGN: $clog2(FILL_DW/8), LINE_ALIGN: $clog2(LINE_WIDTH/8), COUNT_ALIGN: $clog2(LINE_COUNT), - SET_ALIGN: $clog2(SET_COUNT), + SET_ALIGN: $clog2(WAY_COUNT), TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8) - $clog2(LINE_COUNT) + 1, L0_TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8), L0_EARLY_TAG_WIDTH: diff --git a/test/snitch_read_only_cache_tb.sv b/test/snitch_read_only_cache_tb.sv index 1f3687e..9d4ba7f 100644 --- a/test/snitch_read_only_cache_tb.sv +++ b/test/snitch_read_only_cache_tb.sv @@ -249,7 +249,7 @@ module snitch_read_only_cache_tb #( parameter int unsigned AxiIdWidth = 5, parameter int unsigned LineWidth = 256, parameter int unsigned LineCount = 128, - parameter int unsigned SetCount = 2 + parameter int unsigned WayCount = 2 ); localparam time ClkPeriod = 10ns; @@ -362,7 +362,7 @@ module snitch_read_only_cache_tb #( snitch_read_only_cache #( .LineWidth ( LineWidth ), .LineCount ( LineCount ), - .SetCount ( SetCount ), + .WayCount ( WayCount ), .AxiAddrWidth ( AxiAddrWidth ), .AxiDataWidth ( AxiDataWidth ), .AxiIdWidth ( AxiInIdWidth ),