Recent change in verilator broke stuff (or at least that's my understanding of it)

[ourspalois]

Hi I am a french intern in computer architecture at Université paris saclay and I work on the implementation of IBEX in a low power system.

I just started system verilog a week ago, so my understanding of it is quite poor. If the issue is not correct do not hesitate to close the issue.

For context : I recently changed my computer so I re-installed verilator from sources. Doing So broke many pieces of my system.
I am now getting errors like this when compiling:

 src/pulp-platform.org__common_cells_1.28.0/src/lzc.sv:23:51: Static access to non-static task/function 'idx_width'

      parameter int unsigned CNT_WIDTH = cf_math_pkg::idx_width(WIDTH) 

I also get the same errors in the tcdm interconnect package.

At first I though I did something wrong but after reading the reference of system verilog I found that the :: is indeed reserved for static functions. And so the call to idx_width which is labelled as automatic is indeed illegal. (or at least that's what I am thinking with my small understanding of the language)

I just discovered there has been a very recent change in verilator : verilator/verilator#4072
My understanding is that calls to automatic functions need to be hierarchical for verilator to accept them.

I will just checkout to a branch of verilator that doesn't have the patch and see where it goes.