From c27fc5b3fc707bcb883c1925561318920c2543e3 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 10 May 2023 12:10:25 +0200 Subject: [PATCH] Removed RF 1 Write Multiport Read as duplicated from SCM. --- Bender.yml | 3 +- .../register_file_1w_multi_port_read.sv | 173 ------------------ 2 files changed, 1 insertion(+), 175 deletions(-) delete mode 100644 RTL/L1_CACHE/register_file_1w_multi_port_read.sv diff --git a/Bender.yml b/Bender.yml index 3c1089d..32f4843 100644 --- a/Bender.yml +++ b/Bender.yml @@ -6,7 +6,7 @@ package: dependencies: common_cells: { git: "git@github.com:pulp-platform/common_cells.git", version: 1.13.1 } - tech_cells_generic: { git: "git@github.com:pulp-platform/tech_cells_generic", version: 0.1.6 } + tech_cells_generic: { git: "git@github.com:pulp-platform/tech_cells_generic", version: 0.2.11 } scm: { git: "git@github.com:pulp-platform/scm.git", version: 1.0.1 } icache-intc: { git: "git@github.com:pulp-platform/icache-intc.git", version: 1.0.1 } axi_slice: { git: "git@github.com:pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) @@ -24,7 +24,6 @@ sources: - RTL/L1.5_CACHE/REP_buffer_4.sv - RTL/L1_CACHE/pri_icache_controller.sv - RTL/L1_CACHE/refill_arbiter.sv - - RTL/L1_CACHE/register_file_1w_multi_port_read.sv # Level 1 - CTRL_UNIT/hier_icache_ctrl_unit_wrap.sv - RTL/L1.5_CACHE/AXI4_REFILL_Resp_Deserializer.sv diff --git a/RTL/L1_CACHE/register_file_1w_multi_port_read.sv b/RTL/L1_CACHE/register_file_1w_multi_port_read.sv deleted file mode 100644 index 9d93525..0000000 --- a/RTL/L1_CACHE/register_file_1w_multi_port_read.sv +++ /dev/null @@ -1,173 +0,0 @@ -// Copyright 2014-2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module register_file_1w_multi_port_read -#( - parameter ADDR_WIDTH = 5, - parameter DATA_WIDTH = 32, - - parameter N_READ = 2, - parameter N_WRITE = 1 -) -( - input logic clk, - input logic rst_n, - input logic test_en_i, - - // Read port - input logic [N_READ-1:0] ReadEnable, - input logic [N_READ-1:0][ADDR_WIDTH-1:0] ReadAddr, - output logic [N_READ-1:0][DATA_WIDTH-1:0] ReadData, - - // Write port - input logic WriteEnable, - input logic [ADDR_WIDTH-1:0] WriteAddr, - input logic [DATA_WIDTH-1:0] WriteData -); - - localparam NUM_WORDS = 2**ADDR_WIDTH; - - // Read address register, located at the input of the address decoder - logic [N_READ-1:0][ADDR_WIDTH-1:0] RAddrRegxDP; - logic [N_READ-1:0][NUM_WORDS-1:0] RAddrOneHotxD; - - logic [DATA_WIDTH-1:0] MemContentxDP[NUM_WORDS]; - - logic [NUM_WORDS-1:0] WAddrOneHotxD; - logic [NUM_WORDS-1:0] ClocksxC; - logic [DATA_WIDTH-1:0] WDataIntxD; - - logic clk_int; - - int unsigned i; - int unsigned k; - - genvar x; - genvar z; - - cluster_clock_gating CG_WE_GLOBAL - ( - .clk_o ( clk_int ), - .en_i ( WriteEnable ), - .test_en_i ( test_en_i ), - .clk_i ( clk ) - ); - - //----------------------------------------------------------------------------- - //-- READ : Read address register - //----------------------------------------------------------------------------- - - generate - for(z=0; z