diff --git a/hardware/src/mempool_group_floonoc_wrapper.sv b/hardware/src/mempool_group_floonoc_wrapper.sv
index 204d43fd..af388257 100644
--- a/hardware/src/mempool_group_floonoc_wrapper.sv
+++ b/hardware/src/mempool_group_floonoc_wrapper.sv
@@ -222,7 +222,7 @@ for (genvar i = 0; i < NumTilesPerGroup; i++) begin : gen_router_req_to_slave_re
       wen     : floo_req_from_router_after_xbar[i][j].payload.wen,
       be      : floo_req_from_router_after_xbar[i][j].payload.be,
       // row | bank  <= row | bank | tile
-      tgt_addr: floo_req_from_router_after_xbar[i][j].hdr.tgt_addr[(NumTilesPerGroupWidth == 1 ? 0 : NumTilesPerGroupWidth) +: (idx_width(NumBanksPerTile) + TCDMAddrMemWidth)], // For TCDM Bank, remove tile offset, it is selected by "req_tile_sel"
+      tgt_addr: floo_req_from_router_after_xbar[i][j].hdr.tgt_addr[(NumTilesPerGroup == 1 ? 0 : NumTilesPerGroupWidth) +: (idx_width(NumBanksPerTile) + TCDMAddrMemWidth)], // For TCDM Bank, remove tile offset, it is selected by "req_tile_sel"
       ini_addr: floo_req_from_router_after_xbar[i][j].hdr.src_tile_id,                      // For Crossbar when response back
       src_group_id: group_id_t'(floo_req_from_router_after_xbar[i][j].hdr.src_id)           // For NoC Router when response back
     };
diff --git a/hardware/src/mempool_pkg.sv b/hardware/src/mempool_pkg.sv
index 5096c5cb..4f6c43e3 100644
--- a/hardware/src/mempool_pkg.sv
+++ b/hardware/src/mempool_pkg.sv
@@ -161,7 +161,7 @@ package mempool_pkg;
    ***********************/
 
   localparam int unsigned ICacheSizeByte  = 512 * NumCoresPerCache;     // Total Size of instruction cache in bytes
-  localparam int unsigned ICacheSets      = NumCoresPerCache / 2;       // Number of sets
+  localparam int unsigned ICacheSets      = (NumCoresPerCache == 2) ? 2 : NumCoresPerCache / 2;       // Number of sets
   localparam int unsigned ICacheLineWidth = 32 * 2 * NumCoresPerCache;  // Size of each cache line in bits
 
   /*********************