diff --git a/software/runtime/runtime.mk b/software/runtime/runtime.mk
index 5c4051323..53b757b57 100644
--- a/software/runtime/runtime.mk
+++ b/software/runtime/runtime.mk
@@ -85,6 +85,22 @@ DEFINES += -DQLR_FIFO_SIZE=$(qlr_fifo_size)
 ifneq ($(qlr_fifo_size), 0)
 	DEFINES += -DQLR_CFG_BASE=$(qlr_cfg_base) -DQLR_MAX_REQUESTS=$(qlr_max_requests) -DQLR_MAX_RF_READS=$(qlr_max_rf_reads)
 endif
+# For systolic benchmarks' matrix dims
+ifneq ($(DIM_M),)
+DEFINES += -DDIM_M=$(DIM_M)
+endif
+ifneq ($(DIM_N),)
+DEFINES += -DDIM_N=$(DIM_N)
+endif
+ifneq ($(DIM_P),)
+DEFINES += -DDIM_P=$(DIM_P)
+endif
+ifneq ($(REP_COUNT),)
+DEFINES += -DREP_COUNT=$(REP_COUNT)
+endif
+ifneq ($(SYSTOLIC_LENGTH),)
+DEFINES += -DSYSTOLIC_LENGTH=$(SYSTOLIC_LENGTH)
+endif
 
 # Specify cross compilation target. This can be omitted if LLVM is built with riscv as default target
 RISCV_LLVM_TARGET  ?= --target=$(RISCV_TARGET) --sysroot=$(GCC_INSTALL_DIR)/$(RISCV_TARGET) --gcc-toolchain=$(GCC_INSTALL_DIR)
diff --git a/software/runtime/systolic/conv_qlr.h b/software/runtime/systolic/conv_qlr.h
index 4e96cb1b2..7b6b7a8c2 100644
--- a/software/runtime/systolic/conv_qlr.h
+++ b/software/runtime/systolic/conv_qlr.h
@@ -71,7 +71,9 @@
 #define K    3 // hardcoded, do not change
 
 // Repetition count
+#ifndef REP_COUNT
 #define REP_COUNT 1
+#endif
 // Systolic Length (must be divisor of NUM_CORES)
 #ifndef SYSTOLIC_LENGTH
 #define SYSTOLIC_LENGTH 16
diff --git a/software/runtime/systolic/xqueue.h b/software/runtime/systolic/xqueue.h
new file mode 100644
index 000000000..1252b052b
--- /dev/null
+++ b/software/runtime/systolic/xqueue.h
@@ -0,0 +1,26 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//    http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Author: Sergio Mazzola, ETH Zurich
+
+static inline void queue_push(void *const queue, int32_t data, int32_t *const ret) {
+  asm volatile("q.push.w %0, %1, (%2)" : "+r"(*ret) : "r"(data), "r"(queue) : "memory");
+}
+
+inline void queue_pop(void *const queue, int32_t *const ret) {
+  asm volatile("q.pop.w %0, 0(%1)" : "=r"(*ret) : "r"(queue) : "memory");
+}
+