From 49bb84512f6b89bde27c50384d0748212313f915 Mon Sep 17 00:00:00 2001 From: Philip Wiese Date: Wed, 5 Apr 2023 17:48:30 +0200 Subject: [PATCH 1/3] [fix] Fix issue in snitch_addr_demux --- hardware/src/snitch_addr_demux.sv | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hardware/src/snitch_addr_demux.sv b/hardware/src/snitch_addr_demux.sv index 7c1617b99..4990003b3 100644 --- a/hardware/src/snitch_addr_demux.sv +++ b/hardware/src/snitch_addr_demux.sv @@ -38,16 +38,25 @@ module snitch_addr_demux input address_map_t [NumRules-1:0] address_map_i ); - logic [LogNrOutput-1:0] slave_select; - logic [NumRules-1:0] addr_match; - logic [idx_width(NumRules)-1:0] rule_select; + localparam type idx_t = logic [LogNrOutput-1:0]; - assign slave_select = address_map_i[rule_select].slave_idx; + idx_t slave_select; + address_map_t addr_select; + logic [NumRules-1:0] addr_match; + logic [idx_width(NumRules)-1:0] rule_select; // Address Decoder always_comb begin : addr_decoder + addr_match = '0; + slave_select = '0; + addr_select = '0; + for (int i = 0; i < NumRules; i++) begin - addr_match[i] = (req_addr_i & address_map_i[i].mask) == address_map_i[i].value; + if ((req_addr_i & address_map_i[i].mask) == address_map_i[i].value) begin + addr_match[i] = 1'b1; + addr_select = address_map_i[rule_select]; + slave_select = idx_t'(addr_select.slave_idx); + end end end From dd4298c2453fdfe070ada535761e12efd2667b60 Mon Sep 17 00:00:00 2001 From: Philip Wiese Date: Fri, 31 Mar 2023 18:43:20 +0200 Subject: [PATCH 2/3] [fix] Adhere to custom compiler for VCS --- hardware/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hardware/Makefile b/hardware/Makefile index 5ed13ad31..5c5662418 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -189,12 +189,12 @@ $(buildpath)/compilevcs.sh: $(bender) $(config_mk) Makefile $(MEMPOOL_DIR)/Bende compile_vcs_simv: elabvcs $(buildpath)/mempool_simv $(buildpath)/mempool_simv: $(buildpath)/compilevcs.sh $(buildpath)/$(dpi_library)/mempool_vcs_dpi.so cd $(buildpath) && \ - $(vcs_cmd) vcs -full64 $(top_level) $(dpi_library)/mempool_vcs_dpi.so -debug_access=r -kdb -assert disable_cover -o mempool_simv + $(vcs_cmd) vcs -full64 $(top_level) -cc $(CC) -cpp $(CXX) -ld $(CXX) $(dpi_library)/mempool_vcs_dpi.so -debug_access=r -kdb -assert disable_cover -o mempool_simv compile_vcs_simvopt: elabvcs $(buildpath)/mempool_simvopt $(buildpath)/mempool_simvopt: $(buildpath)/compilevcs.sh $(buildpath)/$(dpi_library)/mempool_vcs_dpi.so cd $(buildpath) && \ - $(vcs_cmd) vcs -full64 $(top_level) $(dpi_library)/mempool_vcs_dpi.so -assert disable_cover -o mempool_simvopt + $(vcs_cmd) vcs -full64 $(top_level) -cc $(CC) -cpp $(CXX) -ld $(CXX) $(dpi_library)/mempool_vcs_dpi.so -assert disable_cover -o mempool_simvopt # Simulation simvcs: compile_vcs_simv From 09df703323a208d33a0fc6acdeeda682c2332d97 Mon Sep 17 00:00:00 2001 From: Philip Wiese Date: Mon, 17 Apr 2023 10:38:16 +0200 Subject: [PATCH 3/3] [change] Adapted changelog --- CHANGELOG.md | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index a14c1abe3..17f375e8f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,8 +7,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## Unreleased -## Changes +### Changes - Extended `tracevis.py` to support the new Perfetto UI and compress large traces +- Use custom compiler for VCS specified with `CC` and `CCX` environment variable + +### Fixed +- Fix type issue in `snitch_addr_demux` ## 0.6.0 - 2023-01-09