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First, thank you very much for all these very useful tools and designs that you contribute to the open hardware community.
I would like to report an issue on the SVASE tool. I was trying to "SVASE" the HPDcache IP I developed but I had some issues. Debugging a little bit with GDB, I found that SVASE does not support type definitions (typedef) within generate statements. I joined an example SystemVerilog file where SVASE is failing (Segmentation Fault).
Luckily, there are only 2 places where I do that in the HPDcache and it was very easy to relocate those typedefs outside the generate statements. Nevertheless, as this is supported by the SystemVerilog standard, I wanted to report the issue.
Hello PULP team,
First, thank you very much for all these very useful tools and designs that you contribute to the open hardware community.
I would like to report an issue on the SVASE tool. I was trying to "SVASE" the HPDcache IP I developed but I had some issues. Debugging a little bit with GDB, I found that SVASE does not support type definitions (typedef) within generate statements. I joined an example SystemVerilog file where SVASE is failing (Segmentation Fault).
Luckily, there are only 2 places where I do that in the HPDcache and it was very easy to relocate those typedefs outside the generate statements. Nevertheless, as this is supported by the SystemVerilog standard, I wanted to report the issue.
typedef_in_generate.sv.gz
Thank you !
Best regards
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