RP2350 datasheet: Size of XIP-cache SRAM instances

[maikmerten]

According to "Figure 18. core power domains" in the RP2350 datasheet, the XIP Cache SRAM is comprised of "(2 instances of 16 kB)".

Section 3.3 of the datasheet, however, reads more like this might me 2 instances of 8 kB:

A 16 kB on-chip cache retains the values of recent reads and writes. This reduces the chances that XIP bus accesses
must go to external memory, improving the average throughput and latency of the XIP interface. The cache is physically
structured as two 8 kB banks, interleaving odd and even cache lines of 8-byte granularity over the two banks.

I consider it likely that I misread things, but alternatively there might be an inconsistency in Figure 18? Or are there two separate 16kB XIP-caches (e.g., one for Flash, one for PSRAM?), each structured as two 8 kB banks?