Why SWCLK and SWD register of pads_bank0 is not modeled in hardware structure?

[oldoldman]

Hi guys,
From the rp2040 datasheet(page 300), there are 2 registers named SWCLK and SWD at the offset of PADS_BANK0_BASE+0x7C and PADS_BANK0_BASE+0x80, right after the register for GPIO29. But there is no place for SWCLK and SWD in pads_bank0_hw_t. In my understanding, either the sizeof pads_bank0_hw_t.io should be 32 or there should be 2 additional fields, for example,

typedef struct {
io_rw_32 voltage_select
io_rw_32 io[30];
io_rw_32 swclk;    // 
io_rw_32 swd;      //
} pads_bank0_hw_t;

How does this happen? Many thanks!

[lurch]

Those hardware_structs are autogenerated, so pinging @matiasilva

Interestingly, the "lower level" rp2040/hardware_regs/include/hardware/regs/pads_bank0.h (which is also autogenerated) does provide definitions for SWCLK and SWD.