The RISC-V Performance Analysis SIG drives the strategy and coordinates the development of end-to-end solutions for monitoring, reporting, and analyzing the performance of software executing on RISC-V systems. The group has governance for the software tools used in performance analysis, drives the outreach to upstream projects in this domain, and has the responsibility for ensuring that the necessary ISA and hardware mechanisms to enable these software tools are present in all existing and new RISC-V hardware specifications.
These performance analysis tools serve as the foundation for characterizing workloads, for assessing the performance of workloads on specific hardware and OS combinations, for evaluating micro-architectures, for tuning system configurations, and for directing compiler and software improvements.
The Performance Analysis SIG covers the following activities:
- Provides gap-analysis, strategy-development and outreach for Performance Analysis topics on behalf of the Software HC
- Maintains line-of-sight on RISC-V ecosystem needs for Performance Analysis tools and on upstream/external trends and developments in Performance Analysis
- Coordinates the porting of established Performance Analysis tools to the RISC-V ecosystem to reduce duplication of effort and fostering the collaboration on development activities
- Drives the outreach to external (Open-Source, Academic, and Commercial) projects addressing Performance Analysis for RISC-V and actively recruits partners to support RISC-V in their Performance Analysis tools
- Works with membership to establish guidelines and documentation for the effective use of Performance Analysis on RISC-V
- Provides Performance Analysis expertise to other specification efforts (e.g., SOC Infrastructure efforts, such as IOMMU and AIA) in RISC-V including early review of requirements and gap-analysis
- Collaborates with other RISC-V groups and committees regarding relevant gaps identified (e.g., with Priv IC on HPM ISA)