diff --git a/reri_header.adoc b/reri_header.adoc
index 7dfc46a..6edc9a5 100644
--- a/reri_header.adoc
+++ b/reri_header.adoc
@@ -1,9 +1,9 @@
 [[header]]
 :description: RISC-V RAS Error Record Register Interface Specification
 :company: RISC-V.org
-:revdate: 01/2024
-:revnumber: 1.0-rc1
-:revremark: This document is in stable state. Assume everything can change. See http://riscv.org/spec-state for details.
+:revdate: 02/2024
+:revnumber: 1.0-rc2
+:revremark: This document is in Frozen state. See http://riscv.org/spec-state for details.
 :url-riscv: http://riscv.org
 :doctype: book
 :preface-title: Preamble
@@ -39,12 +39,12 @@ RERI Task Group
 
 // Preamble
 [WARNING]
-.This document is in the link:http://riscv.org/spec-state[Stable state]
+.This document is in the link:http://riscv.org/spec-state[Frozen state]
 ====
-Assume anything could still change, but limited change should be expected.
-This draft specification will change before being accepted as standard, so
-implementations made to this draft specification will likely not conform to
-the future standard.
+Change is extremely unlikely. A high threshold will be used, and a change will
+only occur because of some truly critical issue being identified during the
+public review cycle. Any other desired or needed changes can be the subject of a
+follow-on new extension.
 ====
 
 [preface]