Acquire and release instructions have a bug

[AFOliveira]

Describe the bug
The bug is the aq/rl bit not correctly defined, its left empty in the encoding instead of being 0/1. This is due to my original parsing of instructions coming from riscv-opcodes db and not from the generated .json it creates.

I'm fixing this and I'll PR soon.

[AFOliveira]

Extending on this problem:

riscv-opcodes keeps acquire and release bits always as variable on atomic operations. This is compliant with the ISA standard description of this instructions:

However, LLVM is much more strict on these instructions, and separates them as, per example AMOADD.H - AQ/RL = 00 ---AMOADD.H.AQ - AQ/RL = 10 --- AMOADD.H.RL - AMOADD.H.RL = 01.

I think we could keep this as aq/rl variables for the purpose of the UDB being a DB and extend if we need, but since this caught my eye due to failing the #356 test, I want to ask for your opinion.