PLIC figure 2 clarifications

[IMG-S-Hopton]

Hi,

Could someone please clarify the following issues, which are not clear to me from the spec as-is:

Clarification 1 - Does interrupt priority 0 ('effectively' disabling the interrupt) prevent the interrupt source from showing in the claim register?

The claim register states that:

the claim operation is not affected by the setting of the priority threshold register

The interrupt priority register states that:

A priority value of 0 is reserved to mean ''never interrupt'' and effectively disables the interrupt

Figure 2 has the source interrupt priority AND'd with interrupt pending - but it is not entirely clear if this is meant to just gate priority when pending is not set, or if pending is also gated when priority is 0. I've seen this interpreted both ways.

Clarification 2 - Interrupt pending is per-source, but figure 2 has labelled the per-context EIP as "Interrupt Pending". Is the diagram wrong here, or is interrupt pending only meant to have bits set for interrupt sources which are being presented to the context?

From the wording of the spec I expect that the diagram is wrong, since the interrupt pending register specifically states:

A pending bit in the PLIC core can be cleared by setting the associated enable bit then performing a claim.

which implies that a pending bit can be seen without being enabled for a context.

Thanks!

[changab]

@IMG-S-Hopton

Clarification 1:

Does interrupt priority 0 ('effectively' disabling the interrupt) prevent the interrupt source from showing in the claim register?

Having the interrupt priority set to 0 disables the interrupt source (Source's IP AND Interrupt Priority).
While the interrupt threshold disables the interrupt to the target context however the interrupt pending bit is still visible to the target when the interrupt occurred. So, the claim operation is not affected by the setting of the priority threshold register.
See https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-claim-process

Clarification 2:

Is the diagram wrong here, or is interrupt pending only meant to have bits set for interrupt sources that are being presented to the context?

I think the figure just tries to delineate the EIP of the interrupt source that causes the external interrupt event to the target. It doesn't mean EIP is context-based.