mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode filtering for the cycle and instret counters, respectively.
| 63 | 62 | 61 | 60 | 59 | 58 | 57:0 |
|---|---|---|---|---|---|---|
0 |
MINH |
SINH |
UINH |
VSINH |
VUINH |
WPRI |
| Field | Description |
|---|---|
MINH |
If set, then counting of events in M-mode is inhibited |
SINH |
If set, then counting of events in S/HS-mode is inhibited |
UINH |
If set, then counting of events in U-mode is inhibited |
VSINH |
If set, then counting of events in VS-mode is inhibited |
VUINH |
If set, then counting of events in VU-mode is inhibited |
When all xINH bits are zero, event counting is enabled in all modes.
For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero. Bits 57:56 are reserved for possible future modes.
For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR.
The CSR numbers are 0x321 for mcyclecfg, 0x322 for minstretcfg, 0x721 for mcyclecfgh, and 0x722 for minstretcfgh.
The content of these registers may be accessible from Supervisor level if the Smcdeleg/Ssccfg extensions are implemented.
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Note
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The more natural CSR number for mcyclecfg would be 0x320, but that was allocated to mcountinhibit. This register format matches that specified for programmable counters by Sscofpmf. The bit position for the OF bit (bit 63) is read-only 0, since these counters do not generate local counter overflow interrupts on overflow. |