New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Renesas RX architecture support #24

Closed

XVilka opened this issue Dec 21, 2021 · 0 comments · Fixed by rizinorg/rizin#4198

Assignees

Labels

enhancement high-priority New Architecture

Member

XVilka commented Dec 21, 2021 •

edited

Loading

The RX microcontroller (MCU) family uses a 32-bit enhanced Harvard CISC architecture

https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rx-features
Renesas_RX63N_Chapter03_Slides_Ver0.1.pdf
RX Family RXv1 Instruction Set Architecture.pdf
RX Family RXv2 Instruction Set Architecture.pdf
RX Family RXv3 Instruction Set Architecture
Ghidra plugin

There is LLVM port for RX https://lists.llvm.org/pipermail/llvm-dev/2020-April/140546.html
Thus, it's theoretically possible to use the auto-sync procedure to add its support to capstone (see Tricore support in capstone as a good example).

It is also supported by QEMU: https://gitlab.com/qemu-project/qemu/-/tree/master/target/rx

XVilka assigned Heersin

Heersin mentioned this issue

Disassembler arch for RX microcontroller (MCU) family rizinorg/rizin#4198

Merged

10 tasks

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment