run

#!/bin/bash
# Copyright 2018 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.


# This is simple run script to run a dedicated test or a regression
#
# Usage:
# Run a single test with irun
# ./run -tool irun -test riscv_instr_base_test
#
# Run regression with vcs
# ./run -test all
#
# Change output directory
# ./run -out my_output_dir

DATE=`date +%Y-%m-%d`

# RTL simulator, supports vcs, irun, and questa
SIMULATOR="vcs"

# random seed
SEED=`date +%s`

# Test name, "all" means run all tests in the testlist
TEST="riscv_instr_base_test"

# Number of assembly programs to be generated for this test
# This option only apply to single test mode. For the regression mode, the number is specified in
# the testlist
NUM_TESTS=1

# Simulation output directory
OUT="./out_${DATE}"

# Simulation only
SIM_ONLY=0

# Compile only
CMP_ONLY=0

# Compile/run time options
SIM_OPTS=""
CMP_OPTS=""

# Verbose logging, by default disable detail logging
VERBOSE=0

# Submit to LSF
LSF_CMD="bsub"
LSF_OPTS=""
LSF=0
LSF_TIMEOUT=100

# Testlist for regression
TEST_LIST=testlist

# Process command line options
while [[ $# -gt 0 ]]
do
key="$1"
case $key in
    -tool)
    SIMULATOR="$2"
    shift
    ;;
    -test)
    TEST="$2"
    shift
    ;;
    -n)
    NUM_TESTS="$2"
    shift
    ;;
    -seed)
    SEED="$2"
    shift
    ;;
    -sim_opts)
    SIM_OPTS="$2"
    shift
    ;;
    -cmp_opts)
    CMP_OPTS="$2"
    shift
    ;;
    -testlist)
    TEST_LIST="$2"
    shift
    ;;
    -timeout)
    LSF_TIMEOUT="$2"
    shift
    ;;
    -so)
    SIM_ONLY=1
    ;;
    -verbose)
    VERBOSE=1
    ;;
    -co)
    CMP_ONLY=1
    ;;
    -lsf)
    LSF=1
    ;;
    -lsf_opts)
    LSF_OPTS="$2"
    shift
    ;;
    -o)
    OUT="$2"
    shift
    ;;
    *)
    echo "unknown option $1"
    exit 1
    ;;
esac
shift
done

if [[ $LSF == 0 ]]; then
  LSF_CMD=""
fi

OUT=`realpath ${OUT}`

# Generate compile and simulation commands
if [[ "$SIMULATOR" == "vcs" ]]; then

  function run_compile {
    vcs -file ./vcs.compile.option.f \
        -f ./files.f -full64 \
        -l $OUT/compile.log  \
        -Mdir=$OUT/vcs_simv.csrc \
        -o $OUT/vcs_simv ${CMP_OPTS}
  }

  SIM_CMD="$OUT/vcs_simv +vcs+lic+wait +UVM_TESTNAME="
  SIM_SEED="+ntb_random_seed="

elif [[ "$SIMULATOR" == "irun" ]]; then

  function run_compile {
    irun -64bit \
         -access +rwc \
         -f ./files.f \
         -q -sv -uvm  \
         -vlog_ext +.vh -I. \
         -uvmhome CDNS-1.2 \
         -elaborate \
         -l ${OUT}/compile.log ${CMP_OPTS}
    }

  SIM_CMD="irun -R +UVM_TESTNAME="
  SIM_SEED="-svseed "

elif [[ "$SIMULATOR" == "questa" ]]; then
#Questa requires mapping libraries to compile correctly
  function run_compile {
      vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2
      vlog -64 \
           -access=rwc \
           -f ./files.f \
           -sv \
           -mfcu -cuname design_cuname \
           +define+UVM_REGEX_NO_DPI \
           -writetoplevels ${OUT}/top.list \
           -l ${OUT}/compile.log ${CMP_OPTS}
      vopt -64 -debug \
           +designfile -f ${OUT}/top.list \
           -l ${OUT}/optimize.log ${CMP_OPTS} \
           -o design_opt
    }

  SIM_CMD="vsim -64 -c  -do questa_sim.tcl design_opt  +UVM_TESTNAME="
  SIM_SEED="-sv_seed "

else
  echo "unsupported simulator $SIMULATOR"
  exit 1
fi

# Clean up previous runs
if [[ $SIM_ONLY == 0 ]]; then
  rm -rf ${OUT}
else
  rm -rf ${OUT}/asm_tests
fi

mkdir -p ${OUT}
mkdir -p ${OUT}/asm_tests

# Compilation
if [[ $SIM_ONLY == 0 ]]; then
  echo "Building RISC-V instruction generator..."
  if [[ $VERBOSE == 1 ]]; then
    run_compile
  else
    run_compile > /dev/null
  fi
  echo "Building RISC-V instruction generator...done"
fi

# Skip simulation if compilation only flag is set
if [[ $CMP_ONLY == 1 ]]; then
  exit 0
fi

# Run sim
if [[ ${TEST} == "all" ]]; then
  echo "Running regression with testlist: $TEST_LIST"
  LOG_LIST="${OUT}/sim_log.list"
  PROGRAM_CNT=0
  cat "$TEST_LIST"
  rm -rf "$LOG_LIST"
  while read line; do
    if ! [[ $line =~ ^\/\/ ]]; then
      if [[ $line =~([a-z0-9_-]*)([[:space:]]*)\:([[:space:]]*)([0-9]*)([[:space:]]*)\:(.*$) ]]; then
        SEED=`date +%s`
        TEST=${BASH_REMATCH[1]}
        ITERATION=${BASH_REMATCH[4]}
        TEST_OPTS=${BASH_REMATCH[6]}
        if [[ ${ITERATION} != "0" ]]; then
          echo "Running ${TEST} to generate ${ITERATION} tests"
          CMD="${SIM_CMD}${TEST} +asm_file_name=${OUT}/asm_tests/${TEST} \
               ${SIM_SEED}${SEED} ${TEST_OPTS} ${SIM_OPTS} \
               -l ${OUT}/sim_${TEST}.log +num_of_tests=${ITERATION}"
          ((PROGRAM_CNT+=$ITERATION))
          echo "${OUT}/sim_${TEST}.log" >> ${LOG_LIST}
          if [[ $VERBOSE == 1 ]]; then
            ${LSF_CMD} ${LSF_OPTS} ${CMD}
          else
            ${LSF_CMD} ${LSF_OPTS} ${CMD} > /dev/null
          fi
        fi
      fi
    fi
  done < $TEST_LIST
  # Wait util all tests are generated
  if [[ $LSF == 1 ]]; then
    TIMEOUT_CNT=0
    TOTAL_CNT=`wc -l < ${LOG_LIST}`
    echo "Waiting for ${TOTAL_CNT} tests to complete, ${PROGRAM_CNT} programs to generate."
    while [[ 1 ]]; do
      COMPLETED_CNT=0
      while read log; do
        if [[ -f "$log" ]]; then
          if grep -q "TEST GENERATION DONE" $log; then
            ((COMPLETED_CNT+=1))
          else
            if [[ $VERBOSE == 1 ]]; then
              echo "$log is not completed"
            fi
          fi
        else
          if [[ $VERBOSE == 1 ]]; then
            echo "$log is not completed"
          fi
        fi
      done < ${LOG_LIST}
      GENERATED_CNT=`find ${OUT}/asm_tests/ -name "*.S" | wc -l`
      echo "[$TIMEOUT_CNT] Progress > Test:${COMPLETED_CNT}/${TOTAL_CNT} Program:${GENERATED_CNT}/${PROGRAM_CNT}"
      if [[ "$COMPLETED_CNT" == "$TOTAL_CNT" ]]; then
        break
      else
        if [[ "$TIMEOUT_CNT" == "$LSF_TIMEOUT" ]]; then
          echo "Generator timeout after $LSF_TIMEOUT * 10 seconds"
          break
        else
          sleep 10
        fi
      fi
      ((TIMEOUT_CNT+=1))
    done
  fi
else
  echo "Running test ${TEST} to generate ${NUM_TESTS} tests"
  CMD="${SIM_CMD}${TEST} +asm_file_name=${OUT}/asm_tests/${TEST} \
                    ${SIM_SEED}${SEED} \
                    -l ${OUT}/sim_${TEST}.log \
                    +num_of_tests=${NUM_TESTS} ${SIM_OPTS}"
  if [[ $VERBOSE == 1 ]]; then
    ${CMD}
  else
    ${CMD} > /dev/null
  fi
fi


# List all generated assembly tests
echo "==========================================================="
echo "                Generated RISC-V assembly tests"
echo " ----------------------------------------------------------"
find $OUT/asm_tests -name "*.S" | sort -k11