A set of utilities that can be used to develop digital IPs in Verilog HDL. This includes:
- Code Generators based on IP definition in YAML or JSON
- Bus wrapper Verilog RTL for AMBA AHB lite and APB.
- A testbech template in Verilog for the IP.
- C header file that contains the I/O register definitions.
- IP documentation in Markdown format.
- RTL Library of Components
- Verification Infrastructure