From b2e314e2773b6caf101941f5b0dd221c1a7e53bd Mon Sep 17 00:00:00 2001 From: Mohamed Shalan Date: Tue, 20 Feb 2024 17:44:19 +0200 Subject: [PATCH] Update aucohl_lib.v Fixed a bug that prevented a clock divisor of 2. --- rtl/aucohl_lib.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/aucohl_lib.v b/rtl/aucohl_lib.v index a7479c1..4010662 100644 --- a/rtl/aucohl_lib.v +++ b/rtl/aucohl_lib.v @@ -87,7 +87,7 @@ module aucohl_ticker #(parameter W=8) ( else counter <= counter - 'b1; - assign tick_w = (clk_div == 'b1) ? 1'b1 : counter_is_zero; + assign tick_w = (clk_div == 'b0) ? 1'b1 : counter_is_zero; always @(posedge clk or negedge rst_n) if(!rst_n)