demo.xml

<?xml version="1.0" encoding="utf-8"?>
<architecture>
	<models>
		<model name="multiply">
			<input_ports>
				<port combinational_sink_ports="out" name="a"/>
				<port combinational_sink_ports="out" name="b"/>
			</input_ports>
			<output_ports>
				<port name="out"/>
			</output_ports>
		</model>
		<model name="single_port_ram">
			<input_ports>
				<port clock="clk" name="we"/>
				<port clock="clk" name="addr"/>
				<port clock="clk" name="data"/>
				<port is_clock="1" name="clk"/>
			</input_ports>
			<output_ports>
				<port clock="clk" name="out"/>
			</output_ports>
		</model>
		<model name="dual_port_ram">
			<input_ports>
				<port clock="clk" name="we1"/>
				<port clock="clk" name="we2"/>
				<port clock="clk" name="addr1"/>
				<port clock="clk" name="addr2"/>
				<port clock="clk" name="data1"/>
				<port clock="clk" name="data2"/>
				<port is_clock="1" name="clk"/>
			</input_ports>
			<output_ports>
				<port clock="clk" name="out1"/>
				<port clock="clk" name="out2"/>
			</output_ports>
		</model>
	</models>
	<tiles>
		<tile capacity="8" name="io">
			<equivalent_sites>
				<site pb_type="io"/>
			</equivalent_sites>
			<input name="outpad" num_pins="1"/>
			<output name="inpad" num_pins="1"/>
			<clock name="clock" num_pins="1"/>
			<fc in_type="frac" in_val="0.025 0.025 0.025 0.025" out_type="frac" out_val="0.05 0.05 0.05 0.05"/>
			<pinlocations pattern="custom">
				<loc side="left">io.outpad io.inpad io.clock</loc>
				<loc side="top">io.outpad io.inpad io.clock</loc>
				<loc side="right">io.outpad io.inpad io.clock</loc>
				<loc side="bottom">io.outpad io.inpad io.clock</loc>
			</pinlocations>
		</tile>
		<tile name="clb">
			<equivalent_sites>
				<site pb_type="clb"/>
			</equivalent_sites>
			<input equivalent="full" name="I1" num_pins="10"/>
			<input equivalent="full" name="I2" num_pins="10"/>
			<input equivalent="full" name="I3" num_pins="10"/>
			<input equivalent="full" name="I4" num_pins="10"/>
			<output equivalent="full" name="O1" num_pins="2"/>
			<output equivalent="full" name="O2" num_pins="2"/>
			<output equivalent="full" name="O3" num_pins="2"/>
			<output equivalent="full" name="O4" num_pins="2"/>
			<output equivalent="full" name="O5" num_pins="2"/>
			<output equivalent="full" name="O6" num_pins="2"/>
			<output equivalent="full" name="O7" num_pins="2"/>
			<output equivalent="full" name="O8" num_pins="2"/>
			<output equivalent="full" name="O9" num_pins="2"/>
			<output equivalent="full" name="O10" num_pins="2"/>
			<clock name="clk" num_pins="1"/>
			<fc in_type="frac" in_val="0.025 0.025 0.025 0.025" out_type="frac" out_val="0.05 0.05 0.05 0.05"/>
			<pinlocations pattern="spread"/>
		</tile>
		</tile>
		<tile height="4" name="mult_36">
			<equivalent_sites>
				<site pb_type="mult_36"/>
			</equivalent_sites>
			<input name="a" num_pins="36"/>
			<input name="b" num_pins="36"/>
			<output name="out" num_pins="72"/>
			<fc in_type="frac" in_val="0.025 0.025 0.025 0.025" out_type="frac" out_val="0.05 0.05 0.05 0.05"/>
			<pinlocations pattern="spread"/>
		</tile>
		<tile height="6" name="memory">
			<equivalent_sites>
				<site pb_type="memory"/>
			</equivalent_sites>
			<input name="addr1" num_pins="15"/>
			<input name="addr2" num_pins="15"/>
			<input name="data" num_pins="64"/>
			<input name="we1" num_pins="1"/>
			<input name="we2" num_pins="1"/>
			<output name="out" num_pins="64"/>
			<clock name="clk" num_pins="1"/>
			<fc in_type="frac" in_val="0.025 0.025 0.025 0.025" out_type="frac" out_val="0.05 0.05 0.05 0.05"/>
			<pinlocations pattern="spread"/>
		</tile>
	</tiles>
	<layout>
		<auto_layout aspect_ratio="1.0">
			<perimeter priority="100" type="io"/>
			<corners priority="101" type="EMPTY"/>
			<fill priority="10" type="clb"/>
			<col priority="20" repeatx="8" startx="4" starty="1" type="mult_36"/>
			<col priority="19" repeatx="8" startx="4" starty="1" type="EMPTY"/>
			<col priority="20" repeatx="8" startx="2" starty="1" type="memory"/>
			<col priority="19" repeatx="8" startx="2" starty="1" type="EMPTY"/>
		</auto_layout>
	</layout>
	<device>
		<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>
		<area grid_logic_tile_area="15009.2078955"/>
		<chan_width_distr>
			<x distr="uniform" peak="1.000000"/>
			<y distr="uniform" peak="1.000000"/>
		</chan_width_distr>
		<switch_block fs="3" type="wilton"/>
		<neighbor_interconnect fn="3">
		<connection_block input_switch_name="ipin_cblock"/>
	</device>
	<switchlist>
		<switch Cin="0.000000e+00" Cout="0.000000e+00" R="0.000000" Tdel="1.424e-10" buf_size="25.5612499137" mux_trans_size="1.50823186576" name="0" type="mux"/>
		<switch Cin="0.000000e+00" Cout="0.000000e+00" R="0.000000" Tdel="9.188e-11" buf_size="11.1319292469" mux_trans_size="1.25595750289" name="ipin_cblock" type="mux"/>

	</switchlist>
	<complexblocklist>
		<pb_type name="io">
			<input name="outpad" num_pins="1"/>
			<output name="inpad" num_pins="1"/>
			<clock name="clock" num_pins="1"/>
			<mode name="inpad">
				<pb_type blif_model=".input" name="inpad" num_pb="1">
					<output name="inpad" num_pins="1"/>
				</pb_type>
				<interconnect>
					<direct input="inpad.inpad" name="inpad" output="io.inpad">
						<delay_constant in_port="inpad.inpad" max="4.243e-11" out_port="io.inpad"/>
					</direct>
				</interconnect>
			</mode>
			<mode name="outpad">
				<pb_type blif_model=".output" name="outpad" num_pb="1">
					<input name="outpad" num_pins="1"/>
				</pb_type>
				<interconnect>
					<direct input="io.outpad" name="outpad" output="outpad.outpad">
						<delay_constant in_port="io.outpad" max="1.394e-11" out_port="outpad.outpad"/>
					</direct>
				</interconnect>
			</mode>
		</pb_type>
		<pb_type name="clb">
			<input equivalent="full" name="I1" num_pins="10"/>
			<input equivalent="full" name="I2" num_pins="10"/>
			<input equivalent="full" name="I3" num_pins="10"/>
			<input equivalent="full" name="I4" num_pins="10"/>
			<output equivalent="full" name="O1" num_pins="2"/>
			<output equivalent="full" name="O2" num_pins="2"/>
			<output equivalent="full" name="O3" num_pins="2"/>
			<output equivalent="full" name="O4" num_pins="2"/>
			<output equivalent="full" name="O5" num_pins="2"/>
			<output equivalent="full" name="O6" num_pins="2"/>
			<output equivalent="full" name="O7" num_pins="2"/>
			<output equivalent="full" name="O8" num_pins="2"/>
			<output equivalent="full" name="O9" num_pins="2"/>
			<output equivalent="full" name="O10" num_pins="2"/>
			<clock name="clk" num_pins="1"/>
			<pb_type name="fle" num_pb="10">
				<input name="in_A" num_pins="1"/>
				<input name="in_B" num_pins="1"/>
				<input name="in_C" num_pins="1"/>
				<input name="in_D" num_pins="1"/>
				<input name="in_E" num_pins="1"/>
				<input name="in_F" num_pins="1"/>
				<output name="out_local" num_pins="2"/>
				<output name="out_routing" num_pins="2"/>
				<clock name="clk" num_pins="1"/>
				<mode name="n1_lut6">
					<pb_type name="ble6" num_pb="1">
						<input name="in_A" num_pins="1"/>
						<input name="in_B" num_pins="1"/>
						<input name="in_C" num_pins="1"/>
						<input name="in_D" num_pins="1"/>
						<input name="in_E" num_pins="1"/>
						<input name="in_F" num_pins="1"/>
						<output name="out_local" num_pins="1"/>
						<output name="out_routing" num_pins="2"/>
						<clock name="clk" num_pins="1"/>
						<pb_type blif_model=".names" class="lut" name="lut6" num_pb="1">
							<input name="in" num_pins="6" port_class="lut_in"/>
							<output name="out" num_pins="1" port_class="lut_out"/>
							<delay_matrix in_port="lut6.in" out_port="lut6.out" type="max">
     0
     0
     0
     0
     0
     0
  </delay_matrix>
						</pb_type>
						<pb_type blif_model=".latch" class="flipflop" name="ff" num_pb="1">
							<input name="D" num_pins="1" port_class="D"/>
							<output name="Q" num_pins="1" port_class="Q"/>
							<clock name="clk" num_pins="1" port_class="clock"/>
							<T_setup clock="clk" port="ff.D" value="1.891e-11"/>
							<T_clock_to_Q clock="clk" max="6.032e-11" port="ff.Q"/>
						</pb_type>
						<interconnect>
							<direct input="ble6.in_A" name="direct0" output="lut6.in[0:0]">
								<delay_constant in_port="ble6.in_A" max="2.3877e-10" out_port="lut6.in[0:0]"/>
							</direct>
							<direct input="ble6.in_B" name="direct1" output="lut6.in[1:1]">
								<delay_constant in_port="ble6.in_B" max="2.3773e-10" out_port="lut6.in[1:1]"/>
							</direct>
							<direct input="ble6.in_D" name="direct3" output="lut6.in[3:3]">
								<delay_constant in_port="ble6.in_D" max="1.4124e-10" out_port="lut6.in[3:3]"/>
							</direct>
							<direct input="ble6.in_E" name="direct4" output="lut6.in[4:4]">
								<delay_constant in_port="ble6.in_E" max="1.4482e-10" out_port="lut6.in[4:4]"/>
							</direct>
							<direct input="ble6.in_F" name="direct5" output="lut6.in[5:5]">
								<delay_constant in_port="ble6.in_F" max="1.2502e-10" out_port="lut6.in[5:5]"/>
							</direct>
							<direct input="ble6.clk" name="direct6" output="ff.clk"/>
							<mux input="ble6.in_C ff.Q" name="mux1" output="lut6.in[2:2]">
								<delay_constant in_port="ble6.in_C" max="2.2693e-10" out_port="lut6.in[2:2]"/>
								<delay_constant in_port="ff.Q" max="2.2693e-10" out_port="lut6.in[2:2]"/>
							</mux>
							<mux input="lut6.out ble6.in_C" name="2" output="ff.D">
								<delay_constant in_port="lut6.out" max="1.74588e-11" out_port="ff.D"/>
								<delay_constant in_port="ble6.in_C" max="1.74588e-11" out_port="ff.D"/>
							</mux>
							<mux input="ff.Q lut6.out" name="mux3" output="ble6.out_local">
								<delay_constant in_port="ff.Q" max="1.094e-10" out_port="ble6.out_local"/>
								<delay_constant in_port="lut6.out" max="1.094e-10" out_port="ble6.out_local"/>
							</mux>
							<mux input="ff.Q lut6.out" name="mux4" output="ble6.out_routing[0:0]">
								<delay_constant in_port="ff.Q" max="3.866e-11" out_port="ble6.out_routing[0:0]"/>
								<delay_constant in_port="lut6.out" max="3.866e-11" out_port="ble6.out_routing[0:0]"/>
							</mux>
							<mux input="ff.Q lut6.out" name="mux5" output="ble6.out_routing[1:1]">
								<delay_constant in_port="ff.Q" max="3.866e-11" out_port="ble6.out_routing[1:1]"/>
								<delay_constant in_port="lut6.out" max="3.866e-11" out_port="ble6.out_routing[1:1]"/>
							</mux>
						</interconnect>
					</pb_type>
					<interconnect>
						<direct input="fle.in_A" name="direct1" output="ble6.in_A"/>
						<direct input="fle.in_B" name="direct2" output="ble6.in_B"/>
						<direct input="fle.in_C" name="direct3" output="ble6.in_C"/>
						<direct input="fle.in_D" name="direct4" output="ble6.in_D"/>
						<direct input="fle.in_E" name="direct5" output="ble6.in_E"/>
						<direct input="fle.in_F" name="direct6" output="ble6.in_F"/>
						<direct input="ble6.out_local" name="direct7" output="fle.out_local[0:0]"/>
						<direct input="ble6.out_routing" name="direct8" output="fle.out_routing"/>
						<direct input="fle.clk" name="direct9" output="ble6.clk"/>
					</interconnect>
				</mode>
				<mode name="n2_lut5">
					<pb_type name="lut5inter" num_pb="1">
						<input name="in_A" num_pins="1"/>
						<input name="in_B" num_pins="1"/>
						<input name="in_C" num_pins="1"/>
						<input name="in_D" num_pins="1"/>
						<input name="in_E" num_pins="1"/>
						<output name="out_local" num_pins="2"/>
						<output name="out_routing" num_pins="2"/>
						<clock name="clk" num_pins="1"/>
						<pb_type name="ble5" num_pb="2">
							<input name="in_A" num_pins="1"/>
							<input name="in_B" num_pins="1"/>
							<input name="in_C" num_pins="1"/>
							<input name="in_D" num_pins="1"/>
							<input name="in_E" num_pins="1"/>
							<output name="out_local" num_pins="1"/>
							<output name="out_routing" num_pins="1"/>
							<clock name="clk" num_pins="1"/>
							<pb_type blif_model=".names" class="lut" name="lut5" num_pb="1">
								<input name="in" num_pins="5" port_class="lut_in"/>
								<output name="out" num_pins="1" port_class="lut_out"/>
								<delay_matrix in_port="lut5.in" out_port="lut5.out" type="max">
     0
     0
     0
     0
     0
  </delay_matrix>
							</pb_type>
							<pb_type blif_model=".latch" class="flipflop" name="ff" num_pb="1">
								<input name="D" num_pins="1" port_class="D"/>
								<output name="Q" num_pins="1" port_class="Q"/>
								<clock name="clk" num_pins="1" port_class="clock"/>
								<T_setup clock="clk" port="ff.D" value="1.891e-11"/>
								<T_clock_to_Q clock="clk" max="6.032e-11" port="ff.Q"/>
							</pb_type>
							<interconnect>
								<direct input="ble5.in_A" name="direct0" output="lut5.in[0:0]">
									<delay_constant in_port="ble5.in_A" max="2.3877e-10" out_port="lut5.in[0:0]"/>
								</direct>
								<direct input="ble5.in_B" name="direct1" output="lut5.in[1:1]">
									<delay_constant in_port="ble5.in_B" max="2.3773e-10" out_port="lut5.in[1:1]"/>
								</direct>
								<direct input="ble5.in_D" name="direct3" output="lut5.in[3:3]">
									<delay_constant in_port="ble5.in_D" max="1.4124e-10" out_port="lut5.in[3:3]"/>
								</direct>
								<direct input="ble5.in_E" name="direct4" output="lut5.in[4:4]">
									<delay_constant in_port="ble5.in_E" max="1.4482e-10" out_port="lut5.in[4:4]"/>
								</direct>
								<direct input="ble5.clk" name="direct5" output="ff.clk"/>
								<mux input="ble5.in_C ff.Q" name="mux1" output="lut5.in[2:2]">
									<delay_constant in_port="ble5.in_C" max="2.2693e-10" out_port="lut5.in[2:2]"/>
									<delay_constant in_port="ff.Q" max="2.2693e-10" out_port="lut5.in[2:2]"/>
								</mux>
								<mux input="lut5.out ble5.in_C" name="2" output="ff.D">
									<delay_constant in_port="lut5.out" max="1.74588e-11" out_port="ff.D"/>
									<delay_constant in_port="ble5.in_C" max="1.74588e-11" out_port="ff.D"/>
								</mux>
								<mux input="ff.Q lut5.out" name="mux3" output="ble5.out_local">
									<delay_constant in_port="ff.Q" max="1.094e-10" out_port="ble5.out_local"/>
									<delay_constant in_port="lut5.out" max="1.094e-10" out_port="ble5.out_local"/>
								</mux>
								<mux input="ff.Q lut5.out" name="mux4" output="ble5.out_routing[0:0]">
									<delay_constant in_port="ff.Q" max="3.866e-11" out_port="ble5.out_routing[0:0]"/>
									<delay_constant in_port="lut5.out" max="3.866e-11" out_port="ble5.out_routing[0:0]"/>
								</mux>
							</interconnect>
						</pb_type>
						<interconnect>
							<direct input="lut5inter.in_A" name="direct1" output="ble5[0:0].in_A"/>
							<direct input="lut5inter.in_B" name="direct2" output="ble5[0:0].in_B"/>
							<direct input="lut5inter.in_C" name="direct3" output="ble5[0:0].in_C"/>
							<direct input="lut5inter.in_D" name="direct4" output="ble5[0:0].in_D"/>
							<direct input="lut5inter.in_E" name="direct5" output="ble5[0:0].in_E"/>
							<direct input="lut5inter.in_A" name="direct6" output="ble5[1:1].in_A"/>
							<direct input="lut5inter.in_B" name="direct7" output="ble5[1:1].in_B"/>
							<direct input="lut5inter.in_C" name="direct8" output="ble5[1:1].in_C"/>
							<direct input="lut5inter.in_D" name="direct9" output="ble5[1:1].in_D"/>
							<direct input="lut5inter.in_E" name="direct10" output="ble5[1:1].in_E"/>
							<direct input="ble5[1:0].out_local" name="direct11" output="lut5inter.out_local"/>
							<direct input="ble5[1:0].out_routing" name="direct12" output="lut5inter.out_routing"/>
							<complete input="lut5inter.clk" name="complete1" output="ble5[1:0].clk"/>
						</interconnect>
					</pb_type>
					<interconnect>
						<direct input="fle.in_A" name="direct1" output="lut5inter.in_A"/>
						<direct input="fle.in_B" name="direct2" output="lut5inter.in_B"/>
						<direct input="fle.in_C" name="direct3" output="lut5inter.in_C"/>
						<direct input="fle.in_D" name="direct4" output="lut5inter.in_D"/>
						<direct input="fle.in_E" name="direct5" output="lut5inter.in_E"/>
						<direct input="lut5inter.out_local" name="direct7" output="fle.out_local"/>
						<direct input="lut5inter.out_routing" name="direct8" output="fle.out_routing"/>
						<direct input="fle.clk" name="direct9" output="lut5inter.clk"/>
					</interconnect>
				</mode>
			</pb_type>
			<interconnect>
				<complete input="clb.I4 clb.I3 fle[1:0].out_local fle[3:2].out_local fle[8:8].out_local" name="lutA" output="fle[9:0].in_A">
					<delay_constant in_port="clb.I4" max="6.295e-11" out_port="fle.in_A"/>
					<delay_constant in_port="clb.I3" max="6.295e-11" out_port="fle.in_A"/>
				</complete>
				<complete input="clb.I3 clb.I2 fle[3:2].out_local fle[5:4].out_local fle[9:9].out_local" name="lutB" output="fle[9:0].in_B">
					<delay_constant in_port="clb.I3" max="6.295e-11" out_port="fle.in_B"/>
					<delay_constant in_port="clb.I2" max="6.295e-11" out_port="fle.in_B"/>
				</complete>
				<complete input="clb.I2 clb.I1 fle[5:4].out_local fle[7:6].out_local fle[8:8].out_local" name="lutC" output="fle[9:0].in_C">
					<delay_constant in_port="clb.I2" max="6.295e-11" out_port="fle.in_C"/>
					<delay_constant in_port="clb.I1" max="6.295e-11" out_port="fle.in_C"/>
				</complete>
				<complete input="clb.I4 clb.I2 fle[1:0].out_local fle[5:4].out_local fle[9:9].out_local" name="lutD" output="fle[9:0].in_D">
					<delay_constant in_port="clb.I4" max="6.295e-11" out_port="fle.in_D"/>
					<delay_constant in_port="clb.I2" max="6.295e-11" out_port="fle.in_D"/>
				</complete>
				<complete input="clb.I3 clb.I1 fle[3:2].out_local fle[7:6].out_local fle[8:8].out_local" name="lutE" output="fle[9:0].in_E">
					<delay_constant in_port="clb.I3" max="6.295e-11" out_port="fle.in_E"/>
					<delay_constant in_port="clb.I1" max="6.295e-11" out_port="fle.in_E"/>
				</complete>
				<complete input="clb.I4 clb.I1 fle[1:0].out_local fle[7:6].out_local fle[9:9].out_local" name="lutF" output="fle[9:0].in_F">
					<delay_constant in_port="clb.I4" max="6.295e-11" out_port="fle.in_F"/>
					<delay_constant in_port="clb.I1" max="6.295e-11" out_port="fle.in_F"/>
				</complete>
				<complete input="clb.clk" name="clks" output="fle[9:0].clk"/>
				<direct input="fle[0:0].out_routing" name="clbouts1" output="clb.O1"/>
				<direct input="fle[1:1].out_routing" name="clbouts2" output="clb.O2"/>
				<direct input="fle[2:2].out_routing" name="clbouts3" output="clb.O3"/>
				<direct input="fle[3:3].out_routing" name="clbouts4" output="clb.O4"/>
				<direct input="fle[4:4].out_routing" name="clbouts5" output="clb.O5"/>
				<direct input="fle[5:5].out_routing" name="clbouts6" output="clb.O6"/>
				<direct input="fle[6:6].out_routing" name="clbouts7" output="clb.O7"/>
				<direct input="fle[7:7].out_routing" name="clbouts8" output="clb.O8"/>
				<direct input="fle[8:8].out_routing" name="clbouts9" output="clb.O9"/>
				<direct input="fle[9:9].out_routing" name="clbouts10" output="clb.O10"/>
			</interconnect>
		</pb_type>
		<pb_type name="mult_36">
			<input name="a" num_pins="36"/>
			<input name="b" num_pins="36"/>
			<output name="out" num_pins="72"/>
			<mode name="two_divisible_mult_18x18">
				<pb_type name="divisible_mult_18x18" num_pb="2">
					<input name="a" num_pins="18"/>
					<input name="b" num_pins="18"/>
					<output name="out" num_pins="36"/>
					<mode name="two_mult_9x9">
						<pb_type name="mult_9x9_slice" num_pb="2">
							<input name="A_cfg" num_pins="9"/>
							<input name="B_cfg" num_pins="9"/>
							<output name="OUT_cfg" num_pins="18"/>
							<pb_type blif_model=".subckt multiply" name="mult_9x9" num_pb="1">
								<input name="a" num_pins="9"/>
								<input name="b" num_pins="9"/>
								<output name="out" num_pins="18"/>
								<delay_constant in_port="mult_9x9.a" max="1.667e-9" out_port="mult_9x9.out"/>
								<delay_constant in_port="mult_9x9.b" max="1.667e-9" out_port="mult_9x9.out"/>
							</pb_type>
							<interconnect>
								<direct input="mult_9x9_slice.A_cfg" name="a2a" output="mult_9x9.a"/>
								<direct input="mult_9x9_slice.B_cfg" name="b2b" output="mult_9x9.b"/>
								<direct input="mult_9x9.out" name="out2out" output="mult_9x9_slice.OUT_cfg"/>
							</interconnect>
						</pb_type>
						<interconnect>
							<direct input="divisible_mult_18x18.a" name="a2a" output="mult_9x9_slice[1:0].A_cfg"/>
							<direct input="divisible_mult_18x18.b" name="b2b" output="mult_9x9_slice[1:0].B_cfg"/>
							<direct input="mult_9x9_slice[1:0].OUT_cfg" name="out2out" output="divisible_mult_18x18.out"/>
						</interconnect>
					</mode>
					<mode name="mult_18x18">
						<pb_type name="mult_18x18_slice" num_pb="1">
							<input name="A_cfg" num_pins="18"/>
							<input name="B_cfg" num_pins="18"/>
							<output name="OUT_cfg" num_pins="36"/>
							<pb_type blif_model=".subckt multiply" name="mult_18x18" num_pb="1">
								<input name="a" num_pins="18"/>
								<input name="b" num_pins="18"/>
								<output name="out" num_pins="36"/>
								<delay_constant in_port="mult_18x18.a" max="1.667e-9" out_port="mult_18x18.out"/>
								<delay_constant in_port="mult_18x18.b" max="1.667e-9" out_port="mult_18x18.out"/>
							</pb_type>
							<interconnect>
								<direct input="mult_18x18_slice.A_cfg" name="a2a" output="mult_18x18.a"/>
								<direct input="mult_18x18_slice.B_cfg" name="b2b" output="mult_18x18.b"/>
								<direct input="mult_18x18.out" name="out2out" output="mult_18x18_slice.OUT_cfg"/>
							</interconnect>
						</pb_type>
						<interconnect>
							<direct input="divisible_mult_18x18.a" name="a2a" output="mult_18x18_slice.A_cfg"/>
							<direct input="divisible_mult_18x18.b" name="b2b" output="mult_18x18_slice.B_cfg"/>
							<direct input="mult_18x18_slice.OUT_cfg" name="out2out" output="divisible_mult_18x18.out"/>
						</interconnect>
					</mode>
				</pb_type>
				<interconnect>
					<direct input="mult_36.a" name="a2a" output="divisible_mult_18x18[1:0].a"/>
					<direct input="mult_36.b" name="b2b" output="divisible_mult_18x18[1:0].b"/>
					<direct input="divisible_mult_18x18[1:0].out" name="out2out" output="mult_36.out"/>
				</interconnect>
			</mode>
			<mode name="mult_36x36">
				<pb_type name="mult_36x36_slice" num_pb="1">
					<input name="A_cfg" num_pins="36"/>
					<input name="B_cfg" num_pins="36"/>
					<output name="OUT_cfg" num_pins="72"/>
					<pb_type blif_model=".subckt multiply" name="mult_36x36" num_pb="1">
						<input name="a" num_pins="36"/>
						<input name="b" num_pins="36"/>
						<output name="out" num_pins="72"/>
						<delay_constant in_port="mult_36x36.a" max="1.667e-9" out_port="mult_36x36.out"/>
						<delay_constant in_port="mult_36x36.b" max="1.667e-9" out_port="mult_36x36.out"/>
					</pb_type>
					<interconnect>
						<direct input="mult_36x36_slice.A_cfg" name="a2a" output="mult_36x36.a"/>
						<direct input="mult_36x36_slice.B_cfg" name="b2b" output="mult_36x36.b"/>
						<direct input="mult_36x36.out" name="out2out" output="mult_36x36_slice.OUT_cfg"/>
					</interconnect>
				</pb_type>
				<interconnect>
					<direct input="mult_36.a" name="a2a" output="mult_36x36_slice.A_cfg"/>
					<direct input="mult_36.b" name="b2b" output="mult_36x36_slice.B_cfg"/>
					<direct input="mult_36x36_slice.OUT_cfg" name="out2out" output="mult_36.out"/>
				</interconnect>
			</mode>
		</pb_type>
		<pb_type name="memory">
			<input name="addr1" num_pins="15"/>
			<input name="addr2" num_pins="15"/>
			<input name="data" num_pins="64"/>
			<input name="we1" num_pins="1"/>
			<input name="we2" num_pins="1"/>
			<output name="out" num_pins="64"/>
			<clock name="clk" num_pins="1"/>
			<mode name="mem_512x64_sp">
				<pb_type blif_model=".subckt single_port_ram" class="memory" name="mem_512x64_sp" num_pb="1">
					<input name="addr" num_pins="9" port_class="address"/>
					<input name="data" num_pins="64" port_class="data_in"/>
					<input name="we" num_pins="1" port_class="write_en"/>
					<output name="out" num_pins="64" port_class="data_out"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_512x64_sp.addr" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_512x64_sp.data" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_512x64_sp.we" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_512x64_sp.out"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[8:0]" name="address1" output="mem_512x64_sp.addr"/>
					<direct input="memory.data[63:0]" name="data1" output="mem_512x64_sp.data"/>
					<direct input="memory.we1" name="writeen1" output="mem_512x64_sp.we"/>
					<direct input="mem_512x64_sp.out" name="dataout1" output="memory.out[63:0]"/>
					<direct input="memory.clk" name="clk" output="mem_512x64_sp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_1024x32_sp">
				<pb_type blif_model=".subckt single_port_ram" class="memory" name="mem_1024x32_sp" num_pb="1">
					<input name="addr" num_pins="10" port_class="address"/>
					<input name="data" num_pins="32" port_class="data_in"/>
					<input name="we" num_pins="1" port_class="write_en"/>
					<output name="out" num_pins="32" port_class="data_out"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_1024x32_sp.addr" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_1024x32_sp.data" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_1024x32_sp.we" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_1024x32_sp.out"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[9:0]" name="address1" output="mem_1024x32_sp.addr"/>
					<direct input="memory.data[31:0]" name="data1" output="mem_1024x32_sp.data"/>
					<direct input="memory.we1" name="writeen1" output="mem_1024x32_sp.we"/>
					<direct input="mem_1024x32_sp.out" name="dataout1" output="memory.out[31:0]"/>
					<direct input="memory.clk" name="clk" output="mem_1024x32_sp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_2048x16_sp">
				<pb_type blif_model=".subckt single_port_ram" class="memory" name="mem_2048x16_sp" num_pb="1">
					<input name="addr" num_pins="11" port_class="address"/>
					<input name="data" num_pins="16" port_class="data_in"/>
					<input name="we" num_pins="1" port_class="write_en"/>
					<output name="out" num_pins="16" port_class="data_out"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_2048x16_sp.addr" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x16_sp.data" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x16_sp.we" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_2048x16_sp.out"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[10:0]" name="address1" output="mem_2048x16_sp.addr"/>
					<direct input="memory.data[15:0]" name="data1" output="mem_2048x16_sp.data"/>
					<direct input="memory.we1" name="writeen1" output="mem_2048x16_sp.we"/>
					<direct input="mem_2048x16_sp.out" name="dataout1" output="memory.out[15:0]"/>
					<direct input="memory.clk" name="clk" output="mem_2048x16_sp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_4096x8_sp">
				<pb_type blif_model=".subckt single_port_ram" class="memory" name="mem_4096x8_sp" num_pb="1">
					<input name="addr" num_pins="12" port_class="address"/>
					<input name="data" num_pins="8" port_class="data_in"/>
					<input name="we" num_pins="1" port_class="write_en"/>
					<output name="out" num_pins="8" port_class="data_out"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_4096x8_sp.addr" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_4096x8_sp.data" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_4096x8_sp.we" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_4096x8_sp.out"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[11:0]" name="address1" output="mem_4096x8_sp.addr"/>
					<direct input="memory.data[7:0]" name="data1" output="mem_4096x8_sp.data"/>
					<direct input="memory.we1" name="writeen1" output="mem_4096x8_sp.we"/>
					<direct input="mem_4096x8_sp.out" name="dataout1" output="memory.out[7:0]"/>
					<direct input="memory.clk" name="clk" output="mem_4096x8_sp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_8192x4_sp">
				<pb_type blif_model=".subckt single_port_ram" class="memory" name="mem_8192x4_sp" num_pb="1">
					<input name="addr" num_pins="13" port_class="address"/>
					<input name="data" num_pins="4" port_class="data_in"/>
					<input name="we" num_pins="1" port_class="write_en"/>
					<output name="out" num_pins="4" port_class="data_out"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_8192x4_sp.addr" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_8192x4_sp.data" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_8192x4_sp.we" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_8192x4_sp.out"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[12:0]" name="address1" output="mem_8192x4_sp.addr"/>
					<direct input="memory.data[3:0]" name="data1" output="mem_8192x4_sp.data"/>
					<direct input="memory.we1" name="writeen1" output="mem_8192x4_sp.we"/>
					<direct input="mem_8192x4_sp.out" name="dataout1" output="memory.out[3:0]"/>
					<direct input="memory.clk" name="clk" output="mem_8192x4_sp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_16384x2_sp">
				<pb_type blif_model=".subckt single_port_ram" class="memory" name="mem_16384x2_sp" num_pb="1">
					<input name="addr" num_pins="14" port_class="address"/>
					<input name="data" num_pins="2" port_class="data_in"/>
					<input name="we" num_pins="1" port_class="write_en"/>
					<output name="out" num_pins="2" port_class="data_out"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_16384x2_sp.addr" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_16384x2_sp.data" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_16384x2_sp.we" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_16384x2_sp.out"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[13:0]" name="address1" output="mem_16384x2_sp.addr"/>
					<direct input="memory.data[1:0]" name="data1" output="mem_16384x2_sp.data"/>
					<direct input="memory.we1" name="writeen1" output="mem_16384x2_sp.we"/>
					<direct input="mem_16384x2_sp.out" name="dataout1" output="memory.out[1:0]"/>
					<direct input="memory.clk" name="clk" output="mem_16384x2_sp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_32768x1_sp">
				<pb_type blif_model=".subckt single_port_ram" class="memory" name="mem_32768x1_sp" num_pb="1">
					<input name="addr" num_pins="15" port_class="address"/>
					<input name="data" num_pins="1" port_class="data_in"/>
					<input name="we" num_pins="1" port_class="write_en"/>
					<output name="out" num_pins="1" port_class="data_out"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_32768x1_sp.addr" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_32768x1_sp.data" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_32768x1_sp.we" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_32768x1_sp.out"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[14:0]" name="address1" output="mem_32768x1_sp.addr"/>
					<direct input="memory.data[0:0]" name="data1" output="mem_32768x1_sp.data"/>
					<direct input="memory.we1" name="writeen1" output="mem_32768x1_sp.we"/>
					<direct input="mem_32768x1_sp.out" name="dataout1" output="memory.out[0:0]"/>
					<direct input="memory.clk" name="clk" output="mem_32768x1_sp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_1024x32_dp">
				<pb_type blif_model=".subckt dual_port_ram" class="memory" name="mem_1024x32_dp" num_pb="1">
					<input name="addr1" num_pins="10" port_class="address1"/>
					<input name="addr2" num_pins="10" port_class="address2"/>
					<input name="data1" num_pins="32" port_class="data_in1"/>
					<input name="data2" num_pins="32" port_class="data_in2"/>
					<input name="we1" num_pins="1" port_class="write_en1"/>
					<input name="we2" num_pins="1" port_class="write_en2"/>
					<output name="out1" num_pins="32" port_class="data_out1"/>
					<output name="out2" num_pins="32" port_class="data_out2"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_1024x32_dp.addr1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_1024x32_dp.data1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_1024x32_dp.we1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_1024x32_dp.addr2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_1024x32_dp.data2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_1024x32_dp.we2" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_1024x32_dp.out1"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_1024x32_dp.out2"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[9:0]" name="address1" output="mem_1024x32_dp.addr1"/>
					<direct input="memory.addr2[9:0]" name="address2" output="mem_1024x32_dp.addr2"/>
					<direct input="memory.data[31:0]" name="data1" output="mem_1024x32_dp.data1"/>
					<direct input="memory.data[63:32]" name="data2" output="mem_1024x32_dp.data2"/>
					<direct input="memory.we1" name="writeen1" output="mem_1024x32_dp.we1"/>
					<direct input="memory.we2" name="writeen2" output="mem_1024x32_dp.we2"/>
					<direct input="mem_1024x32_dp.out1" name="dataout1" output="memory.out[31:0]"/>
					<direct input="mem_1024x32_dp.out2" name="dataout2" output="memory.out[63:32]"/>
					<direct input="memory.clk" name="clk" output="mem_1024x32_dp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_2048x16_dp">
				<pb_type blif_model=".subckt dual_port_ram" class="memory" name="mem_2048x16_dp" num_pb="1">
					<input name="addr1" num_pins="11" port_class="address1"/>
					<input name="addr2" num_pins="11" port_class="address2"/>
					<input name="data1" num_pins="16" port_class="data_in1"/>
					<input name="data2" num_pins="16" port_class="data_in2"/>
					<input name="we1" num_pins="1" port_class="write_en1"/>
					<input name="we2" num_pins="1" port_class="write_en2"/>
					<output name="out1" num_pins="16" port_class="data_out1"/>
					<output name="out2" num_pins="16" port_class="data_out2"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_2048x16_dp.addr1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x16_dp.data1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x16_dp.we1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x16_dp.addr2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x16_dp.data2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x16_dp.we2" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_2048x16_dp.out1"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_2048x16_dp.out2"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[10:0]" name="address1" output="mem_2048x16_dp.addr1"/>
					<direct input="memory.addr2[10:0]" name="address2" output="mem_2048x16_dp.addr2"/>
					<direct input="memory.data[15:0]" name="data1" output="mem_2048x16_dp.data1"/>
					<direct input="memory.data[31:16]" name="data2" output="mem_2048x16_dp.data2"/>
					<direct input="memory.we1" name="writeen1" output="mem_2048x16_dp.we1"/>
					<direct input="memory.we2" name="writeen2" output="mem_2048x16_dp.we2"/>
					<direct input="mem_2048x16_dp.out1" name="dataout1" output="memory.out[15:0]"/>
					<direct input="mem_2048x16_dp.out2" name="dataout2" output="memory.out[31:16]"/>
					<direct input="memory.clk" name="clk" output="mem_2048x16_dp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_2048x8_dp">
				<pb_type blif_model=".subckt dual_port_ram" class="memory" name="mem_2048x8_dp" num_pb="1">
					<input name="addr1" num_pins="12" port_class="address1"/>
					<input name="addr2" num_pins="12" port_class="address2"/>
					<input name="data1" num_pins="8" port_class="data_in1"/>
					<input name="data2" num_pins="8" port_class="data_in2"/>
					<input name="we1" num_pins="1" port_class="write_en1"/>
					<input name="we2" num_pins="1" port_class="write_en2"/>
					<output name="out1" num_pins="8" port_class="data_out1"/>
					<output name="out2" num_pins="8" port_class="data_out2"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_2048x8_dp.addr1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x8_dp.data1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x8_dp.we1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x8_dp.addr2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x8_dp.data2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_2048x8_dp.we2" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_2048x8_dp.out1"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_2048x8_dp.out2"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[11:0]" name="address1" output="mem_2048x8_dp.addr1"/>
					<direct input="memory.addr2[11:0]" name="address2" output="mem_2048x8_dp.addr2"/>
					<direct input="memory.data[7:0]" name="data1" output="mem_2048x8_dp.data1"/>
					<direct input="memory.data[15:8]" name="data2" output="mem_2048x8_dp.data2"/>
					<direct input="memory.we1" name="writeen1" output="mem_2048x8_dp.we1"/>
					<direct input="memory.we2" name="writeen2" output="mem_2048x8_dp.we2"/>
					<direct input="mem_2048x8_dp.out1" name="dataout1" output="memory.out[7:0]"/>
					<direct input="mem_2048x8_dp.out2" name="dataout2" output="memory.out[15:8]"/>
					<direct input="memory.clk" name="clk" output="mem_2048x8_dp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_8192x4_dp">
				<pb_type blif_model=".subckt dual_port_ram" class="memory" name="mem_8192x4_dp" num_pb="1">
					<input name="addr1" num_pins="13" port_class="address1"/>
					<input name="addr2" num_pins="13" port_class="address2"/>
					<input name="data1" num_pins="4" port_class="data_in1"/>
					<input name="data2" num_pins="4" port_class="data_in2"/>
					<input name="we1" num_pins="1" port_class="write_en1"/>
					<input name="we2" num_pins="1" port_class="write_en2"/>
					<output name="out1" num_pins="4" port_class="data_out1"/>
					<output name="out2" num_pins="4" port_class="data_out2"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_8192x4_dp.addr1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_8192x4_dp.data1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_8192x4_dp.we1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_8192x4_dp.addr2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_8192x4_dp.data2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_8192x4_dp.we2" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_8192x4_dp.out1"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_8192x4_dp.out2"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[12:0]" name="address1" output="mem_8192x4_dp.addr1"/>
					<direct input="memory.addr2[12:0]" name="address2" output="mem_8192x4_dp.addr2"/>
					<direct input="memory.data[3:0]" name="data1" output="mem_8192x4_dp.data1"/>
					<direct input="memory.data[7:4]" name="data2" output="mem_8192x4_dp.data2"/>
					<direct input="memory.we1" name="writeen1" output="mem_8192x4_dp.we1"/>
					<direct input="memory.we2" name="writeen2" output="mem_8192x4_dp.we2"/>
					<direct input="mem_8192x4_dp.out1" name="dataout1" output="memory.out[3:0]"/>
					<direct input="mem_8192x4_dp.out2" name="dataout2" output="memory.out[7:4]"/>
					<direct input="memory.clk" name="clk" output="mem_8192x4_dp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_16384x2_dp">
				<pb_type blif_model=".subckt dual_port_ram" class="memory" name="mem_16384x2_dp" num_pb="1">
					<input name="addr1" num_pins="14" port_class="address1"/>
					<input name="addr2" num_pins="14" port_class="address2"/>
					<input name="data1" num_pins="2" port_class="data_in1"/>
					<input name="data2" num_pins="2" port_class="data_in2"/>
					<input name="we1" num_pins="1" port_class="write_en1"/>
					<input name="we2" num_pins="1" port_class="write_en2"/>
					<output name="out1" num_pins="2" port_class="data_out1"/>
					<output name="out2" num_pins="2" port_class="data_out2"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_16384x2_dp.addr1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_16384x2_dp.data1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_16384x2_dp.we1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_16384x2_dp.addr2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_16384x2_dp.data2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_16384x2_dp.we2" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_16384x2_dp.out1"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_16384x2_dp.out2"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[13:0]" name="address1" output="mem_16384x2_dp.addr1"/>
					<direct input="memory.addr2[13:0]" name="address2" output="mem_16384x2_dp.addr2"/>
					<direct input="memory.data[1:0]" name="data1" output="mem_16384x2_dp.data1"/>
					<direct input="memory.data[3:2]" name="data2" output="mem_16384x2_dp.data2"/>
					<direct input="memory.we1" name="writeen1" output="mem_16384x2_dp.we1"/>
					<direct input="memory.we2" name="writeen2" output="mem_16384x2_dp.we2"/>
					<direct input="mem_16384x2_dp.out1" name="dataout1" output="memory.out[1:0]"/>
					<direct input="mem_16384x2_dp.out2" name="dataout2" output="memory.out[3:2]"/>
					<direct input="memory.clk" name="clk" output="mem_16384x2_dp.clk"/>
				</interconnect>
			</mode>
			<mode name="mem_32768x1_dp">
				<pb_type blif_model=".subckt dual_port_ram" class="memory" name="mem_32768x1_dp" num_pb="1">
					<input name="addr1" num_pins="15" port_class="address1"/>
					<input name="addr2" num_pins="15" port_class="address2"/>
					<input name="data1" num_pins="1" port_class="data_in1"/>
					<input name="data2" num_pins="1" port_class="data_in2"/>
					<input name="we1" num_pins="1" port_class="write_en1"/>
					<input name="we2" num_pins="1" port_class="write_en2"/>
					<output name="out1" num_pins="1" port_class="data_out1"/>
					<output name="out2" num_pins="1" port_class="data_out2"/>
					<clock name="clk" num_pins="1" port_class="clock"/>
					<T_setup clock="clk" port="mem_32768x1_dp.addr1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_32768x1_dp.data1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_32768x1_dp.we1" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_32768x1_dp.addr2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_32768x1_dp.data2" value="2.448e-10"/>
					<T_setup clock="clk" port="mem_32768x1_dp.we2" value="2.448e-10"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_32768x1_dp.out1"/>
					<T_clock_to_Q clock="clk" max="1.667e-9" port="mem_32768x1_dp.out2"/>
				</pb_type>
				<interconnect>
					<direct input="memory.addr1[14:0]" name="address1" output="mem_32768x1_dp.addr1"/>
					<direct input="memory.addr2[14:0]" name="address2" output="mem_32768x1_dp.addr2"/>
					<direct input="memory.data[0:0]" name="data1" output="mem_32768x1_dp.data1"/>
					<direct input="memory.data[1:1]" name="data2" output="mem_32768x1_dp.data2"/>
					<direct input="memory.we1" name="writeen1" output="mem_32768x1_dp.we1"/>
					<direct input="memory.we2" name="writeen2" output="mem_32768x1_dp.we2"/>
					<direct input="mem_32768x1_dp.out1" name="dataout1" output="memory.out[0:0]"/>
					<direct input="mem_32768x1_dp.out2" name="dataout2" output="memory.out[1:1]"/>
					<direct input="memory.clk" name="clk" output="mem_32768x1_dp.clk"/>
				</interconnect>
			</mode>
		</pb_type>
	</complexblocklist>
	<segmentlist>

		<segment Cmetal="0.000000e+00" Rmetal="0.000000" freq="0.5" length="4" type="unidir">
			<mux name="0"/>
			<sb type="pattern">1 1 1 1 1</sb>
			<cb type="pattern">1 1 1 1</cb>
		</segment>
		<segment Cmetal="0.000000e+00" Rmetal="0.000000" freq="0.5" length="4" type="unidir">
			<mux name="0"/>
			<sb type="pattern">1 1 1 1 1</sb>
			<cb type="pattern">1 1 1 1</cb>
			<bend type="pattern">CC ST ST</bend>
		</segment>
	</segmentlist>
</architecture>