From 454af1b00be854cd29369c1370f39c09686aca35 Mon Sep 17 00:00:00 2001 From: Baocheng Su Date: Fri, 27 Dec 2024 10:01:31 +0800 Subject: [PATCH] u-boot: Fix the SPI and eMMC hang issue This backports 3738645af03054e6e16d7f28fd2d644aa5f1e21a from master branch. Original commit message: Refer to 1 and 2, the root cause is the wrong data type of the timer value. Thanks ronald.wahl@legrand.com for the patches. 1. https://lists.denx.de/pipermail/u-boot/2024-December/574817.html 2. https://lists.denx.de/pipermail/u-boot/2024-December/574818.html Signed-off-by: Baocheng Su --- ...spi-Fix-error-message-on-stuck-busy-.patch | 29 +++++++++++ ...spi-fix-potential-malfunction-after-.patch | 50 +++++++++++++++++++ ...Fix-potential-timer-value-truncation.patch | 42 ++++++++++++++++ recipes-bsp/u-boot/u-boot-iot2050_2023.10.bb | 3 ++ 4 files changed, 124 insertions(+) create mode 100644 recipes-bsp/u-boot/files/0012-spi-cadence-quadspi-Fix-error-message-on-stuck-busy-.patch create mode 100644 recipes-bsp/u-boot/files/0013-spi-cadence-quadspi-fix-potential-malfunction-after-.patch create mode 100644 recipes-bsp/u-boot/files/0014-mmc-Fix-potential-timer-value-truncation.patch diff --git a/recipes-bsp/u-boot/files/0012-spi-cadence-quadspi-Fix-error-message-on-stuck-busy-.patch b/recipes-bsp/u-boot/files/0012-spi-cadence-quadspi-Fix-error-message-on-stuck-busy-.patch new file mode 100644 index 000000000..08ea1ad07 --- /dev/null +++ b/recipes-bsp/u-boot/files/0012-spi-cadence-quadspi-Fix-error-message-on-stuck-busy-.patch @@ -0,0 +1,29 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jan Kiszka +Date: Mon, 30 Oct 2023 17:20:29 +0100 +Subject: [PATCH] spi: cadence-quadspi: Fix error message on stuck busy state + +We are not iterating CQSPI_REG_RETRY, we are waiting 'timeout' ms, since +day 1. + +Signed-off-by: Jan Kiszka +Reviewed-by: Stefan Roese +Reviewed-by: Jagan Teki +--- + drivers/spi/cadence_qspi_apb.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c +index 9ce2c0f254f3..d033184aa466 100644 +--- a/drivers/spi/cadence_qspi_apb.c ++++ b/drivers/spi/cadence_qspi_apb.c +@@ -171,8 +171,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base) + } + + /* Timeout, still in busy mode. */ +- printf("QSPI: QSPI is still busy after poll for %d times.\n", +- CQSPI_REG_RETRY); ++ printf("QSPI: QSPI is still busy after poll for %d ms.\n", timeout); + return 0; + } + diff --git a/recipes-bsp/u-boot/files/0013-spi-cadence-quadspi-fix-potential-malfunction-after-.patch b/recipes-bsp/u-boot/files/0013-spi-cadence-quadspi-fix-potential-malfunction-after-.patch new file mode 100644 index 000000000..5300c2971 --- /dev/null +++ b/recipes-bsp/u-boot/files/0013-spi-cadence-quadspi-fix-potential-malfunction-after-.patch @@ -0,0 +1,50 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ronald Wahl +Date: Wed, 11 Dec 2024 21:51:04 +0100 +Subject: [PATCH] spi: cadence-quadspi: fix potential malfunction after ~49 + days uptime + +The get_timer function returns an unsigned long which may be calculated +from the ARM system counter. This counter is reset only on a cold reset. +U-boot divides this counter down to a 1000 Hz counter that will cross +the 32bit barrier after a bit more than 49 days. Assigning the value to +an unsigned int will truncate it on 64bit systems. +Passing this truncated value back to the get_timer function will return +a very large value that is certainly larger than the timeout and so will +go down the error path and besides stopping U-Boot will lead to messages +like + + "SPI: QSPI is still busy after poll for 5000 ms." + +Signed-off-by: Ronald Wahl +Cc: Vignesh R +Cc: Pratyush Yadav +--- + drivers/spi/cadence_qspi_apb.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c +index d033184aa466..ecbd6f9d147d 100644 +--- a/drivers/spi/cadence_qspi_apb.c ++++ b/drivers/spi/cadence_qspi_apb.c +@@ -152,9 +152,9 @@ static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv, + /* Return 1 if idle, otherwise return 0 (busy). */ + static unsigned int cadence_qspi_wait_idle(void *reg_base) + { +- unsigned int start, count = 0; ++ unsigned long start, count = 0; + /* timeout in unit of ms */ +- unsigned int timeout = 5000; ++ unsigned long timeout = 5000; + + start = get_timer(0); + for ( ; get_timer(start) < timeout ; ) { +@@ -171,7 +171,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base) + } + + /* Timeout, still in busy mode. */ +- printf("QSPI: QSPI is still busy after poll for %d ms.\n", timeout); ++ printf("QSPI: QSPI is still busy after poll for %lu ms.\n", timeout); + return 0; + } + diff --git a/recipes-bsp/u-boot/files/0014-mmc-Fix-potential-timer-value-truncation.patch b/recipes-bsp/u-boot/files/0014-mmc-Fix-potential-timer-value-truncation.patch new file mode 100644 index 000000000..51e9f093d --- /dev/null +++ b/recipes-bsp/u-boot/files/0014-mmc-Fix-potential-timer-value-truncation.patch @@ -0,0 +1,42 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ronald Wahl +Date: Wed, 11 Dec 2024 21:52:00 +0100 +Subject: [PATCH] mmc: Fix potential timer value truncation + +On 64bit systems the timer value might be truncated to a 32bit value +causing malfunctions. For example on ARM the timer might start from 0 +again only after a cold reset. The 32bit overflow occurs after a bit +more than 49 days (1000 Hz counter) so booting after that time may lead +to a surprise because the board might become stuck requiring a cold +reset. + +Signed-off-by: Ronald Wahl +Cc: Peng Fan +Cc: Jaehoon Chung +--- + drivers/mmc/mmc.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c +index 31cfda288587..2779302b843e 100644 +--- a/drivers/mmc/mmc.c ++++ b/drivers/mmc/mmc.c +@@ -713,7 +713,7 @@ static int mmc_send_op_cond(struct mmc *mmc) + { + int err, i; + int timeout = 1000; +- uint start; ++ ulong start; + + /* Some cards seem to need this */ + mmc_go_idle(mmc); +@@ -808,7 +808,8 @@ int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) + static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, + bool send_status) + { +- unsigned int status, start; ++ ulong start; ++ unsigned int status; + struct mmc_cmd cmd; + int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS; + bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) && diff --git a/recipes-bsp/u-boot/u-boot-iot2050_2023.10.bb b/recipes-bsp/u-boot/u-boot-iot2050_2023.10.bb index 71676b5bb..38879be57 100644 --- a/recipes-bsp/u-boot/u-boot-iot2050_2023.10.bb +++ b/recipes-bsp/u-boot/u-boot-iot2050_2023.10.bb @@ -23,6 +23,9 @@ SRC_URI += " \ file://0009-dts-iot2050-Sync-kernel-dts-to-u-boot.patch \ file://0010-dts-iot2050-Support-new-IOT2050-SM-variant.patch \ file://0011-arm-dts-iot2050-Disable-lock-step-mode-for-all-iot20.patch \ + file://0012-spi-cadence-quadspi-Fix-error-message-on-stuck-busy-.patch \ + file://0013-spi-cadence-quadspi-fix-potential-malfunction-after-.patch \ + file://0014-mmc-Fix-potential-timer-value-truncation.patch \ " SRC_URI[sha256sum] = "e00e6c6f014e046101739d08d06f328811cebcf5ae101348f409cbbd55ce6900"