cv32e40s_manifest.flist

///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2020 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
///////////////////////////////////////////////////////////////////////////////
//
// Manifest for the CV32E40S RTL model.
//   - Intended to be used by both synthesis and simulation.
//   - Relevent synthesis and simulation scripts/Makefiles must set the shell
//     ENV variable DESIGN_RTL_DIR as required.
//
///////////////////////////////////////////////////////////////////////////////

+incdir+${DESIGN_RTL_DIR}/include
+incdir+${DESIGN_RTL_DIR}/../bhv
+incdir+${DESIGN_RTL_DIR}/../bhv/include
+incdir+${DESIGN_RTL_DIR}/../sva

${DESIGN_RTL_DIR}/include/cv32e40s_pkg.sv
${DESIGN_RTL_DIR}/cv32e40s_if_c_obi.sv
${DESIGN_RTL_DIR}/../bhv/include/cv32e40s_rvfi_pkg.sv
${DESIGN_RTL_DIR}/../bhv/cv32e40s_wrapper.sv
${DESIGN_RTL_DIR}/cv32e40s_dummy_instr.sv
${DESIGN_RTL_DIR}/cv32e40s_if_stage.sv
${DESIGN_RTL_DIR}/cv32e40s_csr.sv
${DESIGN_RTL_DIR}/cv32e40s_debug_triggers.sv
${DESIGN_RTL_DIR}/cv32e40s_cs_registers.sv
${DESIGN_RTL_DIR}/cv32e40s_register_file.sv
${DESIGN_RTL_DIR}/cv32e40s_register_file_ecc.sv
${DESIGN_RTL_DIR}/cv32e40s_register_file_wrapper.sv
${DESIGN_RTL_DIR}/cv32e40s_write_buffer.sv
${DESIGN_RTL_DIR}/cv32e40s_lsu_response_filter.sv
${DESIGN_RTL_DIR}/cv32e40s_load_store_unit.sv
${DESIGN_RTL_DIR}/cv32e40s_id_stage.sv
${DESIGN_RTL_DIR}/cv32e40s_i_decoder.sv
${DESIGN_RTL_DIR}/cv32e40s_m_decoder.sv
${DESIGN_RTL_DIR}/cv32e40s_b_decoder.sv
${DESIGN_RTL_DIR}/cv32e40s_decoder.sv
${DESIGN_RTL_DIR}/cv32e40s_compressed_decoder.sv
${DESIGN_RTL_DIR}/cv32e40s_sequencer.sv
${DESIGN_RTL_DIR}/cv32e40s_alignment_buffer.sv
${DESIGN_RTL_DIR}/cv32e40s_prefetch_unit.sv
${DESIGN_RTL_DIR}/cv32e40s_mult.sv
${DESIGN_RTL_DIR}/cv32e40s_int_controller.sv
${DESIGN_RTL_DIR}/cv32e40s_clic_int_controller.sv
${DESIGN_RTL_DIR}/cv32e40s_ex_stage.sv
${DESIGN_RTL_DIR}/cv32e40s_wb_stage.sv
${DESIGN_RTL_DIR}/cv32e40s_div.sv
${DESIGN_RTL_DIR}/cv32e40s_alu.sv
${DESIGN_RTL_DIR}/cv32e40s_ff_one.sv
${DESIGN_RTL_DIR}/cv32e40s_popcnt.sv
${DESIGN_RTL_DIR}/cv32e40s_alu_b_cpop.sv
${DESIGN_RTL_DIR}/cv32e40s_controller_fsm.sv
${DESIGN_RTL_DIR}/cv32e40s_controller_bypass.sv
${DESIGN_RTL_DIR}/cv32e40s_controller.sv
${DESIGN_RTL_DIR}/cv32e40s_obi_integrity_fifo.sv
${DESIGN_RTL_DIR}/cv32e40s_instr_obi_interface.sv
${DESIGN_RTL_DIR}/cv32e40s_data_obi_interface.sv
${DESIGN_RTL_DIR}/cv32e40s_prefetcher.sv
${DESIGN_RTL_DIR}/cv32e40s_sleep_unit.sv
${DESIGN_RTL_DIR}/cv32e40s_alert.sv
${DESIGN_RTL_DIR}/cv32e40s_core.sv
${DESIGN_RTL_DIR}/cv32e40s_mpu.sv
${DESIGN_RTL_DIR}/cv32e40s_pma.sv
${DESIGN_RTL_DIR}/cv32e40s_pmp.sv
${DESIGN_RTL_DIR}/cv32e40s_pc_target.sv
${DESIGN_RTL_DIR}/cv32e40s_wpt.sv
${DESIGN_RTL_DIR}/cv32e40s_pc_check.sv
${DESIGN_RTL_DIR}/cv32e40s_rchk_check.sv
${DESIGN_RTL_DIR}/cv32e40s_lfsr.sv

${DESIGN_RTL_DIR}/../bhv/cv32e40s_sim_sffr.sv
${DESIGN_RTL_DIR}/../bhv/cv32e40s_sim_sffs.sv
${DESIGN_RTL_DIR}/../bhv/cv32e40s_sim_clock_gate.sv
${DESIGN_RTL_DIR}/../bhv/cv32e40s_rvfi_instr_obi.sv
${DESIGN_RTL_DIR}/../bhv/cv32e40s_rvfi_data_obi.sv
${DESIGN_RTL_DIR}/../bhv/cv32e40s_rvfi.sv
${DESIGN_RTL_DIR}/../bhv/cv32e40s_rvfi_sim_trace.sv