From 7b384fd91963c096d25dd8eb9af8be78884861c2 Mon Sep 17 00:00:00 2001
From: Peter Gadfort <gadfort@zeroasic.com>
Date: Tue, 15 Aug 2023 07:06:01 -0400
Subject: [PATCH] remove stray max_transitions from SRAM model

---
 .../ram/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib      | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/asic/sky130/ram/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib b/asic/sky130/ram/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
index a2bdf73..2c08585 100644
--- a/asic/sky130/ram/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+++ b/asic/sky130/ram/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
@@ -185,7 +185,6 @@ cell (sky130_sram_2kbyte_1rw1r_32x512_8){
         bus_type  : addr; 
         direction  : input; 
         capacitance : 0.006889999999999999;  
-        max_transition       : 0.04;
         pin(addr0[8:0]){
         timing(){ 
             timing_type : setup_rising; 
@@ -222,7 +221,6 @@ cell (sky130_sram_2kbyte_1rw1r_32x512_8){
         bus_type  : wmask; 
         direction  : input; 
         capacitance : 0.006889999999999999;  
-        max_transition       : 0.04;
         pin(wmask0[3:0]){
         timing(){ 
             timing_type : setup_rising; 
@@ -424,7 +422,6 @@ cell (sky130_sram_2kbyte_1rw1r_32x512_8){
         bus_type  : addr; 
         direction  : input; 
         capacitance : 0.006889999999999999;  
-        max_transition       : 0.04;
         pin(addr1[8:0]){
         timing(){ 
             timing_type : setup_rising;