diff --git a/.gitignore b/.gitignore
index 73a267919..4332d6f99 100644
--- a/.gitignore
+++ b/.gitignore
@@ -180,3 +180,236 @@ buildroot/board/cvitek/SG200X/overlay/mnt/system/sdk-release
 buildroot/board/cvitek/SG200X/overlay/mnt/system/auto.sh
 middleware/v2/mod_tmp/*
 cscope.out
+middleware/v2/3rdparty/inih/ini.d
+middleware/v2/3rdparty/inih/ini.o
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_cmos.d
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_cmos.o
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_sensor_ctl.d
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_sensor_ctl.o
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_cmos.d
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_cmos.o
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_sensor_ctl.d
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_sensor_ctl.o
+middleware/v2/lib/libsns_os04a10.a
+middleware/v2/lib/libsns_os04a10.so
+middleware/v2/modules/bin/src/cvi_bin.d
+middleware/v2/modules/bin/src/cvi_bin.o
+middleware/v2/modules/bin/src/md5.d
+middleware/v2/modules/bin/src/md5.o
+middleware/v2/modules/bin/src/rw_json.d
+middleware/v2/modules/bin/src/rw_json.o
+middleware/v2/modules/bin/src/vo_bin.d
+middleware/v2/modules/bin/src/vo_bin.o
+middleware/v2/modules/bin/src/vo_json_struct.d
+middleware/v2/modules/bin/src/vo_json_struct.o
+middleware/v2/modules/bin/src/vpss_bin.d
+middleware/v2/modules/bin/src/vpss_bin.o
+middleware/v2/modules/bin/src/vpss_json_struct.d
+middleware/v2/modules/bin/src/vpss_json_struct.o
+middleware/v2/modules/ive/src/cvi_ive.d
+middleware/v2/modules/ive/src/cvi_ive.o
+middleware/v2/modules/mipi_tx/src/mipi_tx.d
+middleware/v2/modules/mipi_tx/src/mipi_tx.o
+middleware/v2/modules/misc/src/cvi_misc.d
+middleware/v2/modules/misc/src/cvi_misc.o
+middleware/v2/modules/osdc/src/cmpr_canvas.d
+middleware/v2/modules/osdc/src/cmpr_canvas.o
+middleware/v2/modules/osdc/src/cvi_osdc.d
+middleware/v2/modules/osdc/src/cvi_osdc.o
+middleware/v2/modules/osdc/src/osd_cmpr.d
+middleware/v2/modules/osdc/src/osd_cmpr.o
+middleware/v2/modules/sys/src/cvi_base.d
+middleware/v2/modules/sys/src/cvi_base.o
+middleware/v2/modules/sys/src/cvi_sys.d
+middleware/v2/modules/sys/src/cvi_sys.o
+middleware/v2/modules/sys/src/cvi_thermal.d
+middleware/v2/modules/sys/src/cvi_thermal.o
+middleware/v2/modules/sys/src/cvi_tracer.d
+middleware/v2/modules/sys/src/cvi_tracer.o
+middleware/v2/modules/sys/src/cvi_vb.d
+middleware/v2/modules/sys/src/cvi_vb.o
+middleware/v2/modules/sys/src/devmem.d
+middleware/v2/modules/sys/src/devmem.o
+middleware/v2/modules/sys/src/hashmap.d
+middleware/v2/modules/sys/src/hashmap.o
+middleware/v2/modules/sys/src/peri.d
+middleware/v2/modules/sys/src/peri.o
+middleware/v2/modules/sys/src/sys_ioctl.d
+middleware/v2/modules/sys/src/sys_ioctl.o
+middleware/v2/modules/sys/src/vb_ioctl.d
+middleware/v2/modules/sys/src/vb_ioctl.o
+middleware/v2/modules/vdec/src/cvi_vdec.d
+middleware/v2/modules/vdec/src/cvi_vdec.o
+middleware/v2/modules/venc/src/cvi_venc.d
+middleware/v2/modules/venc/src/cvi_venc.o
+middleware/v2/modules/vpu/src/cvi_gdc_1822.d
+middleware/v2/modules/vpu/src/cvi_gdc_1822.o
+middleware/v2/modules/vpu/src/cvi_region.d
+middleware/v2/modules/vpu/src/cvi_region.o
+middleware/v2/modules/vpu/src/cvi_vi.d
+middleware/v2/modules/vpu/src/cvi_vi.o
+middleware/v2/modules/vpu/src/cvi_vo.d
+middleware/v2/modules/vpu/src/cvi_vo.o
+middleware/v2/modules/vpu/src/cvi_vpss.d
+middleware/v2/modules/vpu/src/cvi_vpss.o
+middleware/v2/modules/vpu/src/dump_register.d
+middleware/v2/modules/vpu/src/dump_register.o
+middleware/v2/modules/vpu/src/dwa_ioctl.d
+middleware/v2/modules/vpu/src/dwa_ioctl.o
+middleware/v2/modules/vpu/src/gdc_mesh_1822.d
+middleware/v2/modules/vpu/src/gdc_mesh_1822.o
+middleware/v2/modules/vpu/src/rgn_ioctl.d
+middleware/v2/modules/vpu/src/rgn_ioctl.o
+middleware/v2/modules/vpu/src/vi_ioctl.d
+middleware/v2/modules/vpu/src/vi_ioctl.o
+middleware/v2/modules/vpu/src/vo_ioctl.d
+middleware/v2/modules/vpu/src/vo_ioctl.o
+middleware/v2/modules/vpu/src/vpss_ioctl.d
+middleware/v2/modules/vpu/src/vpss_ioctl.o
+middleware/v2/sample/audio/aac_sample/cvi_audio_aac_adp.d
+middleware/v2/sample/audio/aac_sample/cvi_audio_aac_adp.o
+middleware/v2/sample/audio/cvi_audio_dl_adp.d
+middleware/v2/sample/audio/cvi_audio_dl_adp.o
+middleware/v2/sample/audio/cvi_audio_parse_param.d
+middleware/v2/sample/audio/cvi_audio_parse_param.o
+middleware/v2/sample/audio/cvi_sample_audio.d
+middleware/v2/sample/audio/cvi_sample_audio.o
+middleware/v2/sample/audio/sample_audio
+middleware/v2/sample/common/loadbmp.d
+middleware/v2/sample/common/loadbmp.o
+middleware/v2/sample/common/md5sum.d
+middleware/v2/sample/common/md5sum.o
+middleware/v2/sample/common/sample_common_bin.d
+middleware/v2/sample/common/sample_common_bin.o
+middleware/v2/sample/common/sample_common_isp.d
+middleware/v2/sample/common/sample_common_isp.o
+middleware/v2/sample/common/sample_common_peripheral.d
+middleware/v2/sample/common/sample_common_peripheral.o
+middleware/v2/sample/common/sample_common_platform.d
+middleware/v2/sample/common/sample_common_platform.o
+middleware/v2/sample/common/sample_common_region.d
+middleware/v2/sample/common/sample_common_region.o
+middleware/v2/sample/common/sample_common_sensor.d
+middleware/v2/sample/common/sample_common_sensor.o
+middleware/v2/sample/common/sample_common_sys.d
+middleware/v2/sample/common/sample_common_sys.o
+middleware/v2/sample/common/sample_common_vdec.d
+middleware/v2/sample/common/sample_common_vdec.o
+middleware/v2/sample/common/sample_common_venc.d
+middleware/v2/sample/common/sample_common_venc.o
+middleware/v2/sample/common/sample_common_vi.d
+middleware/v2/sample/common/sample_common_vi.o
+middleware/v2/sample/common/sample_common_vo.d
+middleware/v2/sample/common/sample_common_vo.o
+middleware/v2/sample/common/sample_common_vpss.d
+middleware/v2/sample/common/sample_common_vpss.o
+middleware/v2/sample/fisheye/sample_fisheye
+middleware/v2/sample/fisheye/sample_fisheye.d
+middleware/v2/sample/fisheye/sample_fisheye.o
+middleware/v2/sample/ir_auto/ir_auto
+middleware/v2/sample/ir_auto/ir_auto.d
+middleware/v2/sample/ir_auto/ir_auto.o
+middleware/v2/sample/ive/sample_16bitto8bit
+middleware/v2/sample/ive/sample_add
+middleware/v2/sample/ive/sample_and
+middleware/v2/sample/ive/sample_bernsen
+middleware/v2/sample/ive/sample_bgmodel
+middleware/v2/sample/ive/sample_cannyedge
+middleware/v2/sample/ive/sample_cannyhysedge
+middleware/v2/sample/ive/sample_csc
+middleware/v2/sample/ive/sample_dilate
+middleware/v2/sample/ive/sample_dma
+middleware/v2/sample/ive/sample_erode
+middleware/v2/sample/ive/sample_filter
+middleware/v2/sample/ive/sample_filterandcsc
+middleware/v2/sample/ive/sample_framediffmotion
+middleware/v2/sample/ive/sample_gmm
+middleware/v2/sample/ive/sample_gmm2
+middleware/v2/sample/ive/sample_gradfg
+middleware/v2/sample/ive/sample_hist
+middleware/v2/sample/ive/sample_integ
+middleware/v2/sample/ive/sample_lbp
+middleware/v2/sample/ive/sample_magandang
+middleware/v2/sample/ive/sample_map
+middleware/v2/sample/ive/sample_ncc
+middleware/v2/sample/ive/sample_normgrad
+middleware/v2/sample/ive/sample_or
+middleware/v2/sample/ive/sample_ordstatfilter
+middleware/v2/sample/ive/sample_query
+middleware/v2/sample/ive/sample_resize
+middleware/v2/sample/ive/sample_sad
+middleware/v2/sample/ive/sample_sobel
+middleware/v2/sample/ive/sample_stcandicorner
+middleware/v2/sample/ive/sample_sub
+middleware/v2/sample/ive/sample_thresh
+middleware/v2/sample/ive/sample_thresh_S16
+middleware/v2/sample/ive/sample_thresh_U16
+middleware/v2/sample/ive/sample_xor
+middleware/v2/sample/mipi_tx/lt9611/lt9611
+middleware/v2/sample/mipi_tx/lt9611/lt9611.d
+middleware/v2/sample/mipi_tx/lt9611/lt9611.o
+middleware/v2/sample/mipi_tx/sample_dsi
+middleware/v2/sample/mipi_tx/sample_dsi.d
+middleware/v2/sample/mipi_tx/sample_dsi.o
+middleware/v2/sample/osdc/sample_osdc
+middleware/v2/sample/osdc/sample_osdc.d
+middleware/v2/sample/osdc/sample_osdc.o
+middleware/v2/sample/overlay/sample_overlay
+middleware/v2/sample/overlay/sample_overlay.d
+middleware/v2/sample/overlay/sample_overlay.o
+middleware/v2/sample/region/sample_region
+middleware/v2/sample/region/sample_region.d
+middleware/v2/sample/region/sample_region.o
+middleware/v2/sample/sample_panel/sample_panel.d
+middleware/v2/sample/sample_panel/sample_panel.o
+middleware/v2/sample/scene_auto/sample_scene_auto
+middleware/v2/sample/scene_auto/src/core/cvi_scene.d
+middleware/v2/sample/scene_auto/src/core/cvi_scene.o
+middleware/v2/sample/scene_auto/src/core/cvi_scene_setparam.d
+middleware/v2/sample/scene_auto/src/core/cvi_scene_setparam.o
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_decode.d
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_decode.o
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_loadparam.d
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_loadparam.o
+middleware/v2/sample/scene_auto/src/sample/sample_scene.d
+middleware/v2/sample/scene_auto/src/sample/sample_scene.o
+middleware/v2/sample/scene_auto/src/sample/sample_scene_main.d
+middleware/v2/sample/scene_auto/src/sample/sample_scene_main.o
+middleware/v2/sample/scene_auto/tools/iniparser/src/dictionary.d
+middleware/v2/sample/scene_auto/tools/iniparser/src/dictionary.o
+middleware/v2/sample/scene_auto/tools/iniparser/src/iniparser.d
+middleware/v2/sample/scene_auto/tools/iniparser/src/iniparser.o
+middleware/v2/sample/sensor_test/sensor_test
+middleware/v2/sample/sensor_test/sensor_test.d
+middleware/v2/sample/sensor_test/sensor_test.o
+middleware/v2/sample/sensor_test/src/ae_test.d
+middleware/v2/sample/sensor_test/src/ae_test.o
+middleware/v2/sample/vdec/sample_vdec
+middleware/v2/sample/vdec/sample_vdec.d
+middleware/v2/sample/vdec/sample_vdec.o
+middleware/v2/sample/vdec/sample_vdec_asan
+middleware/v2/sample/vdec/src/sample_vdec_lib.d
+middleware/v2/sample/vdec/src/sample_vdec_lib.o
+middleware/v2/sample/vdec/src/sample_vdec_testcase.d
+middleware/v2/sample/vdec/src/sample_vdec_testcase.o
+middleware/v2/sample/vdecvo/sample_vdecvo
+middleware/v2/sample/vdecvo/sample_vdecvo.d
+middleware/v2/sample/vdecvo/sample_vdecvo.o
+middleware/v2/sample/venc/sample_vcodec
+middleware/v2/sample/venc/sample_vcodec.d
+middleware/v2/sample/venc/sample_vcodec.o
+middleware/v2/sample/venc/sample_vcodec_asan
+middleware/v2/sample/venc/sample_venc
+middleware/v2/sample/venc/sample_venc.d
+middleware/v2/sample/venc/sample_venc.o
+middleware/v2/sample/venc/sample_venc_asan
+middleware/v2/sample/venc/src/sample_venc_lib.d
+middleware/v2/sample/venc/src/sample_venc_lib.o
+middleware/v2/sample/venc/src/sample_venc_testcase.d
+middleware/v2/sample/venc/src/sample_venc_testcase.o
+middleware/v2/sample/vio/sample_vio
+middleware/v2/sample/vio/sample_vio.d
+middleware/v2/sample/vio/sample_vio.o
+middleware/v2/sample/vio/sample_vio_main.d
+middleware/v2/sample/vio/sample_vio_main.o
+osdrv/extdrv/wireless/.tmp_4261/
diff --git a/build/boards/default/dts/sg200x/soph_base.dtsi b/build/boards/default/dts/sg200x/soph_base.dtsi
index bc8f3f736..12c92cb07 100644
--- a/build/boards/default/dts/sg200x/soph_base.dtsi
+++ b/build/boards/default/dts/sg200x/soph_base.dtsi
@@ -156,21 +156,21 @@
 		compatible = "cvitek,cvi-pwm";
 		reg = <0x0 0x3060000 0x0 0x1000>;
 		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <1>;
+		#pwm-cells = <4>;
 	};
 
 	pwm1: pwm@3061000 {
 		compatible = "cvitek,cvi-pwm";
 		reg = <0x0 0x3061000 0x0 0x1000>;
 		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <2>;
+		#pwm-cells = <4>;
 	};
 
 	pwm2: pwm@3062000 {
 		compatible = "cvitek,cvi-pwm";
 		reg = <0x0 0x3062000 0x0 0x1000>;
 		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <3>;
+		#pwm-cells = <4>;
 	};
 
 	pwm3: pwm@3063000 {
diff --git a/build/boards/sg200x/sg2002_licheervnano_sd/dts_riscv/sg2002_licheervnano_sd.dts b/build/boards/sg200x/sg2002_licheervnano_sd/dts_riscv/sg2002_licheervnano_sd.dts
index 79f985111..c4b621fcf 100644
--- a/build/boards/sg200x/sg2002_licheervnano_sd/dts_riscv/sg2002_licheervnano_sd.dts
+++ b/build/boards/sg200x/sg2002_licheervnano_sd/dts_riscv/sg2002_licheervnano_sd.dts
@@ -8,7 +8,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 &i2c0 {
-        status = "disabled";
+        status = "okay";
         /delete-property/ scl-pinmux;
         /delete-property/ sda-pinmux;
         /delete-property/ scl-gpios;
@@ -16,7 +16,7 @@
 };
 
 &i2c1 {
-        status = "disabled";
+        status = "okay";
         /delete-property/ scl-pinmux;
         /delete-property/ sda-pinmux;
         /delete-property/ scl-gpios;
@@ -148,12 +148,16 @@
 		};
 	};
 
+	// buggy pwm driver, not working, please use userspace pwm api
+	/*
 	lcd0_backlight: pwm-backlight@0 {
 		compatible = "pwm-backlight";
+		pwm-names = "backlight";
 		pwms = <&pwm2 2 50000000>; // 20Khz
 		brightness-levels = <0 2 4 8 16 32 64 128 255>;
 		default-brightness-level = <4>;
 	};
+	*/
 
         wifisd:wifi-sd@4320000 {
                 compatible = "cvitek,cv181x-sdio";
diff --git a/build/boards/sg200x/sg2002_licheervnano_sd/u-boot/cvi_board_init.c b/build/boards/sg200x/sg2002_licheervnano_sd/u-boot/cvi_board_init.c
index 87ebc2364..b3e6c3d13 100644
--- a/build/boards/sg200x/sg2002_licheervnano_sd/u-boot/cvi_board_init.c
+++ b/build/boards/sg200x/sg2002_licheervnano_sd/u-boot/cvi_board_init.c
@@ -113,8 +113,8 @@ int cvi_board_init(void)
         mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE
 
 	// for licheervnano beta
-	//mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
-	mmio_write_32(0x030010ac, 0x0); // PWRGPIO 2 GPIO_MODE
+	mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
+	//mmio_write_32(0x030010ac, 0x0); // PWRGPIO 2 GPIO_MODE
 
         // camera function
         //mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0 for alpha
diff --git a/buildroot/board/cvitek/SG200X/overlay/etc/init.d/S04backlight b/buildroot/board/cvitek/SG200X/overlay/etc/init.d/S04backlight
new file mode 100755
index 000000000..35fcb7d66
--- /dev/null
+++ b/buildroot/board/cvitek/SG200X/overlay/etc/init.d/S04backlight
@@ -0,0 +1,30 @@
+#!/bin/sh
+
+if [ "$1" = "start" ]
+then
+	. /etc/profile
+	if [ ! -e /boot/alpha ]
+	then
+		blpwm="/sys/class/pwm/pwmchip8/pwm2/"
+		if [ ! -e "${blpwm}" ]
+		then
+			echo 2 > /sys/class/pwm/pwmchip8/export
+		fi
+		echo 0 > $blpwm/enable
+		echo "10000" > ${blpwm}/period # 100KHZ
+		if [ -e /boot/uEnv.txt ]
+		then
+			hd22800=$(cat /boot/uEnv.txt | grep hd228001c31 | wc -l)
+			if [ "${hd22800}" -ne 0 ]
+			then
+				echo "5000" > ${blpwm}/duty_cycle # 50%
+			else
+				echo "9500" > ${blpwm}/duty_cycle
+			fi
+		else
+			echo "9500" > ${blpwm}/duty_cycle
+		fi
+		echo 1 > $blpwm/enable
+	fi
+	exit 0
+fi