diff --git a/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Core.vhd b/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Core.vhd index fec7e359..eb9b87f2 100644 --- a/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Core.vhd +++ b/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Core.vhd @@ -25,6 +25,7 @@ use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; use surf.AxiStreamPkg.all; use surf.AxiPkg.all; +use surf.I2cPkg.all; library axi_pcie_core; use axi_pcie_core.AxiPciePkg.all; @@ -48,48 +49,82 @@ entity SlacPgpCardG4Core is -- Top Level Interfaces ------------------------ -- DMA Interfaces (dmaClk domain) - dmaClk : out sl; - dmaRst : out sl; - dmaBuffGrpPause : out slv(7 downto 0); - dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); - dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); - dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); - dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + dmaClk : out sl; + dmaRst : out sl; + dmaBuffGrpPause : out slv(7 downto 0); + dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); -- PIP Interface [0x00080000:0009FFFF] (dmaClk domain) - pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; - pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; + pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; + pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; -- Application AXI-Lite Interfaces [0x00100000:0x00FFFFFF] (appClk domain) - appClk : in sl := '0'; - appRst : in sl := '1'; - appReadMaster : out AxiLiteReadMasterType; - appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C; - appWriteMaster : out AxiLiteWriteMasterType; - appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; + appClk : in sl := '0'; + appRst : in sl := '1'; + appReadMaster : out AxiLiteReadMasterType; + appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C; + appWriteMaster : out AxiLiteWriteMasterType; + appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; ------------------- -- Top Level Ports ------------------- -- System Ports - emcClk : in sl; + emcClk : in sl; + pwrScl : inout sl; + pwrSda : inout sl; + sfpScl : inout sl; + sfpSda : inout sl; + qsfpScl : inout slv(1 downto 0); + qsfpSda : inout slv(1 downto 0); + qsfpRstL : out slv(1 downto 0); + qsfpLpMode : out slv(1 downto 0); + qsfpModSelL : out slv(1 downto 0); + qsfpModPrsL : in slv(1 downto 0); -- Boot Memory Ports - flashCsL : out sl; - flashMosi : out sl; - flashMiso : in sl; - flashHoldL : out sl; - flashWp : out sl; + flashCsL : out sl; + flashMosi : out sl; + flashMiso : in sl; + flashHoldL : out sl; + flashWp : out sl; -- PCIe Ports - pciRstL : in sl; - pciRefClkP : in sl; - pciRefClkN : in sl; - pciRxP : in slv(7 downto 0); - pciRxN : in slv(7 downto 0); - pciTxP : out slv(7 downto 0); - pciTxN : out slv(7 downto 0)); + pciRstL : in sl; + pciRefClkP : in sl; + pciRefClkN : in sl; + pciRxP : in slv(7 downto 0); + pciRxN : in slv(7 downto 0); + pciTxP : out slv(7 downto 0); + pciTxN : out slv(7 downto 0)); end SlacPgpCardG4Core; architecture mapping of SlacPgpCardG4Core is + constant XBAR_I2C_CONFIG_C : AxiLiteCrossbarMasterConfigArray(3 downto 0) := genAxiLiteConfig(4, x"0007_0000", 16, 12); + + constant SFF8472_I2C_CONFIG_C : I2cAxiLiteDevArray(1 downto 0) := ( + 0 => MakeI2cAxiLiteDevType( + i2cAddress => "1010000", -- 2 wire address 1010000X (A0h) + dataSize => 8, -- in units of bits + addrSize => 8, -- in units of bits + endianness => '0', -- Little endian + repeatStart => '1'), -- No repeat start + 1 => MakeI2cAxiLiteDevType( + i2cAddress => "1010001", -- 2 wire address 1010001X (A2h) + dataSize => 8, -- in units of bits + addrSize => 8, -- in units of bits + endianness => '0', -- Little endian + repeatStart => '1')); -- Repeat Start + + constant PWR_I2C_C : I2cAxiLiteDevArray(0 downto 0) := ( + 0 => MakeI2cAxiLiteDevType( + i2cAddress => "1001000", -- 0x90 = SA56004ATK + dataSize => 8, -- in units of bits + addrSize => 8, -- in units of bits + endianness => '0', -- Little endian + repeatStart => '0')); -- No repeat start + signal dmaReadMaster : AxiReadMasterType; signal dmaReadSlave : AxiReadSlaveType; signal dmaWriteMaster : AxiWriteMasterType; @@ -115,6 +150,16 @@ architecture mapping of SlacPgpCardG4Core is signal intPipObMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; signal intPipObSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; + signal i2cReadMaster : AxiLiteReadMasterType; + signal i2cReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C; + signal i2cWriteMaster : AxiLiteWriteMasterType; + signal i2cWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; + + signal i2cReadMasters : AxiLiteReadMasterArray(3 downto 0); + signal i2cReadSlaves : AxiLiteReadSlaveArray(3 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_OK_C); + signal i2cWriteMasters : AxiLiteWriteMasterArray(3 downto 0); + signal i2cWriteSlaves : AxiLiteWriteSlaveArray(3 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_OK_C); + signal sysClock : sl; signal sysReset : sl; signal systemReset : sl; @@ -147,6 +192,11 @@ begin systemReset <= sysReset or cardReset; + qsfpRstL(0) <= not(systemReset); + qsfpRstL(1) <= not(systemReset); + qsfpLpMode <= "00"; + qsfpModSelL <= "00"; + --------------- -- AXI PCIe PHY --------------- @@ -188,6 +238,84 @@ begin pipIbMaster <= intPipIbMaster; intPipIbSlave <= pipIbSlave; + U_XBAR : entity surf.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => 4, + MASTERS_CONFIG_G => XBAR_I2C_CONFIG_C) + port map ( + axiClk => sysClock, + axiClkRst => sysReset, + sAxiWriteMasters(0) => i2cWriteMaster, + sAxiWriteSlaves(0) => i2cWriteSlave, + sAxiReadMasters(0) => i2cReadMaster, + sAxiReadSlaves(0) => i2cReadSlave, + mAxiWriteMasters => i2cWriteMasters, + mAxiWriteSlaves => i2cWriteSlaves, + mAxiReadMasters => i2cReadMasters, + mAxiReadSlaves => i2cReadSlaves); + + U_PwrI2C : entity surf.AxiI2cRegMaster + generic map ( + TPD_G => TPD_G, + DEVICE_MAP_G => PWR_I2C_C, + I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz + AXI_CLK_FREQ_G => DMA_CLK_FREQ_C) + port map ( + -- I2C Ports + scl => pwrScl, + sda => pwrSda, + -- AXI-Lite Register Interface + axiReadMaster => i2cReadMasters(3), + axiReadSlave => i2cReadSlaves(3), + axiWriteMaster => i2cWriteMasters(3), + axiWriteSlave => i2cWriteSlaves(3), + -- Clocks and Resets + axiClk => sysClock, + axiRst => sysReset); + + U_SFP_I2C : entity surf.AxiI2cRegMaster + generic map ( + TPD_G => TPD_G, + I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz + DEVICE_MAP_G => SFF8472_I2C_CONFIG_C, + AXI_CLK_FREQ_G => DMA_CLK_FREQ_C) + port map ( + -- I2C Ports + scl => sfpScl, + sda => sfpSda, + -- AXI-Lite Register Interface + axiReadMaster => i2cReadMasters(2), + axiReadSlave => i2cReadSlaves(2), + axiWriteMaster => i2cWriteMasters(2), + axiWriteSlave => i2cWriteSlaves(2), + -- Clocks and Resets + axiClk => sysClock, + axiRst => sysReset); + + GEN_QSFP : + for i in 1 downto 0 generate + U_I2C : entity surf.AxiI2cRegMaster + generic map ( + TPD_G => TPD_G, + I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz + DEVICE_MAP_G => SFF8472_I2C_CONFIG_C, + AXI_CLK_FREQ_G => DMA_CLK_FREQ_C) + port map ( + -- I2C Ports + scl => qsfpScl(i), + sda => qsfpSda(i), + -- AXI-Lite Register Interface + axiReadMaster => i2cReadMasters(i), + axiReadSlave => i2cReadSlaves(i), + axiWriteMaster => i2cWriteMasters(i), + axiWriteSlave => i2cWriteSlaves(i), + -- Clocks and Resets + axiClk => sysClock, + axiRst => sysReset); + end generate GEN_QSFP; + end generate; SIM_PCIE : if (ROGUE_SIM_EN_G) generate @@ -242,6 +370,11 @@ begin phyReadSlave => phyReadSlave, phyWriteMaster => phyWriteMaster, phyWriteSlave => phyWriteSlave, + -- I2C AXI-Lite Interfaces (axiClk domain) + i2cReadMaster => i2cReadMaster, + i2cReadSlave => i2cReadSlave, + i2cWriteMaster => i2cWriteMaster, + i2cWriteSlave => i2cWriteSlave, -- (Optional) Application AXI-Lite Interfaces appClk => appClk, appRst => appRst, diff --git a/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4App.xdc b/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4App.xdc index 8054ff85..30df3e52 100644 --- a/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4App.xdc +++ b/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4App.xdc @@ -12,12 +12,6 @@ # System # ########## -set_property -dict { PACKAGE_PIN AJ8 IOSTANDARD LVCMOS33 } [get_ports { qsfpScl[0] }] -set_property -dict { PACKAGE_PIN AN8 IOSTANDARD LVCMOS33 } [get_ports { qsfpSda[0] }] - -set_property -dict { PACKAGE_PIN AP8 IOSTANDARD LVCMOS33 } [get_ports { qsfpScl[1] }] -set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS33 } [get_ports { qsfpSda[1] }] - set_property -dict { PACKAGE_PIN AL9 IOSTANDARD LVCMOS33 } [get_ports { ledRedL[0] }] set_property -dict { PACKAGE_PIN AN9 IOSTANDARD LVCMOS33 } [get_ports { ledBlueL[0] }] set_property -dict { PACKAGE_PIN AP9 IOSTANDARD LVCMOS33 } [get_ports { ledGreenL[0] }] @@ -42,23 +36,10 @@ set_property -dict { PACKAGE_PIN AJ10 IOSTANDARD LVCMOS33 } [get_ports { ledRedL set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS33 } [get_ports { ledBlueL[5] }] set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS33 } [get_ports { ledGreenL[5] }] -set_property -dict { PACKAGE_PIN AP11 IOSTANDARD LVCMOS33 } [get_ports { pwrScl }] -set_property -dict { PACKAGE_PIN AP10 IOSTANDARD LVCMOS33 } [get_ports { pwrSda }] - ####### # SFP # ####### -set_property -dict { PACKAGE_PIN AK8 IOSTANDARD LVCMOS33 } [get_ports { sfpScl }] -set_property -dict { PACKAGE_PIN AL8 IOSTANDARD LVCMOS33 } [get_ports { sfpSda }] - -set_property -dict { PACKAGE_PIN AG11 IOSTANDARD LVCMOS33 } [get_ports { sfpRs[1] }]; # SFP_0 -set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS33 } [get_ports { sfpRxLos }]; # SFP_1 -set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS33 } [get_ports { sfpRs[0] }]; # SFP_2 -set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS33 } [get_ports { sfpAbs }]; # SFP_3 -set_property -dict { PACKAGE_PIN AH12 IOSTANDARD LVCMOS33 } [get_ports { sfpTxDis }]; # SFP_4 -set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVCMOS33 } [get_ports { sfpTxFault }]; # SFP_5 - set_property PACKAGE_PIN K6 [get_ports { sfpRefClkP[0] }] ;# 238 MHz set_property PACKAGE_PIN K5 [get_ports { sfpRefClkN[0] }] ;# 238 MHz diff --git a/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4Core.xdc b/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4Core.xdc index 07c69f81..ac0e9e5e 100644 --- a/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4Core.xdc +++ b/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4Core.xdc @@ -8,6 +8,41 @@ ## the terms contained in the LICENSE.txt file. ############################################################################## +#################### +# I2C: Constraints # +#################### + +set_property -dict { PACKAGE_PIN AP11 IOSTANDARD LVCMOS33 } [get_ports { pwrScl }] +set_property -dict { PACKAGE_PIN AP10 IOSTANDARD LVCMOS33 } [get_ports { pwrSda }] + +set_property -dict { PACKAGE_PIN AJ8 IOSTANDARD LVCMOS33 } [get_ports { qsfpScl[0] }] +set_property -dict { PACKAGE_PIN AN8 IOSTANDARD LVCMOS33 } [get_ports { qsfpSda[0] }] + +set_property -dict { PACKAGE_PIN AP8 IOSTANDARD LVCMOS33 } [get_ports { qsfpScl[1] }] +set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS33 } [get_ports { qsfpSda[1] }] + +set_property -dict { PACKAGE_PIN AK8 IOSTANDARD LVCMOS33 } [get_ports { sfpScl }] +set_property -dict { PACKAGE_PIN AL8 IOSTANDARD LVCMOS33 } [get_ports { sfpSda }] + +set_property -dict { PACKAGE_PIN AG11 IOSTANDARD LVCMOS33 } [get_ports { sfpRs[1] }]; # SFP_0 +set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS33 } [get_ports { sfpRxLos }]; # SFP_1 +set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS33 } [get_ports { sfpRs[0] }]; # SFP_2 +set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS33 } [get_ports { sfpAbs }]; # SFP_3 +set_property -dict { PACKAGE_PIN AH12 IOSTANDARD LVCMOS33 } [get_ports { sfpTxDis }]; # SFP_4 +set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVCMOS33 } [get_ports { sfpTxFault }]; # SFP_5 + +set_property -dict { PACKAGE_PIN AE11 IOSTANDARD LVCMOS33 } [get_ports { qsfpRstL[0] }]; # QSFP0_0 +set_property -dict { PACKAGE_PIN AE12 IOSTANDARD LVCMOS33 } [get_ports { qsfpModSelL[0] }]; # QSFP0_1 +set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS33 } [get_ports { qsfpIntL[0] }]; # QSFP0_2 +set_property -dict { PACKAGE_PIN AH13 IOSTANDARD LVCMOS33 } [get_ports { qsfpModPrsL[0] }]; # QSFP0_3 +set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS33 } [get_ports { qsfpLpMode[0] }]; # QSFP0_4 + +set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports { qsfpRstL[1] }]; # QSFP1_0 +set_property -dict { PACKAGE_PIN AF13 IOSTANDARD LVCMOS33 } [get_ports { qsfpModSelL[1] }]; # QSFP1_1 +set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS33 } [get_ports { qsfpIntL[1] }]; # QSFP1_2 +set_property -dict { PACKAGE_PIN AL13 IOSTANDARD LVCMOS33 } [get_ports { qsfpModPrsL[1] }]; # QSFP1_3 +set_property -dict { PACKAGE_PIN AK12 IOSTANDARD LVCMOS33 } [get_ports { qsfpLpMode[1] }]; # QSFP1_4 + ###################### # FLASH: Constraints # ###################### diff --git a/hardware/XilinxAc701/ruckus.tcl b/hardware/XilinxAc701/ruckus.tcl index 2c111825..9a17e6f2 100644 --- a/hardware/XilinxAc701/ruckus.tcl +++ b/hardware/XilinxAc701/ruckus.tcl @@ -13,7 +13,7 @@ if { $::env(PRJ_PART) != "XC7A200TFBG676-2" } { if { [VersionCheck 2018.2] < 0 } {exit -1} # Set the board part -set_property board_part xilinx.com:ac701:part0:1.3 [current_project] +set_property board_part xilinx.com:ac701:part0:1.4 [current_project] ####################################################################################### # 7-Series PCIe IP core appear to not support 40-bit address (even with 64-bit enabled) diff --git a/hardware/XilinxKc705/ruckus.tcl b/hardware/XilinxKc705/ruckus.tcl index d458887f..8adfa590 100644 --- a/hardware/XilinxKc705/ruckus.tcl +++ b/hardware/XilinxKc705/ruckus.tcl @@ -13,7 +13,7 @@ if { $::env(PRJ_PART) != "XC7K325TFFG900-2" } { if { [VersionCheck 2018.2] < 0 } {exit -1} # Set the board part -set_property board_part xilinx.com:kc705:part0:1.5 [current_project] +set_property board_part xilinx.com:kc705:part0:1.6 [current_project] ####################################################################################### # 7-Series PCIe IP core appear to not support 40-bit address (even with 64-bit enabled) diff --git a/hardware/XilinxKcu105/ruckus.tcl b/hardware/XilinxKcu105/ruckus.tcl index d053d3f3..810c0d11 100644 --- a/hardware/XilinxKcu105/ruckus.tcl +++ b/hardware/XilinxKcu105/ruckus.tcl @@ -13,7 +13,7 @@ if { $::env(PRJ_PART) != "XCKU040-FFVA1156-2-E" } { } # Set the board part -set_property board_part xilinx.com:kcu105:part0:1.3 [current_project] +set_property board_part xilinx.com:kcu105:part0:1.6 [current_project] # Load local Source Code and Constraints loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl" diff --git a/hardware/XilinxKcu116/ruckus.tcl b/hardware/XilinxKcu116/ruckus.tcl index 12875118..61fec94b 100644 --- a/hardware/XilinxKcu116/ruckus.tcl +++ b/hardware/XilinxKcu116/ruckus.tcl @@ -13,7 +13,7 @@ if { $::env(PRJ_PART) != "XCKU5P-FFVB676-2-E" } { } # Set the board part -set_property board_part xilinx.com:kcu116:part0:1.2 [current_project] +set_property board_part xilinx.com:kcu116:part0:1.5 [current_project] # Load local Source Code and Constraints loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl" diff --git a/python/axipcie/_AxiPcieCore.py b/python/axipcie/_AxiPcieCore.py index 62169d28..ec027290 100644 --- a/python/axipcie/_AxiPcieCore.py +++ b/python/axipcie/_AxiPcieCore.py @@ -11,8 +11,11 @@ import pyrogue as pr import surf.axi as axi import surf.devices.micron as micron +import surf.devices.nxp as nxp import surf.xilinx as xil +import surf.devices.transceivers as xceiver + import axipcie import click @@ -23,6 +26,7 @@ def __init__(self, useBpi = False, useSpi = False, numDmaLanes = 1, + boardType = None, **kwargs): super().__init__(description=description, **kwargs) @@ -71,11 +75,43 @@ def __init__(self, # DMA AXI Stream Outbound Monitor self.add(axi.AxiStreamMonAxiL( name = 'DmaObAxisMon', - offset = 0x70000, + offset = 0x68000, numberLanes = self.numDmaLanes, expand = False, )) + # I2C access is slow. So using a AXI-Lite proxy to prevent holding up CPU during a BAR0 memory map transaction + self.add(axi.AxiLiteMasterProxy( + name = 'AxilBridge', + offset = 0x70000, + )) + + # Check for the SLAC GEN4 PGP Card + if boardType == 'SlacPgpCardG4': + + for i in range(2): + self.add(xceiver.Qsfp( + name = f'Qsfp[{i}]', + offset = i*0x1000+0x70000, + memBase = self.AxilBridge.proxy, + enabled = False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline + )) + + self.add(xceiver.Sfp( + name = 'Sfp', + offset = 0x72000, + memBase = self.AxilBridge.proxy, + enabled = False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline + )) + + self.add(nxp.Sa56004x( + name = 'BoardTemp', + description = 'This device monitors the board temperature and FPGA junction temperature', + offset = 0x73000, + memBase = self.AxilBridge.proxy, + enabled = False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline + )) + def _start(self): super()._start() DMA_SIZE_G = self.AxiVersion.DMA_SIZE_G.get() diff --git a/shared/rtl/AxiPcieReg.vhd b/shared/rtl/AxiPcieReg.vhd index 074a7103..10ea8bca 100644 --- a/shared/rtl/AxiPcieReg.vhd +++ b/shared/rtl/AxiPcieReg.vhd @@ -48,8 +48,8 @@ entity AxiPcieReg is regReadSlave : out AxiReadSlaveType; regWriteMaster : in AxiWriteMasterType; regWriteSlave : out AxiWriteSlaveType; - pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; + pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C; -- DMA AXI-Lite Interfaces (axiClk domain) dmaCtrlReadMasters : out AxiLiteReadMasterArray(2 downto 0); dmaCtrlReadSlaves : in AxiLiteReadSlaveArray(2 downto 0); @@ -60,6 +60,11 @@ entity AxiPcieReg is phyReadSlave : in AxiLiteReadSlaveType; phyWriteMaster : out AxiLiteWriteMasterType; phyWriteSlave : in AxiLiteWriteSlaveType; + -- I2C AXI-Lite Interfaces (axiClk domain) + i2cReadMaster : out AxiLiteReadMasterType; + i2cReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; + i2cWriteMaster : out AxiLiteWriteMasterType; + i2cWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C; -- Application AXI-Lite Interfaces [0x00100000:0x00FFFFFF] (appClk domain) appClk : in sl; appRst : in sl; @@ -80,18 +85,16 @@ entity AxiPcieReg is bpiWeL : out sl; bpiTri : out sl; bpiDin : out slv(15 downto 0); - bpiDout : in slv(15 downto 0) := x"FFFF"; + bpiDout : in slv(15 downto 0) := x"FFFF"; -- SPI Boot Memory Ports spiCsL : out slv(1 downto 0); spiSck : out slv(1 downto 0); spiMosi : out slv(1 downto 0); - spiMiso : in slv(1 downto 0) := "11"); + spiMiso : in slv(1 downto 0) := "11"); end AxiPcieReg; architecture mapping of AxiPcieReg is - constant NUM_AXI_MASTERS_C : natural := 12; - constant DMA_INDEX_C : natural := 0; constant PHY_INDEX_C : natural := 1; constant VERSION_INDEX_C : natural := 2; @@ -100,11 +103,14 @@ architecture mapping of AxiPcieReg is constant SPI1_INDEX_C : natural := 5; constant AXIS_MON_IB_C : natural := 6; constant AXIS_MON_OB_C : natural := 7; + constant I2C_INDEX_C : natural := 8; -- constant APP0_INDEX_C : natural := XXX; -- Now used for PIP interface - constant APP1_INDEX_C : natural := 8; - constant APP2_INDEX_C : natural := 9; - constant APP3_INDEX_C : natural := 10; - constant APP4_INDEX_C : natural := 11; + constant APP1_INDEX_C : natural := 9; + constant APP2_INDEX_C : natural := 10; + constant APP3_INDEX_C : natural := 11; + constant APP4_INDEX_C : natural := 12; + + constant NUM_AXI_MASTERS_C : natural := 13; constant AXI_CROSSBAR_MASTERS_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXI_MASTERS_C-1 downto 0) := ( DMA_INDEX_C => ( @@ -133,9 +139,13 @@ architecture mapping of AxiPcieReg is connectivity => x"FFFF"), AXIS_MON_IB_C => ( baseAddr => x"0006_0000", - addrBits => 16, + addrBits => 15, connectivity => x"FFFF"), AXIS_MON_OB_C => ( + baseAddr => x"0006_8000", + addrBits => 15, + connectivity => x"FFFF"), + I2C_INDEX_C => ( baseAddr => x"0007_0000", addrBits => 16, connectivity => x"FFFF"), @@ -532,6 +542,27 @@ begin phyReadMaster <= axilReadMasters(PHY_INDEX_C); axilReadSlaves(PHY_INDEX_C) <= phyReadSlave; + -------------------------- + -- Map the AXI-Lite to I2C + -------------------------- + U_AxiLiteMasterProxy : entity surf.AxiLiteMasterProxy + generic map ( + TPD_G => TPD_G) + port map ( + -- Clocks and Resets + axiClk => axiClk, + axiRst => axiRst, + -- AXI-Lite Register Interface + sAxiReadMaster => axilReadMasters(I2C_INDEX_C), + sAxiReadSlave => axilReadSlaves(I2C_INDEX_C), + sAxiWriteMaster => axilWriteMasters(I2C_INDEX_C), + sAxiWriteSlave => axilWriteSlaves(I2C_INDEX_C), + -- AXI-Lite Register Interface + mAxiReadMaster => i2cReadMaster, + mAxiReadSlave => i2cReadSlave, + mAxiWriteMaster => i2cWriteMaster, + mAxiWriteSlave => i2cWriteSlave); + -------------------------------------- -- Combine APP AXI-Lite buses together -------------------------------------- diff --git a/shared/ruckus.tcl b/shared/ruckus.tcl index 1b793d4a..c5f5569e 100644 --- a/shared/ruckus.tcl +++ b/shared/ruckus.tcl @@ -4,7 +4,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Check for submodule tagging if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } { if { [SubmoduleCheck {ruckus} {2.6.0} ] < 0 } {exit -1} - if { [SubmoduleCheck {surf} {2.7.0} ] < 0 } {exit -1} + if { [SubmoduleCheck {surf} {2.20.0} ] < 0 } {exit -1} } else { puts "\n\n*********************************************************" puts "OVERRIDE_SUBMODULE_LOCKS != 0"