diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd
index 11cdbf8..029f073 100644
--- a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd
+++ b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd
@@ -34,7 +34,7 @@ use unisim.vcomponents.all;
 entity XilinxAlveoU55cCore is
    generic (
       TPD_G                : time                        := 1 ns;
-      SI5394_INIT_FILE_G   : string                      := "none";
+      SI5394_INIT_FILE_G   : string                      := "Si5394A_GT_REFCLK_156MHz.mem";
       ROGUE_SIM_EN_G       : boolean                     := false;
       ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000;
       ROGUE_SIM_CH_COUNT_G : natural range 1 to 256      := 256;
@@ -215,7 +215,7 @@ begin
             TPD_G              => TPD_G,
             MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G,
             I2C_BASE_ADDR_G    => "00",
-            I2C_SCL_FREQ_G     => 400.0E+3,        -- units of Hz
+            I2C_SCL_FREQ_G     => 100.0E+3,        -- units of Hz
             AXIL_CLK_FREQ_G    => DMA_CLK_FREQ_C)  -- units of Hz
          port map (
             -- I2C Ports
diff --git a/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd b/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd
index fdb8dfe..1d54aa8 100644
--- a/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd
+++ b/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd
@@ -34,7 +34,7 @@ use unisim.vcomponents.all;
 entity XilinxAlveoU55cCore is
    generic (
       TPD_G                : time                        := 1 ns;
-      SI5394_INIT_FILE_G   : string                      := "none";
+      SI5394_INIT_FILE_G   : string                      := "Si5394A_GT_REFCLK_156MHz.mem";
       ROGUE_SIM_EN_G       : boolean                     := false;
       ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000;
       ROGUE_SIM_CH_COUNT_G : natural range 1 to 256      := 256;
@@ -215,7 +215,7 @@ begin
             TPD_G              => TPD_G,
             MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G,
             I2C_BASE_ADDR_G    => "00",
-            I2C_SCL_FREQ_G     => 400.0E+3,        -- units of Hz
+            I2C_SCL_FREQ_G     => 100.0E+3,        -- units of Hz
             AXIL_CLK_FREQ_G    => DMA_CLK_FREQ_C)  -- units of Hz
          port map (
             -- I2C Ports
diff --git a/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.csv b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.csv
new file mode 100644
index 0000000..803730d
--- /dev/null
+++ b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.csv
@@ -0,0 +1,503 @@
+Address,Data
+0x0006,0x00
+0x0007,0x29
+0x0008,0x04
+0x000B,0x68
+0x0016,0x02
+0x0017,0xdc
+0x0018,0xff
+0x0019,0xff
+0x001A,0xff
+0x002B,0x02
+0x002C,0x00
+0x002D,0x00
+0x002E,0x00
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x00
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003E,0x00
+0x003F,0x00
+0x0040,0x04
+0x0041,0x00
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x0045,0x0c
+0x0046,0x00
+0x0047,0x00
+0x0048,0x00
+0x0049,0x00
+0x004A,0x00
+0x004B,0x00
+0x004C,0x00
+0x004D,0x00
+0x004E,0x00
+0x004F,0x00
+0x0050,0x0f
+0x0051,0x00
+0x0052,0x00
+0x0053,0x00
+0x0054,0x00
+0x0055,0x00
+0x0056,0x00
+0x0057,0x00
+0x0058,0x00
+0x0059,0x00
+0x005A,0x00
+0x005B,0x00
+0x005C,0x00
+0x005D,0x00
+0x005E,0x00
+0x005F,0x00
+0x0060,0x00
+0x0061,0x00
+0x0062,0x00
+0x0063,0x00
+0x0064,0x00
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x00
+0x009B,0x00
+0x009D,0x00
+0x009E,0x00
+0x00A0,0x00
+0x00A2,0x00
+0x00A9,0x00
+0x00AA,0x00
+0x00AB,0x00
+0x00AC,0x00
+0x00E5,0x01
+0x00EA,0x00
+0x00EB,0x00
+0x00EC,0x00
+0x00ED,0x00
+0x0102,0x01
+0x0112,0x02
+0x0113,0x09
+0x0114,0x3e
+0x0115,0x19
+0x0117,0x02
+0x0118,0x09
+0x0119,0x3e
+0x011A,0x19
+0x0126,0x06
+0x0127,0x09
+0x0128,0x3e
+0x0129,0x18
+0x012B,0x06
+0x012C,0x09
+0x012D,0x3e
+0x012E,0x18
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xff
+0x0206,0x00
+0x0208,0x00
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x00
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x0b
+0x0232,0x0b
+0x0233,0x0b
+0x0234,0x0b
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0xa5
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0x80
+0x0250,0x01
+0x0251,0x00
+0x0252,0x00
+0x0253,0x01
+0x0254,0x00
+0x0255,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x026B,0x00
+0x026C,0x00
+0x026D,0x00
+0x026E,0x00
+0x026F,0x00
+0x0270,0x00
+0x0271,0x00
+0x0272,0x00
+0x028A,0x00
+0x028B,0x00
+0x028C,0x00
+0x028D,0x00
+0x028E,0x00
+0x028F,0x00
+0x0290,0x00
+0x0291,0x00
+0x0292,0x3f
+0x0293,0x2f
+0x0294,0x80
+0x0296,0x00
+0x0297,0x00
+0x0299,0x00
+0x029D,0x00
+0x029E,0x00
+0x029F,0x00
+0x02A9,0x00
+0x02AA,0x00
+0x02AB,0x00
+0x02B7,0xff
+0x02BC,0x00
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x00
+0x0306,0x21
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x10
+0x0312,0x00
+0x0313,0x00
+0x0314,0x7C
+0x0315,0xF0
+0x0316,0xC1
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x0338,0x00
+0x0339,0x1f
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0487,0x00
+0x0508,0x00
+0x0509,0x00
+0x050A,0x00
+0x050B,0x00
+0x050C,0x00
+0x050D,0x00
+0x050E,0x00
+0x050F,0x00
+0x0510,0x00
+0x0511,0x00
+0x0512,0x00
+0x0513,0x00
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0x00
+0x051A,0x00
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x00
+0x0521,0x2b
+0x052A,0x00
+0x052B,0x01
+0x052C,0x0f
+0x052D,0x03
+0x052E,0x00
+0x052F,0x00
+0x0531,0x00
+0x0532,0x00
+0x0533,0x04
+0x0534,0x00
+0x0535,0x01
+0x0536,0x06
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x053D,0x0a
+0x053E,0x06
+0x0588,0x00
+0x0589,0x0c
+0x058A,0x00
+0x058B,0x00
+0x058C,0x00
+0x058D,0x00
+0x059B,0x18
+0x059C,0x0c
+0x059D,0x00
+0x059E,0x00
+0x059F,0x00
+0x05A0,0x00
+0x05A1,0x00
+0x05A2,0x00
+0x05A4,0x20
+0x05A5,0x00
+0x05A6,0x00
+0x05AC,0x00
+0x05AD,0x00
+0x05AE,0x00
+0x05B1,0x00
+0x05B2,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x01
+0x0805,0x00
+0x0806,0x00
+0x0807,0x00
+0x0808,0x00
+0x0809,0x00
+0x080A,0x00
+0x080B,0x00
+0x080C,0x00
+0x080D,0x00
+0x080E,0x00
+0x080F,0x00
+0x0810,0x00
+0x0811,0x00
+0x0812,0x00
+0x0813,0x00
+0x0814,0x00
+0x0815,0x00
+0x0816,0x00
+0x0817,0x00
+0x0818,0x00
+0x0819,0x00
+0x081A,0x00
+0x081B,0x00
+0x081C,0x00
+0x081D,0x00
+0x081E,0x00
+0x081F,0x00
+0x0820,0x00
+0x0821,0x00
+0x0822,0x00
+0x0823,0x00
+0x0824,0x00
+0x0825,0x00
+0x0826,0x00
+0x0827,0x00
+0x0828,0x00
+0x0829,0x00
+0x082A,0x00
+0x082B,0x00
+0x082C,0x00
+0x082D,0x00
+0x082E,0x00
+0x082F,0x00
+0x0830,0x00
+0x0831,0x00
+0x0832,0x00
+0x0833,0x00
+0x0834,0x00
+0x0835,0x00
+0x0836,0x00
+0x0837,0x00
+0x0838,0x00
+0x0839,0x00
+0x083A,0x00
+0x083B,0x00
+0x083C,0x00
+0x083D,0x00
+0x083E,0x00
+0x083F,0x00
+0x0840,0x00
+0x0841,0x00
+0x0842,0x00
+0x0843,0x00
+0x0844,0x00
+0x0845,0x00
+0x0846,0x00
+0x0847,0x00
+0x0848,0x00
+0x0849,0x00
+0x084A,0x00
+0x084B,0x00
+0x084C,0x00
+0x084D,0x00
+0x084E,0x00
+0x084F,0x00
+0x0850,0x00
+0x0851,0x00
+0x0852,0x00
+0x0853,0x00
+0x0854,0x00
+0x0855,0x00
+0x0856,0x00
+0x0857,0x00
+0x0858,0x00
+0x0859,0x00
+0x085A,0x00
+0x085B,0x00
+0x085C,0x00
+0x085D,0x00
+0x085E,0x00
+0x085F,0x00
+0x0860,0x00
+0x0861,0x00
+0x090E,0x03
+0x0943,0x00
+0x0949,0x00
+0x094A,0x00
+0x094E,0x49
+0x094F,0xf2
+0x095E,0x00
+0x0A02,0x00
+0x0A03,0x03
+0x0A04,0x01
+0x0A05,0x03
+0x0A14,0x00
+0x0A1A,0x00
+0x0A20,0x00
+0x0A26,0x00
+0x0A38,0x00
+0x0A39,0x00
+0x0A3A,0x00
+0x0A3C,0x00
+0x0A3D,0x00
+0x0A3E,0x00
+0x0A40,0x00
+0x0A41,0x00
+0x0A42,0x00
+0x0A44,0x00
+0x0A45,0x00
+0x0A46,0x00
+0x0A4C,0x00
+0x0A4D,0x00
+0x0A4E,0x00
+0x0A4F,0x00
+0x0A50,0x00
+0x0A51,0x00
+0x0A52,0x00
+0x0A53,0x00
+0x0A54,0x00
+0x0A55,0x00
+0x0A56,0x00
+0x0A57,0x00
+0x0A58,0x00
+0x0A59,0x00
+0x0A5A,0x00
+0x0A5B,0x00
+0x0B44,0x0f
+0x0B46,0x00
+0x0B47,0x0f
+0x0B48,0x0f
+0x0B4A,0x0c
+0x0B57,0x44
+0x0B58,0x01
+0x0C02,0x03
+0x0C03,0x00
+0x0C07,0x00
+0x0C08,0x00
diff --git a/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.mem b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.mem
new file mode 100644
index 0000000..780c68d
--- /dev/null
+++ b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.mem
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:059e22dec189abe1054ddc14afbd8de732bf0ed8d4c311a5675313da9905e2ca
+size 7168
diff --git a/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.csv b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.csv
new file mode 100644
index 0000000..b361337
--- /dev/null
+++ b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.csv
@@ -0,0 +1,503 @@
+Address,Data
+0x0006,0x00
+0x0007,0x29
+0x0008,0x04
+0x000B,0x68
+0x0016,0x02
+0x0017,0xdc
+0x0018,0xff
+0x0019,0xff
+0x001A,0xff
+0x002B,0x02
+0x002C,0x00
+0x002D,0x00
+0x002E,0x00
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x00
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003E,0x00
+0x003F,0x00
+0x0040,0x04
+0x0041,0x00
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x0045,0x0c
+0x0046,0x00
+0x0047,0x00
+0x0048,0x00
+0x0049,0x00
+0x004A,0x00
+0x004B,0x00
+0x004C,0x00
+0x004D,0x00
+0x004E,0x00
+0x004F,0x00
+0x0050,0x0f
+0x0051,0x00
+0x0052,0x00
+0x0053,0x00
+0x0054,0x00
+0x0055,0x00
+0x0056,0x00
+0x0057,0x00
+0x0058,0x00
+0x0059,0x00
+0x005A,0x00
+0x005B,0x00
+0x005C,0x00
+0x005D,0x00
+0x005E,0x00
+0x005F,0x00
+0x0060,0x00
+0x0061,0x00
+0x0062,0x00
+0x0063,0x00
+0x0064,0x00
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x00
+0x009B,0x00
+0x009D,0x00
+0x009E,0x00
+0x00A0,0x00
+0x00A2,0x00
+0x00A9,0x00
+0x00AA,0x00
+0x00AB,0x00
+0x00AC,0x00
+0x00E5,0x01
+0x00EA,0x00
+0x00EB,0x00
+0x00EC,0x00
+0x00ED,0x00
+0x0102,0x01
+0x0112,0x02
+0x0113,0x09
+0x0114,0x3e
+0x0115,0x19
+0x0117,0x02
+0x0118,0x09
+0x0119,0x3e
+0x011A,0x19
+0x0126,0x06
+0x0127,0x09
+0x0128,0x3e
+0x0129,0x18
+0x012B,0x06
+0x012C,0x09
+0x012D,0x3e
+0x012E,0x18
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xff
+0x0206,0x00
+0x0208,0x00
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x00
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x0b
+0x0232,0x0b
+0x0233,0x0b
+0x0234,0x0b
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0xa5
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0x80
+0x0250,0x01
+0x0251,0x00
+0x0252,0x00
+0x0253,0x01
+0x0254,0x00
+0x0255,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x026B,0x00
+0x026C,0x00
+0x026D,0x00
+0x026E,0x00
+0x026F,0x00
+0x0270,0x00
+0x0271,0x00
+0x0272,0x00
+0x028A,0x00
+0x028B,0x00
+0x028C,0x00
+0x028D,0x00
+0x028E,0x00
+0x028F,0x00
+0x0290,0x00
+0x0291,0x00
+0x0292,0x3f
+0x0293,0x2f
+0x0294,0x80
+0x0296,0x00
+0x0297,0x00
+0x0299,0x00
+0x029D,0x00
+0x029E,0x00
+0x029F,0x00
+0x02A9,0x00
+0x02AA,0x00
+0x02AB,0x00
+0x02B7,0xff
+0x02BC,0x00
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x00
+0x0306,0x21
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x10
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0xc8
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x0338,0x00
+0x0339,0x1f
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0487,0x00
+0x0508,0x00
+0x0509,0x00
+0x050A,0x00
+0x050B,0x00
+0x050C,0x00
+0x050D,0x00
+0x050E,0x00
+0x050F,0x00
+0x0510,0x00
+0x0511,0x00
+0x0512,0x00
+0x0513,0x00
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0x00
+0x051A,0x00
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x00
+0x0521,0x2b
+0x052A,0x00
+0x052B,0x01
+0x052C,0x0f
+0x052D,0x03
+0x052E,0x00
+0x052F,0x00
+0x0531,0x00
+0x0532,0x00
+0x0533,0x04
+0x0534,0x00
+0x0535,0x01
+0x0536,0x06
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x053D,0x0a
+0x053E,0x06
+0x0588,0x00
+0x0589,0x0c
+0x058A,0x00
+0x058B,0x00
+0x058C,0x00
+0x058D,0x00
+0x059B,0x18
+0x059C,0x0c
+0x059D,0x00
+0x059E,0x00
+0x059F,0x00
+0x05A0,0x00
+0x05A1,0x00
+0x05A2,0x00
+0x05A4,0x20
+0x05A5,0x00
+0x05A6,0x00
+0x05AC,0x00
+0x05AD,0x00
+0x05AE,0x00
+0x05B1,0x00
+0x05B2,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x01
+0x0805,0x00
+0x0806,0x00
+0x0807,0x00
+0x0808,0x00
+0x0809,0x00
+0x080A,0x00
+0x080B,0x00
+0x080C,0x00
+0x080D,0x00
+0x080E,0x00
+0x080F,0x00
+0x0810,0x00
+0x0811,0x00
+0x0812,0x00
+0x0813,0x00
+0x0814,0x00
+0x0815,0x00
+0x0816,0x00
+0x0817,0x00
+0x0818,0x00
+0x0819,0x00
+0x081A,0x00
+0x081B,0x00
+0x081C,0x00
+0x081D,0x00
+0x081E,0x00
+0x081F,0x00
+0x0820,0x00
+0x0821,0x00
+0x0822,0x00
+0x0823,0x00
+0x0824,0x00
+0x0825,0x00
+0x0826,0x00
+0x0827,0x00
+0x0828,0x00
+0x0829,0x00
+0x082A,0x00
+0x082B,0x00
+0x082C,0x00
+0x082D,0x00
+0x082E,0x00
+0x082F,0x00
+0x0830,0x00
+0x0831,0x00
+0x0832,0x00
+0x0833,0x00
+0x0834,0x00
+0x0835,0x00
+0x0836,0x00
+0x0837,0x00
+0x0838,0x00
+0x0839,0x00
+0x083A,0x00
+0x083B,0x00
+0x083C,0x00
+0x083D,0x00
+0x083E,0x00
+0x083F,0x00
+0x0840,0x00
+0x0841,0x00
+0x0842,0x00
+0x0843,0x00
+0x0844,0x00
+0x0845,0x00
+0x0846,0x00
+0x0847,0x00
+0x0848,0x00
+0x0849,0x00
+0x084A,0x00
+0x084B,0x00
+0x084C,0x00
+0x084D,0x00
+0x084E,0x00
+0x084F,0x00
+0x0850,0x00
+0x0851,0x00
+0x0852,0x00
+0x0853,0x00
+0x0854,0x00
+0x0855,0x00
+0x0856,0x00
+0x0857,0x00
+0x0858,0x00
+0x0859,0x00
+0x085A,0x00
+0x085B,0x00
+0x085C,0x00
+0x085D,0x00
+0x085E,0x00
+0x085F,0x00
+0x0860,0x00
+0x0861,0x00
+0x090E,0x03
+0x0943,0x00
+0x0949,0x00
+0x094A,0x00
+0x094E,0x49
+0x094F,0xf2
+0x095E,0x00
+0x0A02,0x00
+0x0A03,0x03
+0x0A04,0x01
+0x0A05,0x03
+0x0A14,0x00
+0x0A1A,0x00
+0x0A20,0x00
+0x0A26,0x00
+0x0A38,0x00
+0x0A39,0x00
+0x0A3A,0x00
+0x0A3C,0x00
+0x0A3D,0x00
+0x0A3E,0x00
+0x0A40,0x00
+0x0A41,0x00
+0x0A42,0x00
+0x0A44,0x00
+0x0A45,0x00
+0x0A46,0x00
+0x0A4C,0x00
+0x0A4D,0x00
+0x0A4E,0x00
+0x0A4F,0x00
+0x0A50,0x00
+0x0A51,0x00
+0x0A52,0x00
+0x0A53,0x00
+0x0A54,0x00
+0x0A55,0x00
+0x0A56,0x00
+0x0A57,0x00
+0x0A58,0x00
+0x0A59,0x00
+0x0A5A,0x00
+0x0A5B,0x00
+0x0B44,0x0f
+0x0B46,0x00
+0x0B47,0x0f
+0x0B48,0x0f
+0x0B4A,0x0c
+0x0B57,0x44
+0x0B58,0x01
+0x0C02,0x03
+0x0C03,0x00
+0x0C07,0x00
+0x0C08,0x00
diff --git a/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.mem b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.mem
new file mode 100644
index 0000000..a94fc7b
--- /dev/null
+++ b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.mem
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:2b39c1903e47755682b1191bda28555db41ad033d28236e158b51ac42203b029
+size 7168
diff --git a/hardware/XilinxAlveoU55c/ruckus.tcl b/hardware/XilinxAlveoU55c/ruckus.tcl
index 2c4adc4..0cf816c 100644
--- a/hardware/XilinxAlveoU55c/ruckus.tcl
+++ b/hardware/XilinxAlveoU55c/ruckus.tcl
@@ -32,3 +32,7 @@ loadConstraints               -path "$::DIR_PATH/xdc/XilinxAlveoU55cApp.xdc"
 
 # Load the PCIe core
 loadRuckusTcl "$::DIR_PATH/${pcieType}"
+
+# Adding the Si5345 configurations
+add_files -norecurse "$::DIR_PATH/pll-config/Si5394A_GT_REFCLK_156MHz.mem"
+add_files -norecurse "$::DIR_PATH/pll-config/Si5394A_GT_REFCLK_161MHz.mem"
diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc
index 3c56893..a3f0a46 100644
--- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc
+++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc
@@ -70,8 +70,8 @@ set_property PACKAGE_PIN V52 [get_ports { qsfp1RxN[3] }]
 # Clocks #
 ##########
 
-create_clock -period 6.206 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# 161.1328125 MHz
-create_clock -period 6.206 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# 161.1328125 MHz
+create_clock -period 6.4 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# SI5394_INIT_FILE_G="Si5394A_GT_REFCLK_156MHz.mem"
+create_clock -period 6.4 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# SI5394_INIT_FILE_G="Si5394A_GT_REFCLK_156MHz.mem"
 
 set_clock_groups -asynchronous \
    -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] \
diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc
index 38eb4d1..13e112e 100644
--- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc
+++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc
@@ -22,12 +22,21 @@ set_property -dict { PACKAGE_PIN BL10 IOSTANDARD LVDS } [get_ports { userClkN }]
 set_property -dict { PACKAGE_PIN BK43 IOSTANDARD LVDS } [get_ports { hbmRefClkP }]
 set_property -dict { PACKAGE_PIN BK44 IOSTANDARD LVDS } [get_ports { hbmRefClkN }]
 
-set_property -dict { PACKAGE_PIN BM14 IOSTANDARD LVCMOS18 } [get_ports { si5394Scl }]
-set_property -dict { PACKAGE_PIN BN14 IOSTANDARD LVCMOS18 } [get_ports { si5394Sda }]
-set_property -dict { PACKAGE_PIN BM9  IOSTANDARD LVCMOS18 } [get_ports { si5394IrqL }]
-set_property -dict { PACKAGE_PIN BN10 IOSTANDARD LVCMOS18 } [get_ports { si5394LolL }]
-set_property -dict { PACKAGE_PIN BM10 IOSTANDARD LVCMOS18 } [get_ports { si5394LosL }]
-set_property -dict { PACKAGE_PIN BM8  IOSTANDARD LVCMOS18 } [get_ports { si5394RstL }]
+####################################################################################
+# I2C_SI5394_SCLK    Master I2C clock connection from FPGA to Si5394B
+# I2C_SI5394_SDA     Master I2C data connection from FPGA to Si5394B
+# SI_INTRB           Active low interrupt output from Si5394B to FPGA input
+# SI_PLL_LOCK        Active low PLL Loss of Lock output from Si5394B to FPGA input
+# SI_IN_LOS          Active low PLL Loss of Signal output from Si5394B to FPGA input
+# SI_RSTBB           Active low reset output from FPGA to Si5394B input
+####################################################################################
+
+set_property -dict { PACKAGE_PIN BM14 IOSTANDARD LVCMOS18 } [get_ports { si5394Scl }] ;# Bank  68 VCCO - VCC1V8   - IO_L5P_T0U_N8_AD14P_68
+set_property -dict { PACKAGE_PIN BN14 IOSTANDARD LVCMOS18 } [get_ports { si5394Sda }] ;# Bank  68 VCCO - VCC1V8   - IO_L4N_T0U_N7_DBC_AD7N_68
+set_property -dict { PACKAGE_PIN BM9  IOSTANDARD LVCMOS18 } [get_ports { si5394IrqL }] ;# Bank  68 VCCO - VCC1V8   - IO_L9P_T1L_N4_AD12P_68
+set_property -dict { PACKAGE_PIN BN10 IOSTANDARD LVCMOS18 } [get_ports { si5394LolL }] ;# Bank  68 VCCO - VCC1V8   - IO_L8N_T1L_N3_AD5N_68
+set_property -dict { PACKAGE_PIN BM10 IOSTANDARD LVCMOS18 } [get_ports { si5394LosL }] ;# Bank  68 VCCO - VCC1V8   - IO_L8P_T1L_N2_AD5P_68
+set_property -dict { PACKAGE_PIN BM8  IOSTANDARD LVCMOS18 } [get_ports { si5394RstL }] ;# Bank  68 VCCO - VCC1V8   - IO_L10N_T1U_N7_QBC_AD4N_68
 
 ####################
 # PCIe Constraints #
diff --git a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd
index e26522e..5c84a5c 100644
--- a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd
+++ b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd
@@ -34,7 +34,7 @@ use unisim.vcomponents.all;
 entity XilinxVariumC1100Core is
    generic (
       TPD_G                : time                        := 1 ns;
-      SI5394_INIT_FILE_G   : string                      := "none";
+      SI5394_INIT_FILE_G   : string                      := "Si5394A_GT_REFCLK_156MHz.mem";
       ROGUE_SIM_EN_G       : boolean                     := false;
       ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000;
       ROGUE_SIM_CH_COUNT_G : natural range 1 to 256      := 256;
@@ -215,7 +215,7 @@ begin
             TPD_G              => TPD_G,
             MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G,
             I2C_BASE_ADDR_G    => "00",
-            I2C_SCL_FREQ_G     => 400.0E+3,        -- units of Hz
+            I2C_SCL_FREQ_G     => 100.0E+3,        -- units of Hz
             AXIL_CLK_FREQ_G    => DMA_CLK_FREQ_C)  -- units of Hz
          port map (
             -- I2C Ports
diff --git a/hardware/XilinxVariumC1100/pcie-4x8/rtl/XilinxVariumC1100Core.vhd b/hardware/XilinxVariumC1100/pcie-4x8/rtl/XilinxVariumC1100Core.vhd
index 24062b2..5cd42f9 100644
--- a/hardware/XilinxVariumC1100/pcie-4x8/rtl/XilinxVariumC1100Core.vhd
+++ b/hardware/XilinxVariumC1100/pcie-4x8/rtl/XilinxVariumC1100Core.vhd
@@ -34,7 +34,7 @@ use unisim.vcomponents.all;
 entity XilinxVariumC1100Core is
    generic (
       TPD_G                : time                        := 1 ns;
-      SI5394_INIT_FILE_G   : string                      := "none";
+      SI5394_INIT_FILE_G   : string                      := "Si5394A_GT_REFCLK_156MHz.mem";
       ROGUE_SIM_EN_G       : boolean                     := false;
       ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000;
       ROGUE_SIM_CH_COUNT_G : natural range 1 to 256      := 256;
@@ -215,7 +215,7 @@ begin
             TPD_G              => TPD_G,
             MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G,
             I2C_BASE_ADDR_G    => "00",
-            I2C_SCL_FREQ_G     => 400.0E+3,        -- units of Hz
+            I2C_SCL_FREQ_G     => 100.0E+3,        -- units of Hz
             AXIL_CLK_FREQ_G    => DMA_CLK_FREQ_C)  -- units of Hz
          port map (
             -- I2C Ports
diff --git a/hardware/XilinxVariumC1100/ruckus.tcl b/hardware/XilinxVariumC1100/ruckus.tcl
index df802df..5174a3f 100644
--- a/hardware/XilinxVariumC1100/ruckus.tcl
+++ b/hardware/XilinxVariumC1100/ruckus.tcl
@@ -38,3 +38,7 @@ loadSource -lib axi_pcie_core -path "$::DIR_PATH/hbm/HbmAxiFifo.dcp"
 
 # Load the PCIe core
 loadRuckusTcl "$::DIR_PATH/${pcieType}"
+
+# Adding the Si5345 configurations
+add_files -norecurse "$::DIR_PATH/../XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.mem"
+add_files -norecurse "$::DIR_PATH/../XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.mem"