From 3ab27a3486f31f3b833a88b7d9d401f8b380773a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 11 May 2023 16:05:49 -0700 Subject: [PATCH] updating XilinxVariumC1100 & XilinxAlveoU55c to boot with 156.25 MHz QSFP GT clk --- .../pcie-3x16/rtl/XilinxAlveoU55cCore.vhd | 4 +- .../pcie-4x8/rtl/XilinxAlveoU55cCore.vhd | 4 +- .../pll-config/Si5394A_GT_REFCLK_156MHz.csv | 503 ++++++++++++++++++ .../pll-config/Si5394A_GT_REFCLK_156MHz.mem | 3 + .../pll-config/Si5394A_GT_REFCLK_161MHz.csv | 503 ++++++++++++++++++ .../pll-config/Si5394A_GT_REFCLK_161MHz.mem | 3 + hardware/XilinxAlveoU55c/ruckus.tcl | 4 + .../xdc/XilinxAlveoU55cApp.xdc | 4 +- .../xdc/XilinxAlveoU55cCore.xdc | 21 +- .../pcie-3x16/rtl/XilinxVariumC1100Core.vhd | 4 +- .../pcie-4x8/rtl/XilinxVariumC1100Core.vhd | 4 +- hardware/XilinxVariumC1100/ruckus.tcl | 4 + 12 files changed, 1045 insertions(+), 16 deletions(-) create mode 100644 hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.csv create mode 100644 hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.mem create mode 100644 hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.csv create mode 100644 hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.mem diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd index 11cdbf8..029f073 100644 --- a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd +++ b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd @@ -34,7 +34,7 @@ use unisim.vcomponents.all; entity XilinxAlveoU55cCore is generic ( TPD_G : time := 1 ns; - SI5394_INIT_FILE_G : string := "none"; + SI5394_INIT_FILE_G : string := "Si5394A_GT_REFCLK_156MHz.mem"; ROGUE_SIM_EN_G : boolean := false; ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000; ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256; @@ -215,7 +215,7 @@ begin TPD_G => TPD_G, MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G, I2C_BASE_ADDR_G => "00", - I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz + I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C) -- units of Hz port map ( -- I2C Ports diff --git a/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd b/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd index fdb8dfe..1d54aa8 100644 --- a/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd +++ b/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd @@ -34,7 +34,7 @@ use unisim.vcomponents.all; entity XilinxAlveoU55cCore is generic ( TPD_G : time := 1 ns; - SI5394_INIT_FILE_G : string := "none"; + SI5394_INIT_FILE_G : string := "Si5394A_GT_REFCLK_156MHz.mem"; ROGUE_SIM_EN_G : boolean := false; ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000; ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256; @@ -215,7 +215,7 @@ begin TPD_G => TPD_G, MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G, I2C_BASE_ADDR_G => "00", - I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz + I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C) -- units of Hz port map ( -- I2C Ports diff --git a/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.csv b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.csv new file mode 100644 index 0000000..803730d --- /dev/null +++ b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.csv @@ -0,0 +1,503 @@ +Address,Data +0x0006,0x00 +0x0007,0x29 +0x0008,0x04 +0x000B,0x68 +0x0016,0x02 +0x0017,0xdc +0x0018,0xff +0x0019,0xff +0x001A,0xff +0x002B,0x02 +0x002C,0x00 +0x002D,0x00 +0x002E,0x00 +0x002F,0x00 +0x0030,0x00 +0x0031,0x00 +0x0032,0x00 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0x00 +0x0037,0x00 +0x0038,0x00 +0x0039,0x00 +0x003A,0x00 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x003E,0x00 +0x003F,0x00 +0x0040,0x04 +0x0041,0x00 +0x0042,0x00 +0x0043,0x00 +0x0044,0x00 +0x0045,0x0c +0x0046,0x00 +0x0047,0x00 +0x0048,0x00 +0x0049,0x00 +0x004A,0x00 +0x004B,0x00 +0x004C,0x00 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a/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.mem b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.mem new file mode 100644 index 0000000..780c68d --- /dev/null +++ b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.mem @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:059e22dec189abe1054ddc14afbd8de732bf0ed8d4c311a5675313da9905e2ca +size 7168 diff --git a/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.csv b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.csv new file mode 100644 index 0000000..b361337 --- /dev/null +++ b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.csv @@ -0,0 +1,503 @@ +Address,Data +0x0006,0x00 +0x0007,0x29 +0x0008,0x04 +0x000B,0x68 +0x0016,0x02 +0x0017,0xdc +0x0018,0xff +0x0019,0xff +0x001A,0xff +0x002B,0x02 +0x002C,0x00 +0x002D,0x00 +0x002E,0x00 +0x002F,0x00 +0x0030,0x00 +0x0031,0x00 +0x0032,0x00 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0x00 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+0x0A54,0x00 +0x0A55,0x00 +0x0A56,0x00 +0x0A57,0x00 +0x0A58,0x00 +0x0A59,0x00 +0x0A5A,0x00 +0x0A5B,0x00 +0x0B44,0x0f +0x0B46,0x00 +0x0B47,0x0f +0x0B48,0x0f +0x0B4A,0x0c +0x0B57,0x44 +0x0B58,0x01 +0x0C02,0x03 +0x0C03,0x00 +0x0C07,0x00 +0x0C08,0x00 diff --git a/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.mem b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.mem new file mode 100644 index 0000000..a94fc7b --- /dev/null +++ b/hardware/XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.mem @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2b39c1903e47755682b1191bda28555db41ad033d28236e158b51ac42203b029 +size 7168 diff --git a/hardware/XilinxAlveoU55c/ruckus.tcl b/hardware/XilinxAlveoU55c/ruckus.tcl index 2c4adc4..0cf816c 100644 --- a/hardware/XilinxAlveoU55c/ruckus.tcl +++ b/hardware/XilinxAlveoU55c/ruckus.tcl @@ -32,3 +32,7 @@ loadConstraints -path "$::DIR_PATH/xdc/XilinxAlveoU55cApp.xdc" # Load the PCIe core loadRuckusTcl "$::DIR_PATH/${pcieType}" + +# Adding the Si5345 configurations +add_files -norecurse "$::DIR_PATH/pll-config/Si5394A_GT_REFCLK_156MHz.mem" +add_files -norecurse "$::DIR_PATH/pll-config/Si5394A_GT_REFCLK_161MHz.mem" diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc index 3c56893..a3f0a46 100644 --- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc +++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cApp.xdc @@ -70,8 +70,8 @@ set_property PACKAGE_PIN V52 [get_ports { qsfp1RxN[3] }] # Clocks # ########## -create_clock -period 6.206 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# 161.1328125 MHz -create_clock -period 6.206 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# 161.1328125 MHz +create_clock -period 6.4 -name qsfp0RefClkP [get_ports {qsfp0RefClkP}] ;# SI5394_INIT_FILE_G="Si5394A_GT_REFCLK_156MHz.mem" +create_clock -period 6.4 -name qsfp1RefClkP [get_ports {qsfp1RefClkP}] ;# SI5394_INIT_FILE_G="Si5394A_GT_REFCLK_156MHz.mem" set_clock_groups -asynchronous \ -group [get_clocks -include_generated_clocks {qsfp0RefClkP}] \ diff --git a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc index 38eb4d1..13e112e 100644 --- a/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc +++ b/hardware/XilinxAlveoU55c/xdc/XilinxAlveoU55cCore.xdc @@ -22,12 +22,21 @@ set_property -dict { PACKAGE_PIN BL10 IOSTANDARD LVDS } [get_ports { userClkN }] set_property -dict { PACKAGE_PIN BK43 IOSTANDARD LVDS } [get_ports { hbmRefClkP }] set_property -dict { PACKAGE_PIN BK44 IOSTANDARD LVDS } [get_ports { hbmRefClkN }] -set_property -dict { PACKAGE_PIN BM14 IOSTANDARD LVCMOS18 } [get_ports { si5394Scl }] -set_property -dict { PACKAGE_PIN BN14 IOSTANDARD LVCMOS18 } [get_ports { si5394Sda }] -set_property -dict { PACKAGE_PIN BM9 IOSTANDARD LVCMOS18 } [get_ports { si5394IrqL }] -set_property -dict { PACKAGE_PIN BN10 IOSTANDARD LVCMOS18 } [get_ports { si5394LolL }] -set_property -dict { PACKAGE_PIN BM10 IOSTANDARD LVCMOS18 } [get_ports { si5394LosL }] -set_property -dict { PACKAGE_PIN BM8 IOSTANDARD LVCMOS18 } [get_ports { si5394RstL }] +#################################################################################### +# I2C_SI5394_SCLK Master I2C clock connection from FPGA to Si5394B +# I2C_SI5394_SDA Master I2C data connection from FPGA to Si5394B +# SI_INTRB Active low interrupt output from Si5394B to FPGA input +# SI_PLL_LOCK Active low PLL Loss of Lock output from Si5394B to FPGA input +# SI_IN_LOS Active low PLL Loss of Signal output from Si5394B to FPGA input +# SI_RSTBB Active low reset output from FPGA to Si5394B input +#################################################################################### + +set_property -dict { PACKAGE_PIN BM14 IOSTANDARD LVCMOS18 } [get_ports { si5394Scl }] ;# Bank 68 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_68 +set_property -dict { PACKAGE_PIN BN14 IOSTANDARD LVCMOS18 } [get_ports { si5394Sda }] ;# Bank 68 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_68 +set_property -dict { PACKAGE_PIN BM9 IOSTANDARD LVCMOS18 } [get_ports { si5394IrqL }] ;# Bank 68 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_68 +set_property -dict { PACKAGE_PIN BN10 IOSTANDARD LVCMOS18 } [get_ports { si5394LolL }] ;# Bank 68 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_68 +set_property -dict { PACKAGE_PIN BM10 IOSTANDARD LVCMOS18 } [get_ports { si5394LosL }] ;# Bank 68 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_68 +set_property -dict { PACKAGE_PIN BM8 IOSTANDARD LVCMOS18 } [get_ports { si5394RstL }] ;# Bank 68 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_68 #################### # PCIe Constraints # diff --git a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd index e26522e..5c84a5c 100644 --- a/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd +++ b/hardware/XilinxVariumC1100/pcie-3x16/rtl/XilinxVariumC1100Core.vhd @@ -34,7 +34,7 @@ use unisim.vcomponents.all; entity XilinxVariumC1100Core is generic ( TPD_G : time := 1 ns; - SI5394_INIT_FILE_G : string := "none"; + SI5394_INIT_FILE_G : string := "Si5394A_GT_REFCLK_156MHz.mem"; ROGUE_SIM_EN_G : boolean := false; ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000; ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256; @@ -215,7 +215,7 @@ begin TPD_G => TPD_G, MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G, I2C_BASE_ADDR_G => "00", - I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz + I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C) -- units of Hz port map ( -- I2C Ports diff --git a/hardware/XilinxVariumC1100/pcie-4x8/rtl/XilinxVariumC1100Core.vhd b/hardware/XilinxVariumC1100/pcie-4x8/rtl/XilinxVariumC1100Core.vhd index 24062b2..5cd42f9 100644 --- a/hardware/XilinxVariumC1100/pcie-4x8/rtl/XilinxVariumC1100Core.vhd +++ b/hardware/XilinxVariumC1100/pcie-4x8/rtl/XilinxVariumC1100Core.vhd @@ -34,7 +34,7 @@ use unisim.vcomponents.all; entity XilinxVariumC1100Core is generic ( TPD_G : time := 1 ns; - SI5394_INIT_FILE_G : string := "none"; + SI5394_INIT_FILE_G : string := "Si5394A_GT_REFCLK_156MHz.mem"; ROGUE_SIM_EN_G : boolean := false; ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000; ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256; @@ -215,7 +215,7 @@ begin TPD_G => TPD_G, MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G, I2C_BASE_ADDR_G => "00", - I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz + I2C_SCL_FREQ_G => 100.0E+3, -- units of Hz AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C) -- units of Hz port map ( -- I2C Ports diff --git a/hardware/XilinxVariumC1100/ruckus.tcl b/hardware/XilinxVariumC1100/ruckus.tcl index df802df..5174a3f 100644 --- a/hardware/XilinxVariumC1100/ruckus.tcl +++ b/hardware/XilinxVariumC1100/ruckus.tcl @@ -38,3 +38,7 @@ loadSource -lib axi_pcie_core -path "$::DIR_PATH/hbm/HbmAxiFifo.dcp" # Load the PCIe core loadRuckusTcl "$::DIR_PATH/${pcieType}" + +# Adding the Si5345 configurations +add_files -norecurse "$::DIR_PATH/../XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_156MHz.mem" +add_files -norecurse "$::DIR_PATH/../XilinxAlveoU55c/pll-config/Si5394A_GT_REFCLK_161MHz.mem"