diff --git a/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4App.xdc b/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4App.xdc index f147f061..97eb2c3b 100644 --- a/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4App.xdc +++ b/hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4App.xdc @@ -66,9 +66,9 @@ set_property PACKAGE_PIN H6 [get_ports { sfpRefClkP[1] }] ;# 371.428571 MHz set_property PACKAGE_PIN H5 [get_ports { sfpRefClkN[1] }] ;# 371.428571 MHz set_property PACKAGE_PIN F6 [get_ports { sfpTxP }] -set_property PACKAGE_PIN F5 [get_ports { sfpRxP }] -set_property PACKAGE_PIN E4 [get_ports { sfpRxN }] -set_property PACKAGE_PIN E3 [get_ports { sfpTxN }] +set_property PACKAGE_PIN F5 [get_ports { sfpTxN }] +set_property PACKAGE_PIN E4 [get_ports { sfpRxP }] +set_property PACKAGE_PIN E3 [get_ports { sfpRxN }] ############# # QSFP[1:0] # diff --git a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncCore.vhd b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncCore.vhd index 6604be3b..d2bcb4b2 100644 --- a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncCore.vhd +++ b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncCore.vhd @@ -67,7 +67,7 @@ architecture mapping of AxiPcieGpuAsyncCore is TDATA_BYTES_C => AXI_PCIE_CONFIG_C.DATA_BYTES_C, -- Match the AXI and AXIS widths for M_AXI port TDEST_BITS_C => 8, TID_BITS_C => 8, - TKEEP_MODE_C => TKEEP_COMP_C, + TKEEP_MODE_C => TKEEP_COUNT_C, -- AXI DMA V2 uses TKEEP_COUNT_C to help meet timing TUSER_BITS_C => 8, TUSER_MODE_C => TUSER_FIRST_LAST_C); diff --git a/python/axipcie/_AxiPcieCore.py b/python/axipcie/_AxiPcieCore.py index 4990ddcf..09cc8480 100644 --- a/python/axipcie/_AxiPcieCore.py +++ b/python/axipcie/_AxiPcieCore.py @@ -14,200 +14,11 @@ import surf.devices.micron as micron import surf.xilinx as xil -class PcieAxiVersion(axi.AxiVersion): - def __init__(self, - name = 'AxiVersion', - description = 'AXI-Lite Version Module', - numUserConstants = 0, - **kwargs): - super().__init__( - name = name, - description = description, - **kwargs - ) - - self.add(pr.RemoteVariable( - name = 'DMA_SIZE_G', - offset = 0x400+(4*0), - bitSize = 32, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'Reserved', - offset = 0x400+(4*1), - bitSize = 32, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'DRIVER_TYPE_ID_G', - offset = 0x400+(4*2), - bitSize = 32, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'XIL_DEVICE_G', - offset = 0x400+(4*3), - bitSize = 32, - mode = 'RO', - enum = { - 0x0: 'ULTRASCALE', - 0x1: '7SERIES', - }, - )) - - self.add(pr.RemoteVariable( - name = 'DMA_CLK_FREQ_C', - offset = 0x400+(4*4), - bitSize = 32, - mode = 'RO', - disp = '{:d}', - units = 'Hz', - )) +import axipcie - self.add(pr.RemoteVariable( - name = 'BOOT_PROM_G', - offset = 0x400+(4*5), - bitSize = 32, - mode = 'RO', - enum = { - 0x0: 'BPI', - 0x1: 'SPIx8', - 0x2: 'SPIx4', - }, - )) - - self.add(pr.RemoteVariable( - name = 'DMA_AXIS_CONFIG_G_TDATA_BYTES_C', - offset = 0x400+(4*6), - bitSize = 8, - bitOffset = 24, - mode = 'RO', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'DMA_AXIS_CONFIG_G_TDEST_BITS_C', - offset = 0x400+(4*6), - bitSize = 4, - bitOffset = 20, - mode = 'RO', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'DMA_AXIS_CONFIG_G_TUSER_BITS_C', - offset = 0x400+(4*6), - bitSize = 4, - bitOffset = 16, - mode = 'RO', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'DMA_AXIS_CONFIG_G_TID_BITS_C', - offset = 0x400+(4*6), - bitSize = 4, - bitOffset = 12, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'DMA_AXIS_CONFIG_G_TKEEP_MODE_C', - offset = 0x400+(4*6), - bitSize = 4, - bitOffset = 8, - mode = 'RO', - enum = { - 0x0: 'TKEEP_NORMAL_C', - 0x1: 'TKEEP_COMP_C', - 0x2: 'TKEEP_FIXED_C', - 0x3: 'TKEEP_COUNT_C', - }, - )) - - self.add(pr.RemoteVariable( - name = 'DMA_AXIS_CONFIG_G_TUSER_MODE_C', - offset = 0x400+(4*6), - bitSize = 4, - bitOffset = 4, - mode = 'RO', - enum = { - 0x0: 'TUSER_NORMAL_C', - 0x1: 'TUSER_FIRST_LAST_C', - 0x2: 'TUSER_LAST_C', - 0x3: 'TUSER_NONE_C', - }, - )) - - self.add(pr.RemoteVariable( - name = 'DMA_AXIS_CONFIG_G_TSTRB_EN_C', - offset = 0x400+(4*6), - bitSize = 1, - bitOffset = 1, - mode = 'RO', - base = pr.Bool, - )) - - self.add(pr.RemoteVariable( - name = 'AppReset', - offset = 0x400+(4*6), - bitSize = 1, - bitOffset = 0, - mode = 'RO', - base = pr.Bool, - pollInterval = 1, - )) - - self.add(pr.RemoteVariable( - name = 'AXI_PCIE_CONFIG_C_ADDR_WIDTH_C', - offset = 0x400+(4*7), - bitSize = 8, - bitOffset = 24, - mode = 'RO', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'AXI_PCIE_CONFIG_C_DATA_BYTES_C', - offset = 0x400+(4*7), - bitSize = 8, - bitOffset = 16, - mode = 'RO', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'AXI_PCIE_CONFIG_C_ID_BITS_C', - offset = 0x400+(4*7), - bitSize = 8, - bitOffset = 8, - mode = 'RO', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'AXI_PCIE_CONFIG_C_LEN_BITS_C', - offset = 0x400+(4*7), - bitSize = 8, - bitOffset = 0, - mode = 'RO', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = "AppClkFreq", - description = "Application Clock Frequency", - offset = 0x400+(4*8), - units = 'Hz', - disp = '{:d}', - mode = "RO", - pollInterval = 1 - )) class AxiPcieCore(pr.Device): + """This class maps to axi-pcie-core/shared/rtl/AxiPcieReg.vhd""" def __init__(self, description = 'Base components of the PCIe firmware core', useBpi = False, @@ -223,7 +34,7 @@ def __init__(self, )) # AxiVersion Module - self.add(PcieAxiVersion( + self.add(axipcie.PcieAxiVersion( offset = 0x20000, expand = False, )) diff --git a/python/axipcie/_AxiPcieDma.py b/python/axipcie/_AxiPcieDma.py new file mode 100644 index 00000000..fa7f9aba --- /dev/null +++ b/python/axipcie/_AxiPcieDma.py @@ -0,0 +1,27 @@ +import rogue +from collections import defaultdict + +def createAxiPcieMemMap(driverPath, host='localhost', port=8000): + """Provides BAR0 access to AxiPcieCore""" + if driverPath != 'sim': + return rogue.hardware.axi.AxiMemMap(driverPath) + else: + return rogue.interfaces.memory.TcpClient(host, port) + +def createAxiPcieDmaStreams(driverPath, streamMap, host='localhost', basePort=8000): + """Provides DMA stream access for AxiPcieCore""" + d = defaultdict(dict) + for lane, dests in streamMap.items(): + for dest in dests: + if driverPath != 'sim': + d[lane][dest] = rogue.hardware.axi.AxiStreamDma(driverPath, (0x100*lane)|dest, True) + else: + d[lane][dest] = rogue.interfaces.stream.TcpClient(host, (basePort+2)+(512*lane)+2*dest) + return d + + + + + + + diff --git a/python/axipcie/_AxiPcieRoot.py b/python/axipcie/_AxiPcieRoot.py new file mode 100644 index 00000000..7e6f7d8c --- /dev/null +++ b/python/axipcie/_AxiPcieRoot.py @@ -0,0 +1,15 @@ +import axipcie as pcie + +import pyrogue as pr +import rogue + +class AxiPcieRoot(pr.Root): + def __init__(self, dev, **kwargs): + super().__init__(**kwargs) + + memMap = rogue.hardware.axi.AxiMemMap(dev) + + self.add(pcie.AxiPcieCore( + memBase = memMap, + useBpi = True, + useSpi = True)) diff --git a/python/axipcie/_PcieAxiVersion.py b/python/axipcie/_PcieAxiVersion.py new file mode 100644 index 00000000..eb2a4090 --- /dev/null +++ b/python/axipcie/_PcieAxiVersion.py @@ -0,0 +1,195 @@ +import pyrogue as pr +import surf.axi as axi + +class PcieAxiVersion(axi.AxiVersion): + def __init__(self, + name = 'AxiVersion', + description = 'AXI-Lite Version Module', + numUserConstants = 0, + **kwargs): + super().__init__( + name = name, + description = description, + **kwargs + ) + + self.add(pr.RemoteVariable( + name = 'DMA_SIZE_G', + offset = 0x400+(4*0), + bitSize = 32, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'Reserved', + offset = 0x400+(4*1), + bitSize = 32, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'DRIVER_TYPE_ID_G', + offset = 0x400+(4*2), + bitSize = 32, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'XIL_DEVICE_G', + offset = 0x400+(4*3), + bitSize = 32, + mode = 'RO', + enum = { + 0x0: 'ULTRASCALE', + 0x1: '7SERIES', + }, + )) + + self.add(pr.RemoteVariable( + name = 'DMA_CLK_FREQ_C', + offset = 0x400+(4*4), + bitSize = 32, + mode = 'RO', + disp = '{:d}', + units = 'Hz', + )) + + self.add(pr.RemoteVariable( + name = 'BOOT_PROM_G', + offset = 0x400+(4*5), + bitSize = 32, + mode = 'RO', + enum = { + 0x0: 'BPI', + 0x1: 'SPIx8', + 0x2: 'SPIx4', + }, + )) + + self.add(pr.RemoteVariable( + name = 'DMA_AXIS_CONFIG_G_TDATA_BYTES_C', + offset = 0x400+(4*6), + bitSize = 8, + bitOffset = 24, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'DMA_AXIS_CONFIG_G_TDEST_BITS_C', + offset = 0x400+(4*6), + bitSize = 4, + bitOffset = 20, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'DMA_AXIS_CONFIG_G_TUSER_BITS_C', + offset = 0x400+(4*6), + bitSize = 4, + bitOffset = 16, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'DMA_AXIS_CONFIG_G_TID_BITS_C', + offset = 0x400+(4*6), + bitSize = 4, + bitOffset = 12, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'DMA_AXIS_CONFIG_G_TKEEP_MODE_C', + offset = 0x400+(4*6), + bitSize = 4, + bitOffset = 8, + mode = 'RO', + enum = { + 0x0: 'TKEEP_NORMAL_C', + 0x1: 'TKEEP_COMP_C', + 0x2: 'TKEEP_FIXED_C', + 0x3: 'TKEEP_COUNT_C', + }, + )) + + self.add(pr.RemoteVariable( + name = 'DMA_AXIS_CONFIG_G_TUSER_MODE_C', + offset = 0x400+(4*6), + bitSize = 4, + bitOffset = 4, + mode = 'RO', + enum = { + 0x0: 'TUSER_NORMAL_C', + 0x1: 'TUSER_FIRST_LAST_C', + 0x2: 'TUSER_LAST_C', + 0x3: 'TUSER_NONE_C', + }, + )) + + self.add(pr.RemoteVariable( + name = 'DMA_AXIS_CONFIG_G_TSTRB_EN_C', + offset = 0x400+(4*6), + bitSize = 1, + bitOffset = 1, + mode = 'RO', + base = pr.Bool, + )) + + self.add(pr.RemoteVariable( + name = 'AppReset', + offset = 0x400+(4*6), + bitSize = 1, + bitOffset = 0, + mode = 'RO', + base = pr.Bool, + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'AXI_PCIE_CONFIG_C_ADDR_WIDTH_C', + offset = 0x400+(4*7), + bitSize = 8, + bitOffset = 24, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'AXI_PCIE_CONFIG_C_DATA_BYTES_C', + offset = 0x400+(4*7), + bitSize = 8, + bitOffset = 16, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'AXI_PCIE_CONFIG_C_ID_BITS_C', + offset = 0x400+(4*7), + bitSize = 8, + bitOffset = 8, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'AXI_PCIE_CONFIG_C_LEN_BITS_C', + offset = 0x400+(4*7), + bitSize = 8, + bitOffset = 0, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = "AppClkFreq", + description = "Application Clock Frequency", + offset = 0x400+(4*8), + units = 'Hz', + disp = '{:d}', + mode = "RO", + pollInterval = 1 + )) diff --git a/python/axipcie/__init__.py b/python/axipcie/__init__.py index 011977fc..1c39758d 100644 --- a/python/axipcie/__init__.py +++ b/python/axipcie/__init__.py @@ -1,5 +1,8 @@ #!/usr/bin/env python -from axipcie._AxiPcieCore import * -from axipcie._AxiPipCore import * from axipcie._AxiGpuAsyncCore import * +from axipcie._AxiPcieCore import * +from axipcie._AxiPcieDma import * +from axipcie._AxiPcieRoot import * +from axipcie._AxiPipCore import * +from axipcie._PcieAxiVersion import * diff --git a/python/axipcie/updateFpga.py b/python/axipcie/updateFpga.py new file mode 100644 index 00000000..b7d07d7d --- /dev/null +++ b/python/axipcie/updateFpga.py @@ -0,0 +1,198 @@ +#!/usr/bin/env python3 +#----------------------------------------------------------------------------- +# Title : BPI/SPIx4/SPIx8 Prom Update +#----------------------------------------------------------------------------- +# File : updatePcieFpga.py +# Created : 2018-06-22 +#----------------------------------------------------------------------------- +# This file is part of the 'axi-pcie-core'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'axi-pcie-core', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr +import os +import importlib + +baseDir = os.path.dirname(os.path.realpath(__file__)) + +print(f"Basedir = {baseDir}") +pr.addLibraryPath(baseDir + '/..') + +# First see if surf is already in the python path +try: + import surf + +# Otherwise assume it is relative in a standard development directory structure +except: + pr.addLibraryPath(baseDir + '/../../../surf/python') + +import sys +import glob +import argparse +import rogue.hardware.axi +import axipcie as pcie +from collections import OrderedDict as odict + +if __name__ == "__main__": + + # Set the argument parser + parser = argparse.ArgumentParser() + + # Add arguments + parser.add_argument( + "--dev", + type = str, + required = False, + default = "/dev/datadev_0", + help = "path to device", + ) + + parser.add_argument( + "--package", + type = str, + default = None, + required = False, + help = "path to images", + ) + + parser.add_argument( + "--path", + type = str, + default = None, + required = False, + help = "path to images", + ) + + parser.add_argument( + "--type", + type = str, + default = None, + required = False, + help = "prom type", + ) + + # Get the arguments + args = parser.parse_args() + + if args.package is not None: + BasePackage = importlib.import_module(args.package) + args.path = BasePackage.ImageDir + + if args.path is None: + print("\nInvalid images directory, use --path or --package args\n") + parser.print_help() + exit() + + # Set base + base = pr.Root(name='PcieTop',description='',pollEn=False) + + # Create the stream interface + memMap = rogue.hardware.axi.AxiMemMap(args.dev) + + # Add Base Device + base.add(pcie.AxiPcieCore( + memBase = memMap, + useBpi = True, + useSpi = True, + )) + + # Start the system + base.start() + + # Read all the variables + base.ReadAll() + + # Create useful pointers + AxiVersion = base.AxiPcieCore.AxiVersion + + if args.type is None: + promType = AxiVersion.BOOT_PROM_G.getDisp() + else: + promType = args.type + + # Case on PROM type + if (promType == 'BPI'): + PROM_PRI = base.AxiPcieCore.AxiMicronP30 + elif (promType == 'SPIx8') or (promType == 'SPIx4'): + PROM_PRI = base.AxiPcieCore.AxiMicronN25Q[0] + if (promType == 'SPIx8'): + PROM_SEC = base.AxiPcieCore.AxiMicronN25Q[1] + else: + raise ValueError('Invalid promType') + + # Printout Current AxiVersion status + print('#########################################') + print('Current Firmware Loaded on the PCIe card:') + print('#########################################') + AxiVersion.printStatus() + print('#########################################') + + # Get a list of images, using .mcs first + imgLst = odict() + + rawLst = glob.glob('{}/*.mcs*'.format(args.path)) + for l in rawLst: + + # Determine suffix + if '.mcs.gz' in l: + suff = 'mcs.gz' + else: + suff = 'mcs' + + # Get basename + l = l.replace('_primary.mcs.gz','') + l = l.replace('_secondary.mcs.gz','') + l = l.replace('_primary.mcs','') + l = l.replace('_secondary.mcs','') + l = l.replace('.mcs.gz','') + l = l.replace('.mcs','') + + # Store entry + imgLst[l] = suff + + # Sort list + imgLst = odict(sorted(imgLst.items(), key=lambda x: x[0])) + + for i,l in enumerate(imgLst.items()): + print('{} : {}'.format(i,l[0])) + + idx = int(input('Enter image to program into the PCIe card\'s PROM: ')) + + ent = list(imgLst.items())[idx] + if (promType == 'SPIx8'): + pri = ent[0] + '_primary.' + ent[1] + sec = ent[0] + '_secondary.' + ent[1] + else: + pri = ent[0] + '.' + ent[1] + + # Load the primary MCS file + PROM_PRI.LoadMcsFile(pri) + + # Update the programing done flag + progDone = PROM_PRI._progDone + + # Check for secondary PROM + if (promType == 'SPIx8'): + # Check if the primary MCS failed + if PROM_PRI._progDone: + # Load the secondary MCS file + PROM_SEC.LoadMcsFile(sec) + # Update the programing done flag + progDone = PROM_PRI._progDone and PROM_SEC._progDone + + # Check if programming was successful + if (progDone): + print('\nReloading FPGA firmware from PROM ....') + AxiVersion.FpgaReload() + print('\nPlease reboot the computer') + else: + print('Failed to program FPGA') + + # Close out + base.stop() + exit() diff --git a/python/updatePcieFpga.py b/python/updatePcieFpga.py deleted file mode 100644 index ef64c84a..00000000 --- a/python/updatePcieFpga.py +++ /dev/null @@ -1,167 +0,0 @@ -#!/usr/bin/env python3 -#----------------------------------------------------------------------------- -# Title : BPI/SPIx4/SPIx8 Prom Update -#----------------------------------------------------------------------------- -# File : updatePcieFpga.py -# Created : 2018-06-22 -#----------------------------------------------------------------------------- -# This file is part of the 'axi-pcie-core'. It is subject to -# the license terms in the LICENSE.txt file found in the top-level directory -# of this distribution and at: -# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -# No part of the 'axi-pcie-core', including this file, may be -# copied, modified, propagated, or distributed except according to the terms -# contained in the LICENSE.txt file. -#----------------------------------------------------------------------------- - -import pyrogue as pr -import os -baseDir = os.path.dirname(os.path.realpath(__file__)) -pr.addLibraryPath(baseDir) -pr.addLibraryPath(baseDir + '/../../surf/python') - -import sys -import glob -import argparse -import rogue.hardware.axi -import axipcie as pcie -from collections import OrderedDict as odict - -# Set the argument parser -parser = argparse.ArgumentParser() - -# Add arguments -parser.add_argument( - "--dev", - type = str, - required = False, - default = "/dev/datadev_0", - help = "path to device", -) - -parser.add_argument( - "--path", - type = str, - required = True, - help = "path to images", -) - -parser.add_argument( - "--type", - type = str, - default = None, - required = False, - help = "prom type", -) - -# Get the arguments -args = parser.parse_args() - -# Set base -base = pr.Root(name='PcieTop',description='') - -# Create the stream interface -memMap = rogue.hardware.axi.AxiMemMap(args.dev) - -# Add Base Device -base.add(pcie.AxiPcieCore( - memBase = memMap, - useBpi = True, - useSpi = True, -)) - -# Start the system -base.start(pollEn=False) - -# Read all the variables -base.ReadAll() - -# Create useful pointers -AxiVersion = base.AxiPcieCore.AxiVersion - -if args.type is None: - promType = AxiVersion.BOOT_PROM_G.getDisp() -else: - promType = args.type - -# Case on PROM type -if (promType == 'BPI'): - PROM_PRI = base.AxiPcieCore.AxiMicronP30 -elif (promType == 'SPIx8') or (promType == 'SPIx4'): - PROM_PRI = base.AxiPcieCore.AxiMicronN25Q[0] - if (promType == 'SPIx8'): - PROM_SEC = base.AxiPcieCore.AxiMicronN25Q[1] -else: - raise ValueError(f'Invalid promType' ) - -# Printout Current AxiVersion status -print('#########################################') -print('Current Firmware Loaded on the PCIe card:') -print('#########################################') -AxiVersion.printStatus() -print('#########################################') - -# Get a list of images, using .mcs first -imgLst = odict() - -rawLst = glob.glob('{}/*.mcs*'.format(args.path)) -for l in rawLst: - - # Determine suffix - if '.mcs.gz' in l: - suff = 'mcs.gz' - else: - suff = 'mcs' - - # Get basename - l = l.replace('_primary.mcs.gz','') - l = l.replace('_secondary.mcs.gz','') - l = l.replace('_primary.mcs','') - l = l.replace('_secondary.mcs','') - l = l.replace('.mcs.gz','') - l = l.replace('.mcs','') - - # Store entry - imgLst[l] = suff - -# Sort list -imgLst = odict(sorted(imgLst.items(), key=lambda x: x[0])) - -for i,l in enumerate(imgLst.items()): - print('{} : {}'.format(i,l[0])) - -idx = int(input('Enter image to program into the PCIe card\'s PROM: ')) - -ent = list(imgLst.items())[idx] -if (promType == 'SPIx8'): - pri = ent[0] + '_primary.' + ent[1] - sec = ent[0] + '_secondary.' + ent[1] -else: - pri = ent[0] + '.' + ent[1] - -# Load the primary MCS file -PROM_PRI.LoadMcsFile(pri) - -# Update the programing done flag -progDone = PROM_PRI._progDone - -# Check for secondary PROM -if (promType == 'SPIx8'): - # Check if the primary MCS failed - if PROM_PRI._progDone: - # Load the secondary MCS file - PROM_SEC.LoadMcsFile(sec) - # Update the programing done flag - progDone = PROM_PRI._progDone and PROM_SEC._progDone - -# Check if programming was successful -if (progDone): - print('\nReloading FPGA firmware from PROM ....') - AxiVersion.FpgaReload() - print('\nPlease reboot the computer') -else: - print('Failed to program FPGA') - -# Close out -base.stop() -exit()