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adc.json
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[
{
"mnemonic": "adc",
"mnemonicPrecise": "adcb",
"opcode": 20,
"opcodeHex": "14",
"operands": [
"al",
"Immediate8"
],
"operandSize": 8,
"operandEncoding": "rm",
"lock": true,
"skipMorm": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcw",
"opcode": 21,
"opcodeHex": "15",
"operands": [
"ax",
"Immediate16"
],
"operandSize": 16,
"operandEncoding": "rm",
"lock": true,
"skipMorm": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcd",
"opcode": 21,
"opcodeHex": "15",
"operands": [
"eax",
"Immediate32"
],
"operandSize": 32,
"operandEncoding": "rm",
"lock": true,
"skipMorm": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcq",
"opcode": 21,
"opcodeHex": "15",
"operands": [
"rax",
"Immediate32"
],
"operandSize": 64,
"operandEncoding": "rm",
"lock": true,
"skipMorm": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcb",
"opcode": 128,
"opcodeHex": "80",
"operands": [
[
"Register8",
"Memory"
],
"Immediate8"
],
"operandSize": 8,
"opcodeExtensionInModrm": 2,
"operandEncoding": "rm",
"lock": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcw",
"opcode": 129,
"opcodeHex": "81",
"operands": [
[
"Register16",
"Memory"
],
"Immediate16"
],
"operandSize": 16,
"opcodeExtensionInModrm": 2,
"operandEncoding": "rm",
"lock": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcd",
"opcode": 129,
"opcodeHex": "81",
"operands": [
[
"Register32",
"Memory"
],
"Immediate32"
],
"operandSize": 32,
"opcodeExtensionInModrm": 2,
"operandEncoding": "rm",
"lock": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcq",
"opcode": 129,
"opcodeHex": "81",
"operands": [
[
"Register64",
"Memory"
],
"Immediate32"
],
"operandSize": 64,
"opcodeExtensionInModrm": 2,
"operandEncoding": "rm",
"lock": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcw",
"opcode": 131,
"opcodeHex": "83",
"operands": [
[
"Register16",
"Memory"
],
"Immediate8"
],
"operandSize": 16,
"opcodeExtensionInModrm": 2,
"operandEncoding": "rm",
"lock": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcd",
"opcode": 131,
"opcodeHex": "83",
"operands": [
[
"Register32",
"Memory"
],
"Immediate8"
],
"operandSize": 32,
"opcodeExtensionInModrm": 2,
"operandEncoding": "rm",
"lock": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcq",
"opcode": 131,
"opcodeHex": "83",
"operands": [
[
"Register64",
"Memory"
],
"Immediate8"
],
"operandSize": 64,
"opcodeExtensionInModrm": 2,
"operandEncoding": "rm",
"lock": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcb",
"opcode": 16,
"opcodeHex": "10",
"operands": [
[
"Register8",
"Memory"
],
"Register8"
],
"operandSize": 8,
"operandEncoding": "mr",
"lock": true,
"setOpcodeDirectionBit": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcb",
"opcode": 18,
"opcodeHex": "12",
"operands": [
"Register8",
[
"Register8",
"Memory"
]
],
"operandSize": 8,
"operandEncoding": "rm",
"lock": true,
"setOpcodeDirectionBit": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcw",
"opcode": 17,
"opcodeHex": "11",
"operands": [
[
"Register16",
"Memory"
],
"Register16"
],
"operandSize": 16,
"operandEncoding": "mr",
"lock": true,
"setOpcodeDirectionBit": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcw",
"opcode": 19,
"opcodeHex": "13",
"operands": [
"Register16",
[
"Register16",
"Memory"
]
],
"operandSize": 16,
"operandEncoding": "rm",
"lock": true,
"setOpcodeDirectionBit": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcd",
"opcode": 17,
"opcodeHex": "11",
"operands": [
[
"Register32",
"Memory"
],
"Register32"
],
"operandSize": 32,
"operandEncoding": "mr",
"lock": true,
"setOpcodeDirectionBit": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcd",
"opcode": 19,
"opcodeHex": "13",
"operands": [
"Register32",
[
"Register32",
"Memory"
]
],
"operandSize": 32,
"operandEncoding": "rm",
"lock": true,
"setOpcodeDirectionBit": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcq",
"opcode": 17,
"opcodeHex": "11",
"operands": [
[
"Register64",
"Memory"
],
"Register64"
],
"operandSize": 64,
"operandEncoding": "mr",
"lock": true,
"setOpcodeDirectionBit": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
},
{
"mnemonic": "adc",
"mnemonicPrecise": "adcq",
"opcode": 19,
"opcodeHex": "13",
"operands": [
"Register64",
[
"Register64",
"Memory"
]
],
"operandSize": 64,
"operandEncoding": "rm",
"lock": true,
"setOpcodeDirectionBit": true,
"modes": [
"REAL",
"PROT",
"COMP",
"LEG",
"X32",
"X64"
]
}
]